CN103532119A - Voltage amplitude-limiting system of antenna signal in electronic tag - Google Patents
Voltage amplitude-limiting system of antenna signal in electronic tag Download PDFInfo
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- CN103532119A CN103532119A CN201210225628.2A CN201210225628A CN103532119A CN 103532119 A CN103532119 A CN 103532119A CN 201210225628 A CN201210225628 A CN 201210225628A CN 103532119 A CN103532119 A CN 103532119A
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Abstract
The invention discloses a voltage amplitude-limiting system of an antenna signal in an electronic tag. The voltage amplitude-limiting system consist of a first N-channel enhanced field effect transistor, a second N-channel enhanced field effect transistor, a third N-channel enhanced field effect transistor, a fourth N-channel enhanced field effect transistor, a fifth resistor, a first capacitor, a second capacitor and a plurality of P-channel enhanced field effect transistor in series connection. To be specific, the plurality of P-channel enhanced field effect transistor in series connection and the first capacitor are connected in parallel to form a series-parallel circuit. One end of a series-parallel branch circuit of the second capacitor and the fifth resistor is connected with a circuit between a drain electrode of the third N-channel enhanced field effect transistor and a drain electrode of the fourth N-channel enhanced field effect transistor; and the other end is connected with a circuit between the plurality of P-channel enhanced field effect transistor in series connection and the fourth resistor. With the structure, when the voltage amplitude limiting of the antenna is realized, the power is not influenced; and the system can be operated conveniently.
Description
Technical field
The present invention relates to radio-frequency technique field, specifically the voltage limiter system of aerial signal in electronic tag.
Background technology
Radio-frequency (RF) identification is current application one of the most contactless Target Recognition, and it has the advantages such as noncontact, read-write is flexible, speed is fast, fail safe is high, is therefore widely used in every field.Radio-frequency recognition system mainly comprises reader and electronic tag, the energy that electronic tag receives reader can be affected by the angle between operating distance and reader antenna, the voltage that electronic tag senses may be larger, so must there be independent modular circuit to realize amplitude limit, by limiting voltage within limits, breakdown to prevent receiving metal-oxide-semiconductor grid.The simplest directly measure of amplitude limit is to reduce coupling coefficient, people usually reduce coupling coefficient by the operating distance of adjustment reader and electronic tag or the input capacitance of adjustment electronic tag now, wherein, adopting the operating distance of adjustment reader and electronic tag is to be difficult to hold for operating personnel, and the method does not gear to actual circumstances; Change the input capacitance of electronic tag, be to change resonance frequency, reduce coupling coefficient, the power transmitting in electronic tag also can reduce, in large scale integrated circuit design, the realization of electric capacity can take larger chip area, and the parameter of electric capacity is floated relatively large.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of convenient operation to control, simple in structure, and when carrying out voltage amplitude limit, can not affect the voltage limiter system of aerial signal in the electronic tag of delivering power.
Object of the present invention is achieved through the following technical solutions: the voltage limiter system of aerial signal in electronic tag, comprise a N channel enhancement field effect transistor, the 2nd N channel enhancement field effect transistor, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor, the P-channel enhancement type field effect transistor of the first electric capacity and a plurality of series connection, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor and a plurality of P-channel enhancement type field effect transistor are the metal-oxide-semiconductor that diode connects, the drain electrode of described the 3rd N channel enhancement field effect transistor is connected with a N channel enhancement field effect transistor drain electrode with the 4th N channel enhancement field effect transistor drain electrode respectively with source electrode, the drain electrode of the 2nd N channel enhancement field effect transistor is connected with the 4th N channel enhancement field effect transistor source electrode, the one N channel enhancement field effect transistor source electrode and the 2nd N channel enhancement field effect transistor source grounding, connect respectively and form connection in series-parallel circuit with the first Capacitance parallel connection after the 3rd resistance and the 4th resistance in the series arm two ends of the P-channel enhancement type field effect transistor of described a plurality of series connection, connection between this connection in series-parallel circuit one end and the drain electrode of the 3rd N channel enhancement field effect transistor and the drain electrode of the 4th N channel enhancement field effect transistor, its other end ground connection, the grid of a described N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor all with a plurality of P-channel enhancement type field effect transistor of connecting and the 4th resistance between connection, described the second electric capacity is connected with the 5th resistance, connection between the drain electrode of series arm one end of the second electric capacity and the 5th resistance and the 3rd N channel enhancement field effect transistor and the drain electrode of the 4th N channel enhancement field effect transistor, the connection between its other end and a plurality of P-channel enhancement type field effect transistor of connecting and the 4th resistance.The metal-oxide-semiconductor that in the present invention, diode connects is that the grid of metal-oxide-semiconductor and source electrode are linked together, because metal-oxide-semiconductor exists leakage current under certain voltage, so the metal-oxide-semiconductor that in the present invention, diode connects is used for simulating the resistance that resistance is very large, and can realize the control to resistance by adjusting the parameter of metal-oxide-semiconductor.
On circuit between a described N channel enhancement field effect transistor drain electrode and the 3rd N channel enhancement field effect transistor source electrode, be connected with the first resistance; On circuit between described the 2nd N channel enhancement field effect transistor drain electrode and the 4th N channel enhancement field effect transistor source electrode, be connected with the second resistance.
As preferably, the quantity of described P-channel enhancement type field effect transistor is five.
The present invention is when application, a signal input part of antenna is connected on the circuit between the first resistance and N channel enhancement field effect transistor drain electrode, another signal input part of antenna is connected on the circuit between the second resistance and the drain electrode of the 2nd N channel enhancement field effect transistor, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor and the first electric capacity are used for the radiofrequency signal of sampling, the 3rd resistance, the P-channel enhancement type field effect transistor of the 4th resistance and a plurality of series connection forms with reference to controlling voltage, the one N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor are leak-off pipe, the one N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor are connected in parallel on antenna ends and carry out amplitude limit shunting.When the signal of sampling is during higher than reference level, the electric current of the 4th resistance of flowing through increases, therefore the current potential of controlling a N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor grid improves, increase the ducting capacity of a N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor, the electric current of the N channel enhancement field effect transistor of flowing through and the 2nd N channel enhancement field effect transistor increases, reduce the pay(useful) load of label antenna, thus the voltage amplitude of restriction aerial signal.The connection in series-parallel circuit that in the present invention, the P-channel enhancement type field effect transistor of the 3rd resistance, the 4th resistance, the first electric capacity and a plurality of series connection forms is low-pass filtering loop, it changes and produces reaction low frequency signal, this low-pass filtering circuit feedback is adjusted the conducting degree of a N channel enhancement field effect transistor and the 2nd N channel enhancement field effect transistor, thereby while guaranteeing that the present invention applies, voltage is stable; The 5th resistance and the second electric capacity form high pass path, and rapid reflection is made in its sudden change to received signal, with this, increases amplitude limit ability.
Compared with prior art, the present invention has following beneficial effect: the present invention includes a N channel enhancement field effect transistor, the 2nd N channel enhancement field effect transistor, the 3rd N channel enhancement field effect transistor, the 4th N channel enhancement field effect transistor, the 5th resistance, the first electric capacity, the P-channel enhancement type field effect transistor of the second electric capacity and a plurality of series connection, the present invention uses the quantity of electronic component few, overall structure is simple, while being integrated in module, volume is little, be convenient to realize, cost is low, and the present invention passes through to improve the grid voltage of a N channel enhancement field effect transistor and the second enhancement mode field effect transistor when application, can not exert an influence to power, at input voltage, make shunt circuit conducting in parallel during higher than certain voltage value, make the electric current of circuit become large, thereby make voltage voltage stabilizing in certain scope.
Accompanying drawing explanation
Fig. 1 is the structural representation of the embodiment of the present invention.
In accompanying drawing, the corresponding name of Reference numeral is called: N1-one N channel enhancement field effect transistor, N2-two N channel enhancement field effect transistor, N3-three N channel enhancement field effect transistor, N4-four N channel enhancement field effect transistor, P1-the first P-channel enhancement type field effect transistor, P2-the second P-channel enhancement type field effect transistor, P3-three P-channel enhancement type field effect transistor, P4-four P-channel enhancement type field effect transistor, P5-five P-channel enhancement type field effect transistor, C1-the first electric capacity, C2-the second electric capacity, R1-the first resistance, R2-the second resistance, R3-three resistance, R4-four resistance, R5-five resistance, Ant1-the first antenna signal input part, Ant2-the second antenna signal input part.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment:
As shown in Figure 1, the voltage limiter system of aerial signal in electronic tag, comprises shell and internal circuit is in the enclosure set, internal circuit comprises a N channel enhancement field effect transistor N1, the 2nd N channel enhancement field effect transistor N2, the 3rd N channel enhancement field effect transistor N3, the 4th N channel enhancement field effect transistor N4, the 5th resistance R 5, the first capacitor C 1, the P-channel enhancement type field effect transistor of the second capacitor C 2 and a plurality of series connection, wherein, the 3rd N channel enhancement field effect transistor N3, the 4th N channel enhancement field effect transistor N4 and a plurality of P-channel enhancement type field effect transistor are the metal-oxide-semiconductor that diode connects, the metal-oxide-semiconductor connecting at this diode is that the grid in metal-oxide-semiconductor is connected with source electrode, the quantity of P-channel enhancement type field effect transistor is preferably five, is the first P-channel enhancement type field effect transistor P1 of series connection, the second P-channel enhancement type field effect transistor P2, the 3rd P-channel enhancement type field effect transistor P3, the 4th P-channel enhancement type field effect transistor P4 and the 5th P-channel enhancement type field effect transistor P5.
The drain electrode of the 3rd N channel enhancement field effect transistor N3 is connected with a N channel enhancement field effect transistor N1 drain electrode with the 4th N channel enhancement field effect transistor N4 drain electrode respectively with source electrode, the drain electrode of the 2nd N channel enhancement field effect transistor N2 is connected with the 4th N channel enhancement field effect transistor N4 source electrode, the one N channel enhancement field effect transistor N1 source electrode and the 2nd N channel enhancement field effect transistor N2 source grounding, on circuit between the one N channel enhancement field effect transistor N1 drain electrode and the 3rd N channel enhancement field effect transistor N3 source electrode, be connected with the first resistance R 1, on circuit between the 2nd N channel enhancement field effect transistor N2 drain electrode and the 4th N channel enhancement field effect transistor N4 source electrode, be connected with the second resistance R 2.Connect respectively after the 3rd resistance R 3 and the 4th resistance R 4 and the first capacitor C 1 formation in parallel connection in series-parallel circuit in the series arm two ends of the P-channel enhancement type field effect transistor of five series connection, connection between this connection in series-parallel circuit one end and the 3rd N channel enhancement field effect transistor N3 drain electrode and the 4th N channel enhancement field effect transistor N4 drain electrode, its other end ground connection.The grid of the one N channel enhancement field effect transistor N1 and the 2nd N channel enhancement field effect transistor N2 all with a plurality of P-channel enhancement type field effect transistor of connecting and the 4th resistance R 4 between connection.The second capacitor C 2 is connected with the 5th resistance R 5, connection between series arm one end of the second capacitor C 2 and the 5th resistance R 5 and the 3rd N channel enhancement field effect transistor N3 drain electrode and the 4th N channel enhancement field effect transistor N4 drain electrode, the connection between its other end and a plurality of P-channel enhancement type field effect transistor of connecting and the 4th resistance R 4.
On circuit between the first resistance R 1 and N channel enhancement field effect transistor N1 drain electrode, be connected with the first antenna signal input part Ant1, on the circuit between the second resistance R 2 and the 2nd N channel enhancement field effect transistor N2 drain electrode, be connected with the second antenna signal input part Ant2.
As mentioned above, can well realize the present invention.
Claims (3)
1. the voltage limiter system of aerial signal in electronic tag, it is characterized in that: comprise a N channel enhancement field effect transistor (N1), the 2nd N channel enhancement field effect transistor (N2), the 3rd N channel enhancement field effect transistor (N3), the 4th N channel enhancement field effect transistor (N4), the 5th resistance (R5), the first electric capacity (C1), the P-channel enhancement type field effect transistor of the second electric capacity (C2) and a plurality of series connection, the 3rd N channel enhancement field effect transistor (N3), the 4th N channel enhancement field effect transistor (N4) and a plurality of P-channel enhancement type field effect transistor are the metal-oxide-semiconductor that diode connects, the drain electrode of described the 3rd N channel enhancement field effect transistor (N3) is connected with N channel enhancement field effect transistor (N1) drain electrode with the 4th N channel enhancement field effect transistor (N4) drain electrode respectively with source electrode, the drain electrode of the 2nd N channel enhancement field effect transistor (N2) is connected with the 4th N channel enhancement field effect transistor (N4) source electrode, the one N channel enhancement field effect transistor (N1) source electrode and the 2nd N channel enhancement field effect transistor (N2) source grounding, connect respectively after the 3rd resistance (R3) and the 4th resistance (R4) and the first electric capacity (C1) formation in parallel connection in series-parallel circuit in the series arm two ends of the P-channel enhancement type field effect transistor of described a plurality of series connection, connection between this connection in series-parallel circuit one end and the drain electrode of the 3rd N channel enhancement field effect transistor (N3) and the drain electrode of the 4th N channel enhancement field effect transistor (N4), its other end ground connection, a described N channel enhancement field effect transistor (N1) and the 2nd both grids of N channel enhancement field effect transistor (N2) all with a plurality of P-channel enhancement type field effect transistor of connecting and the 4th resistance (R4) between connection, described the second electric capacity (C2) is connected with the 5th resistance (R5), connection between the drain electrode of series arm one end of the second electric capacity (C2) and the 5th resistance (R5) and the 3rd N channel enhancement field effect transistor (N3) and the 4th N channel enhancement field effect transistor (N4) drain, the connection between its other end and a plurality of P-channel enhancement type field effect transistor of connecting and the 4th resistance (R4).
2. the voltage limiter system of aerial signal in electronic tag according to claim 1, is characterized in that: on the circuit between described N channel enhancement field effect transistor (N1) drain electrode and the 3rd N channel enhancement field effect transistor (N3) source electrode, be connected with the first resistance (R1); On circuit between described the 2nd N channel enhancement field effect transistor (N2) drain electrode and the 4th N channel enhancement field effect transistor (N4) source electrode, be connected with the second resistance (R2).
3. the voltage limiter system of aerial signal in electronic tag according to claim 1 and 2, is characterized in that: the quantity of described P-channel enhancement type field effect transistor is five.
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CN111264034A (en) * | 2017-10-25 | 2020-06-09 | 日本精机株式会社 | Receiving circuit and communication device |
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CN101102040A (en) * | 2006-07-06 | 2008-01-09 | 上海华虹Nec电子有限公司 | High-voltage I/O Buffer circuit structure |
CN102110238A (en) * | 2009-12-23 | 2011-06-29 | 北京中电华大电子设计有限责任公司 | Adaptive impedance matching ultrahigh-frequency passive electronic tag interface circuit |
CN202663107U (en) * | 2012-07-03 | 2013-01-09 | 成都市宏山科技有限公司 | Voltage amplitude limiting system of antenna signal in radio frequency identification |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN101102040A (en) * | 2006-07-06 | 2008-01-09 | 上海华虹Nec电子有限公司 | High-voltage I/O Buffer circuit structure |
CN102110238A (en) * | 2009-12-23 | 2011-06-29 | 北京中电华大电子设计有限责任公司 | Adaptive impedance matching ultrahigh-frequency passive electronic tag interface circuit |
CN202663107U (en) * | 2012-07-03 | 2013-01-09 | 成都市宏山科技有限公司 | Voltage amplitude limiting system of antenna signal in radio frequency identification |
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CN111264034A (en) * | 2017-10-25 | 2020-06-09 | 日本精机株式会社 | Receiving circuit and communication device |
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