CN202677432U

CN202677432U - System for modulating load voltage in electronic tag

Info

Publication number: CN202677432U
Application number: CN 201220316406
Authority: CN
Inventors: 曾维亮
Original assignee: Chengdu Hongshan Technology Co Ltd
Current assignee: Chengdu Hongshan Technology Co Ltd
Priority date: 2012-07-03
Filing date: 2012-07-03
Publication date: 2013-01-16
Anticipated expiration: 2022-07-03

Abstract

The utility model discloses a system for modulating load voltage in an electronic tag, comprising four NMOS transistors, two PMOS transistors and two NOT gates, wherein the sources of the four NMOS transistors are grounded; the grids of the first NMOS transistor, the second NMOS transistor and the second PMOS transistor are connected with the line between the source of the first PMOS transistor and the drain of the third NMOS transistor; the grid of the first PMOS transistor is connected with the line between the source of the second PMOS transistor and the drain of the fourth NMOS transistor; the second NOT gate is connected with the grid of the fourth NMOS transistor; and the grid of the third NMOS transistor is connected with the line between the first NOT gate and the second NOT gate. The system for modulating load voltage in an electronic tag uses the above structure, thus being simple in the whole structure, saving the cost, and improving the induction voltage of the antenna of a reader without increasing the cost and the volume of a reader at the same time.

Description

The system of modulation load voltage in the electronic tag

Technical field

The utility model relates to the radio-frequency technique field, specifically the system of modulation load voltage in the electronic tag.

Background technology

Radio-frequency (RF) identification is one of the most contactless Target Recognition of current application, and it has the advantages such as noncontact, read-write is flexible, speed is fast, security is high, therefore is widely used in every field.Coupling in the existing radio-frequency recognition system between reader and the electronic label antenna is very weak, the voltage fluctuation of the signal that receives on the reader antenna is less than the output voltage of reader, system such as 13.56MHz, when reader antenna voltage is approximately 100V, can only obtain the useful signal of about 10mv.In order to make reader detect these very variations of small voltage, have complex circuit designs on the reader now, this has just increased volume and the cost of reader.

The utility model content

The purpose of this utility model is to overcome the deficiencies in the prior art, provides a kind of simple in structure, and cost is low, and can improve the system of modulation load voltage in the electronic tag of reader antenna induced voltage.

The purpose of this utility model is achieved through the following technical solutions: the system of modulation load voltage in the electronic tag comprises four NMOS transistors, two PMOS transistors and two not gates, the source grounding of described four NMOS transistors; Described four NMOS transistors comprises the first nmos pass transistor, the second nmos pass transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor, described PMOS transistor comprises a PMOS transistor and the 2nd PMOS transistor, the one PMOS transistor source is connected with the 3rd nmos transistor drain, the first nmos pass transistor, the second nmos pass transistor and the 2nd PMOS transistor three's grid all is connected on the circuit between a PMOS transistor source and the 3rd nmos transistor drain, described the 2nd PMOS transistor source is connected with the 4th nmos transistor drain, and a PMOS transistor gate is connected on the circuit between the 2nd PMOS transistor source and the 4th nmos transistor drain; Described not gate comprises the first not gate and the second not gate, the input end of described the second not gate is connected with the output terminal of the first not gate, the output terminal of the second not gate is connected with the 4th nmos pass transistor grid, the connection between described the 3rd nmos pass transistor grid and the first not gate and the second not gate.

The drain electrode of described the first nmos pass transistor is connected with the first resistance, and the drain electrode of described the second nmos pass transistor is connected with the second resistance.The other end that the utility model first resistance when using connects the drain electrode end of the first nmos pass transistor relatively is a rf access point, the other end that the second resistance connects the drain electrode end of the second nmos pass transistor relatively is a rf access point, and the utility model two rf access points when using all are connected on the antenna of electronic tag.

The input end of described the first not gate is connected with the data receiver port.Data receiver port of the present utility model receives the data that electronic tag sends when using.

Compared with prior art, the utlity model has following beneficial effect: the utility model comprises four NMOS transistors, two PMOS transistors, two not gates and two resistance, one-piece construction is simple, be convenient to realize, cost is low, wherein, the first nmos pass transistor in the four NMOS transistors and the second nmos pass transistor form the load-modulate switching tube, the first resistance and the second resistance are modulated resistance, the first resistance and the second resistance are parallel to the electronic label antenna two ends, when the input end of the first not gate receives low level, the first nmos pass transistor and the judgement of the second nmos pass transistor, the antenna working current is constant, when the input end of the first not gate receives high level, the first nmos pass transistor and the second nmos pass transistor conducting, the antenna equivalent load resistance reduces, and antenna current increases, induced voltage reduces, so, the induced voltage of reader antenna raises, and can avoid setting up at reader the circuit of identification small voltage signal by the utility model, saves the reader cost.

Description of drawings

Fig. 1 is the structural representation of the utility model embodiment.

The corresponding name of Reference numeral is called in the accompanying drawing: N1-first nmos pass transistor, N2-second nmos pass transistor, N3-the 3rd nmos pass transistor, N4-the 4th nmos pass transistor, P1-the one PMOS transistor, P2-the 2nd PMOS transistor, Data-data receiver port, the 1-the first not gate, the 2-the second not gate, R1-first resistance, R2-second resistance.

Embodiment

The utility model is described in further detail below in conjunction with embodiment and accompanying drawing, but embodiment of the present utility model is not limited to this.

Embodiment:

As shown in Figure 1, the system of modulation load voltage in the electronic tag comprises shell and setting internal circuit in the enclosure, and internal circuit comprises four NMOS transistors and two PMOS transistors, wherein, and the source grounding of four NMOS transistors.Four NMOS transistors is respectively the first nmos pass transistor N1, the second nmos pass transistor N2, the 3rd nmos pass transistor N3 and the 4th nmos pass transistor N4, and two PMOS transistors are respectively a PMOS transistor P1 and the 2nd PMOS transistor P2.The one PMOS transistor P1 source electrode and the 3rd nmos pass transistor N3 drain electrode is connected, and the first nmos pass transistor N1, the second nmos pass transistor N2 and the 2nd PMOS transistor P2 three's grid all is connected on a PMOS transistor P1 source electrode and the 3rd nmos pass transistor N3 circuit between draining.The 2nd PMOS transistor P2 source electrode is connected with the 4th nmos pass transistor N4 drain electrode, the one PMOS transistor P1 grid is connected on the circuit between the 2nd PMOS transistor P2 source electrode and the 4th nmos pass transistor N4 drain electrode, and PMOS transistor P1 drain electrode and the 2nd PMOS transistor P2 drain and all be connected on the power supply.When using, the drain electrode of the first nmos pass transistor N1 is connected with the first resistance R 1, the drain electrode of the second nmos pass transistor N2 be connected with the other end that the second resistance R 2, the first resistance R 1 connect the first nmos pass transistor N1 drain electrode end relatively connect and be connected resistance R 2 relatively the other ends of connection the second nmos pass transistor N2 drain electrode ends all be connected on the antenna of electronic tag.

The system of modulation load voltage in the electronic tag, also comprise the first not gate 1 and the second not gate 2, wherein, the input end of the second not gate 2 is connected with the output terminal of the first not gate, the output terminal of the second not gate 2 is connected with the 4th nmos pass transistor N4 grid, connection between the 3rd nmos pass transistor N3 grid and the first not gate 1 and the second not gate 2, the input end of the first not gate 1 are connected with and receive the data receiver port Data that electronic tag sends data.

As mentioned above, then can well realize the utility model.

Claims

1. the system of modulation load voltage in the electronic tag is characterized in that: comprise four NMOS transistors, two PMOS transistors and two not gates, the source grounding of described four NMOS transistors; Described four NMOS transistors comprises the first nmos pass transistor (N1), the second nmos pass transistor (N2), the 3rd nmos pass transistor (N3) and the 4th nmos pass transistor (N4), described PMOS transistor comprises a PMOS transistor (P1) and the 2nd PMOS transistor (P2), the one PMOS transistor (P1) source electrode is connected with the 3rd nmos pass transistor (N3) drain electrode, the first nmos pass transistor (N1), the second nmos pass transistor (N2) and the 2nd PMOS transistor (P2) three's grid all is connected on the circuit between the drain electrode of PMOS transistor (P1) source electrode and the 3rd nmos pass transistor (N3), the drain electrode of described the 2nd PMOS transistor (P2) source electrode and the 4th nmos pass transistor (N4) is connected, and PMOS transistor (P1) grid is connected on the 2nd PMOS transistor (P2) source electrode and the 4th nmos pass transistor (N4) circuit between draining; Described not gate comprises the first not gate (1) and the second not gate (2), the input end of described the second not gate (2) is connected with the output terminal of the first not gate (1), the output terminal of the second not gate (2) is connected with the 4th nmos pass transistor (N4) grid, the connection between described the 3rd nmos pass transistor (N3) grid and the first not gate (1) and the second not gate (2).

2. the system of modulation load voltage in the electronic tag according to claim 1, it is characterized in that: the drain electrode of described the first nmos pass transistor (N1) is connected with the first resistance (R1), and the drain electrode of described the second nmos pass transistor (N2) is connected with the second resistance (R2).

3. the system of modulation load voltage in the electronic tag according to claim 1 and 2, it is characterized in that: the input end of described the first not gate (1) is connected with data receiver port (Data).