CN103515320A - Semiconductor device and forming method thereof - Google Patents
Semiconductor device and forming method thereof Download PDFInfo
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- CN103515320A CN103515320A CN201210206464.9A CN201210206464A CN103515320A CN 103515320 A CN103515320 A CN 103515320A CN 201210206464 A CN201210206464 A CN 201210206464A CN 103515320 A CN103515320 A CN 103515320A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 239000000463 material Substances 0.000 claims description 37
- 239000000758 substrate Substances 0.000 claims description 32
- 230000015572 biosynthetic process Effects 0.000 claims description 31
- 238000005137 deposition process Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 4
- 239000012495 reaction gas Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 abstract description 9
- 230000001939 inductive effect Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Condensed Matter Physics & Semiconductors (AREA)
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Abstract
The invention discloses a semiconductor device and a forming method thereof. A groove is formed between two adjacent side walls of two adjacent gate structures, and the groove has side walls which are gradually narrow from top to bottom, namely, the depth-to-width ratio of the groove is reduced to a certain extent. A stress top cover layer needing to be deposited in a deep position of the groove is reduced, and the stress top cover layer can be easily deposited in a deep position of the groove, namely, the problem of air gap in deposition of the stress top cover layer in the groove is avoided. Therefore, the stress top cover layer is enabled to play a good role of stress inducing, and the performance of the device is improved.
Description
Technical field
The present invention relates to integrated circuit and manufacture field, particularly a kind of semiconductor device and forming method thereof.
Background technology
In advanced complementary metal oxide semiconductors (CMOS) (CMOS) industry, the characteristic size of device is constantly being dwindled, however the certainty such as various current material, technique exist physics limit, such as short-channel effect, hot carrier's effects etc. are all the bottlenecks of limiting device performance.In the face of these difficult problems, adopt new material, optimized production process is just extremely urgent.
Find after deliberation ， channel region stress application, just can improve electron mobility, thereby solve the difficult problems such as short-channel effect, improve the performance of device.Such as stress memory technique (stress memorization technology, SMT), the way of tradition SMT technique is: at transistor surface deposition stress cap layer, and carry out annealing process, change gate electrode amorphous silicon structures, by stress-induced, to substrate, afterwards stress cap layer is removed.This technology can be improved the electric property of N NMOS N-channel MOS N field effect transistor (NMOS) preferably.
Although the effect that this technology improves performance is pretty good, because variety of issue appears in being limited in the process that forms stress cap layer of size.As shown in Figure 1, it is the schematic diagram that existing technique forms stress cap layer, forms grid structure 101 on substrate 100, near grid structure 101, forms side wall 102, between adjacent two side walls 102 that adjacent two grid structures are 101, is groove.Wherein side wall 102 is that (whole is rectangular shape to round rectangle shape, wherein one jiao is fillet, in this case a jiao away from grid structure 101 and substrate 100 is fillet, other San Gejiaowei right angles), the sidewall of groove (be side wall 102 away from its near the one side of grid structure 101) for vertical.Cover afterwards stress cap layer 103, because distance is very little, the depth-to-width ratio of groove is very large conventionally, therefore, due to the characteristic of depositing operation, easily makes the deposition of stress cap layer 103 in groove occur space 104.Due to the existence in space 104, by being unfavorable for stress-induced to substrate by stress cap layer 103, can not reach and form stress cap layer 103 needed objects.Therefore, how avoiding the appearance in space in stress cap layer, is a problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of formation method of semiconductor device, to solve, in prior art, form the problem that space easily appears in stress cap layer.
For solving the problems of the technologies described above, the invention provides a kind of formation method of semiconductor device, comprising:
Substrate is provided;
On described substrate, form a plurality of grid structures;
In each grid structure both sides, forming side wall, is groove between adjacent two side walls between adjacent two grid structures, and described groove has top-down gradually narrow sidewall.
Further, for the formation method of described semiconductor device, the technique that forms side wall in each grid structure both sides comprises the steps:
Form the first material layer, substrate and grid structure described in described the first layer of material covers;
Described in etching, the first material layer forms the first side wall;
Form the second material layer, substrate, the first side wall and grid structure described in described the second layer of material covers;
The second material layer described in etching, forms the second side wall.
Further, for the formation method of described semiconductor device, the thickness of described the first side wall is 50 ~ 200 dusts.
Further, for the formation method of described semiconductor device, the height of described the first side wall is lower than the height of described grid structure.
Further, for the formation method of described semiconductor device, the thickness of described the second side wall is 50 ~ 200 dusts.
Further, for the formation method of described semiconductor device, the height of described the second side wall equals the height of described grid structure.
Further, for the formation method of described semiconductor device, described the first material layer is the silicon nitride layer forming through atom layer deposition process.
Further, for the formation method of described semiconductor device, described the second material layer is the silicon nitride layer forming through atom layer deposition process.
Further, for the formation method of described semiconductor device, the process conditions of described formation the first material layer and the second material layer are: pressure 5 ~ 10Torr, 500 ~ 600 ℃ of temperature, power 100 ~ 200W.
Further, for the formation method of described semiconductor device, the reacting gas of described atom layer deposition process includes SiH
2cl
2, NH
3, N
2.
Further, for the formation method of described semiconductor device, described reaction gas flow is 50 ~ 1000sccm.
Further, the formation method for described semiconductor device, also comprises: after forming the second side wall, form stress cap layer, described stress cap layer covers described substrate, the second side wall and grid structure.
The present invention proposes a kind of semiconductor device, it is characterized in that, comprising:
Substrate, has a plurality of grid structures on described substrate;
Near the groove between the side wall of described grid structure and the side wall of neighboring gates structure, described groove has top-down gradually narrow sidewall.
Compared with prior art, in the formation method of semiconductor device provided by the invention, between adjacent two side walls between adjacent two grid structures, it is groove, the gradually narrow sidewall of described groove between having from top to bottom, reduced to a certain extent the depth-to-width ratio of groove, make in groove the stress cap layer of putting required deposition compared with deep-seated reduce, make thus groove put and be easy to deposit stress cap layer compared with deep-seated, avoided the deposition of stress cap layer in groove to occur the problem in space, thereby can make stress cap layer play the effect of preferably bringing out stress, improved the performance of device.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of each ATM layer relationsATM after existing technique formation stress cap layer;
Fig. 2 ~ Fig. 6 is the process schematic diagram that the embodiment of the present invention forms semiconductor device.
Embodiment
Below in conjunction with the drawings and specific embodiments, semiconductor device provided by the invention and forming method thereof is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 2, substrate 200 is provided, such as silicon substrate etc., form a plurality of grid structures 201 on described substrate 200, described grid structure 201 can utilize any method in existing technique to form.On described substrate 200, form the first material layer 202, described substrate 200 and grid structure 201 are covered by the first material layer 202.Wherein, described the first material layer 202 is silicon nitride (SiN) layer, can form through ald (atomic layer deposition, ALD) technique, or form through boiler tube technique.In the present embodiment, adopt atom layer deposition process, its process conditions are: pressure 5 ~ 10Torr, 500 ~ 600 ℃ of temperature, power 100 ~ 200W.The reacting gas of described atom layer deposition process comprises dichlorosilane (SiH
2cl
2), ammonia (NH
3), nitrogen (N
2).Described reaction gas flow is 50 ~ 1000sccm, can be preferably 50 ~ 100sccm.The thickness of the first material layer 202 is 50 ~ 200 dusts, preferred, can be 100 ~ 120 dusts.
Please refer to Fig. 3, the first material layer described in etching, removal is positioned on described substrate 200, part first material layer of whole and grid structure 201 both sides of grid structure 201 upper surfaces, form the first side wall 300, described the first side wall 300 near described grid structure 201 and described substrate 200, the height of described the first side wall 300 is lower than the height of described grid structure 201, the thickness of described the first side wall 300 is 50 ~ 200 dusts, preferably, can be 100 ~ 120 dusts, described the first side wall 300 be shaped as round rectangle shape (herein with background technology in related be identical concept, a jiao away from grid structure 201 and substrate 200 is fillet, other San Gejiaowei right angles.But, because the cross-sectional width of formed the first side wall 300 is less, therefore, in figure, show as near grid structure 201 and away from a jiao of substrate 200 due to the slightly narrow wedge angle that becomes of width, near substrate 200Liang Ge Jiao Wei right angle).Wherein, etching technics can adopt existing dry etching or wet etching, can adopt gate oxide (therefore more common not shown) as etching stop layer.
Please refer to Fig. 4, form the second material layer 400, described the second material layer 400 covers described substrate 200, the first side wall 300 and grid structure 201.Wherein, described the second material layer 400 is silicon nitride layer, can form through atom layer deposition process, or form through boiler tube technique.In the present embodiment, adopt atom layer deposition process, its process conditions are: pressure 5 ~ 10Torr, 500 ~ 600 ℃ of temperature, power 100 ~ 200W.The reacting gas of described atom layer deposition process comprises SiH
2cl
2, NH
3, N
2.Described reaction gas flow is 50 ~ 1000sccm, preferred, can be 50 ~ 100sccm.The thickness of the first material layer 202 is 50 ~ 200 dusts, preferred, can be 100 ~ 120 dusts.
Then, please refer to Fig. 5, the second material layer described in etching, removes and is positioned on described substrate 200 and the second material layer of grid structure 201 upper surfaces, forms the second side wall 500, the first side walls 300 and the second side wall 500 in conjunction with forming required side wall 501.Wherein, etching technics can adopt existing dry etching or wet etching.The height of described the second side wall 500 equals the height of described grid structure 201, and the thickness of described the second side wall 500 is 50 ~ 200 dusts, preferred, can be 100 ~ 120 dusts.Known in Fig. 5, between adjacent two side walls 501 that adjacent two grid structures are 201, it is groove 503, described groove 503 have top-down gradually narrow sidewall (be side wall 501 away from its near the one side of grid structure 201, this is the existence due to the first side wall 300, therefore the second side wall 500 will be easy to have certain angle of inclination after forming, and due to the existence at this angle of inclination, groove 503 just has top-down gradually narrow sidewall).Preferably, the sidewall of described groove 503 has 85 ° ~ 86° inclination angle 502, preferred, can be 85.5 °.Follow-up depositing operation is convenient at described inclination angle 502, can avoid the dark height of existing technique further groove larger than very, and the problem in space appears in the deposition of stress cap layer in groove.
Concrete, please refer to Fig. 6, form stress cap layer 600, described stress cap layer 600 covers described substrate 200, the second side wall 500 and grid structure 201, visible, stress cap layer 600 depositions in the groove between adjacent side wall 501 are good, and stress cap layer 600 is interior very close to each other.Wherein, described stress cap layer 600 is nitride, forming technique can be chemical vapor deposition (CVD) technique, preferably, can before forming stress cap layer 600, be pre-formed one deck buffer oxide layer (not shown), to avoid 600 pairs of grid structures 201 of stress cap layer to cause unnecessary destruction, also can be as etching stop layer when follow-up removal stress cap layer 600.
Afterwards, carry out annealing process, the stress memory bringing due to formation stress cap layer, among described substrate, is improved to the electron mobility of channel region, improve the electric property of device.Follow-uply continue to remove other techniques such as stress cap layer, the application does not repeat this.
Above-mentioned formed the first material layer and the second material layer, its thickness sum should with traditional handicraft in only to deposit the thickness of a material layer suitable, to avoid difference in thickness compared with large and cause critical size (CD) to occur larger change, to actual production, make troubles.Nature, described semiconductor device is after etching forms side wall, and the final critical size of device also should to have the device of round rectangle shape side wall close with tradition, and what be convenient to subsequent technique carries out and ensures the overall performance of device smoothly.
In the formation method of the semiconductor device that above-described embodiment provides, between adjacent two side walls between adjacent two grid structures, it is groove, the gradually narrow sidewall of described groove between having from top to bottom, reduced to a certain extent the depth-to-width ratio of groove, make in groove the stress cap layer of putting required deposition compared with deep-seated reduce, make thus groove put and be easy to deposit stress cap layer compared with deep-seated, avoided the deposition of stress cap layer in groove to occur the problem in space, thereby can make stress cap layer play the effect of preferably bringing out stress, improve the performance of device.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these change and modification.
Claims (13)
1. a formation method for semiconductor device, is characterized in that, comprising:
Substrate is provided;
On described substrate, form a plurality of grid structures;
In each grid structure both sides, forming side wall, is groove between adjacent two side walls between adjacent two grid structures, and described groove has top-down gradually narrow sidewall.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the technique that forms side wall in each grid structure both sides comprises the steps:
Form the first material layer, substrate and grid structure described in described the first layer of material covers;
Described in etching, the first material layer forms the first side wall;
Form the second material layer, substrate, the first side wall and grid structure described in described the second layer of material covers;
The second material layer described in etching, forms the second side wall.
3. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the thickness of described the first side wall is 50 ~ 200 dusts.
4. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the height of described the first side wall is lower than the height of described grid structure.
5. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the thickness of described the second side wall is 50 ~ 200 dusts.
6. the formation method of semiconductor device as claimed in claim 2, is characterized in that, the height of described the second side wall equals the height of described grid structure.
7. the formation method of semiconductor device as claimed in claim 2, is characterized in that, described the first material layer is the silicon nitride layer forming through atom layer deposition process.
8. the formation method of semiconductor device as claimed in claim 2, is characterized in that, described the second material layer is the silicon nitride layer forming through atom layer deposition process.
9. the formation method of semiconductor device as claimed in claim 7 or 8, is characterized in that, the process conditions that form the first material layer and the second material layer are: pressure 5 ~ 10Torr, 500 ~ 600 ℃ of temperature, power 100 ~ 200W.
10. the formation method of semiconductor device as claimed in claim 7 or 8, is characterized in that, the reacting gas of described atom layer deposition process includes SiH
2cl
2, NH
3, N
2.
The formation method of 11. semiconductor devices as claimed in claim 10, is characterized in that, described reaction gas flow is 50 ~ 1000sccm.
The formation method of 12. semiconductor devices as claimed in claim 2, is characterized in that, also comprises: after forming the second side wall, form stress cap layer, described stress cap layer covers described substrate, the second side wall and grid structure.
13. 1 kinds as the formed semiconductor device of formation method of the semiconductor device of any one in claim 1 to 12, it is characterized in that, comprising:
Substrate, has a plurality of grid structures on described substrate;
Near the side wall of described grid structure, between adjacent two side walls between adjacent two grid structures, be groove, described groove has top-down gradually narrow sidewall.
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| CN201210206464.9A CN103515320A (en) | 2012-06-20 | 2012-06-20 | Semiconductor device and forming method thereof |
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| CN201210206464.9A CN103515320A (en) | 2012-06-20 | 2012-06-20 | Semiconductor device and forming method thereof |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469428A (en) * | 2002-07-19 | 2004-01-21 | ����ʿ�뵼������˾ | Method for producing semi-conductor |
| US20040023478A1 (en) * | 2002-07-31 | 2004-02-05 | Samavedam Srikanth B. | Capped dual metal gate transistors for CMOS process and method for making the same |
| CN1770407A (en) * | 2004-11-01 | 2006-05-10 | 富士通株式会社 | Semiconductor device and method for fabricating the same |
| CN101449364A (en) * | 2006-05-19 | 2009-06-03 | 国际商业机器公司 | Compressive nitride film and method of manufacturing thereof |
| CN102479789A (en) * | 2010-11-22 | 2012-05-30 | 台湾积体电路制造股份有限公司 | Spacer elements for semiconductor device |
| CN103474350A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its formation method |
-
2012
- 2012-06-20 CN CN201210206464.9A patent/CN103515320A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469428A (en) * | 2002-07-19 | 2004-01-21 | ����ʿ�뵼������˾ | Method for producing semi-conductor |
| US20040023478A1 (en) * | 2002-07-31 | 2004-02-05 | Samavedam Srikanth B. | Capped dual metal gate transistors for CMOS process and method for making the same |
| CN1770407A (en) * | 2004-11-01 | 2006-05-10 | 富士通株式会社 | Semiconductor device and method for fabricating the same |
| CN101449364A (en) * | 2006-05-19 | 2009-06-03 | 国际商业机器公司 | Compressive nitride film and method of manufacturing thereof |
| CN102479789A (en) * | 2010-11-22 | 2012-05-30 | 台湾积体电路制造股份有限公司 | Spacer elements for semiconductor device |
| CN103474350A (en) * | 2012-06-06 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and its formation method |
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Application publication date: 20140115 |