CN103490762B - The single wire transmission circuit of integrated circuit and light emitting diode integrated circuit cascade signal - Google Patents
The single wire transmission circuit of integrated circuit and light emitting diode integrated circuit cascade signal Download PDFInfo
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- CN103490762B CN103490762B CN201310396363.7A CN201310396363A CN103490762B CN 103490762 B CN103490762 B CN 103490762B CN 201310396363 A CN201310396363 A CN 201310396363A CN 103490762 B CN103490762 B CN 103490762B
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Abstract
A kind of integrated circuit, can split and recombination data, using the single wire transmission circuit of the light emitting diode integrated circuit cascade signal of the integrated circuit, by fractionation and merging to transmitting data, common configuration data and display data can be simultaneously sent in same frame data, data redundancy amount is few, than traditional single line communication, the efficiency of order wire is effectively improved, MCU resources is taken less.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of integrated circuit and using the integrated circuit luminous two
The single wire transmission circuit of pole pipe integrated circuit cascade signal.
Background technology
The single wire transmission circuit data transfer and repeating process of traditional light emitting diode integrated circuit cascade signal are as follows：
Controller sends a frame configuration data C1C2C3C4 ... Cn, when integrated circuit 1 has received data C1, behind forwarding
Data C2C3C4 ... Cn, integrated circuit 2 received data C2, and forwarding data C3C4 ... Cn below, integrated circuit 3 connects
Data C3 is harvested, forwarding data C4C5 ... Cn ... ... below is by that analogy.If now controller sends prolonged low
Level (RESET) signal, all integrated circuits will reset and control after data (Ci, i the are 1~n) decoding being respectively received
RGB ports output processed, completes a data refresh cycle, and integrated circuit is returned to receive SBR.C1 connects for integrated circuit 1
The data of receipts, are generally used to control the RGB configurations of LED, and each color is controlled using 8 data, and in general C1 has 24.C2
It is the data that integrated circuit 2 is received, C3 is the data that data ... the Cn that integrated circuit 3 is received is received for integrated circuit n.If
In order to configure all integrated circuit operations under same state, then C1, C2, C3, C4 ... Cn are identical data.When one
After frame configuration data C1C2C3C4 ... Cn is sent, controller sends next frame display data D1D2D3D4 ... Dn.
The single wire transmission circuit of traditional light emitting diode integrated circuit cascade signal, Data duplication amount is big, takes MCU moneys
Source is more.And data are without verification, receive and forwarding is not all verified, error code easily occur.
The content of the invention
Based on this, it is necessary to provide one kind can reduce MCU take resource be applied to light emitting diode integrated circuit cascade letter
Number single wire transmission circuit integrated circuit.
There is a need to provide it is a kind of can reduce MCU take resource and can verification data be applied to the integrated electricity of light emitting diode
The integrated circuit of the single wire transmission circuit of road cascade signal.
Additionally, also providing a kind of single wire transmission electricity of the light emitting diode integrated circuit cascade signal of application integrated circuit
Road.
A kind of integrated circuit, the transmission data of common configuration data C1 and private data D1D2 ... Dn are included for processing
C1D1D2 ... Dn, it is characterised in that including：
Storage module is received, for receiving and common configuration data C1 is stored；
Data forwarding module, for forwarding the data after receiving storage module treatment；
Data cutout module, for intercepting storage data D1 from private data D1D2 ... Dn；
Data reorganization module, for data D2D3 ... the Dn restructuring after common configuration data C1 and interception storage data.
A kind of integrated circuit, the transmission data of common configuration data C1C2 and private data D1D2 ... Dn are included for processing
C1C2D1D2 ... Dn, including：
Storage module is received, for receiving and common configuration data C1 is stored；
Correction verification module, for receiving common configuration data C1, defeated from the data of integrated circuit from the reception storage module
Enter end and receive common configuration data C2, and common configuration data C1, C2 are verified；
Data forwarding module, for forwarding the data after correction verification module verification；
First modulation module, for modulating the data after the verification；
Second modulation module, for modulating private data D1D2 ... Dn；
Data cutout module, for intercepting storage data D1 from private data D1D2 ... Dn；
Data reorganization module, for data D2D3 ... the Dn weights after common configuration data C1C2 and interception storage data
Group.
Wherein in one embodiment, the reception storage module includes：Not gate N10, not gate N12, AND OR NOT gate
AOI10, and m d type flip flop；M d type flip flop is respectively d type flip flop DFF1, d type flip flop DFF2 ... d type flip flops DFFm.
The AND OR NOT gate AOI10 includes first with door, second and door, the first nor gate.
The not gate N10 output ends connect second input of described first and door, and the not gate N10 inputs connect institute
The first input end of second and door is stated, the output end of first nor gate connects the input of the not gate N12, the not gate
The output end of N12 connects the D inputs of the d type flip flop DFF1.
The Q output of the d type flip flop DFF1 connects the D inputs of the d type flip flop DFF2, the d type flip flop DFF2
The Q output of Q output D inputs ... the d type flip flop DFFm-1 that connects the d type flip flop DFF3 connect the D and touch
The D inputs of hair device DFFm.
The Q output of the d type flip flop DFFm connects the first input end of described first and door.
The input of the not gate N10 receives control signal CMD1H, and described second receives described with the second input of door
Transmission data DICOR, the d type flip flop DFF1, the clock input clock of d type flip flop DFF2 ... d type flip flops DFFm
Signal MQ<1>, the Q output output data CMDQ to described first of the d type flip flop DFFm and the first input end of door.
The control signal CMD1H be used for described first with the first input end data of door and described second and the of door
The gating of two fan-in evidences, the data of gating are in the clock signal MQ<1>Triggering under, deposit by turn successively into the D
Trigger DFF1, d type flip flop DFF2 ... d type flip flops DFFm.
Wherein in one embodiment, correction verification module verify the C2 whether be the C1 inverted value.
Wherein in one embodiment, the correction verification module includes：Not gate N20, not gate N22, AND OR NOT gate AOI20, D are tactile
Hair device Dff20, with OR gate XNOR20, nor gate NOR20.
The AND OR NOT gate AOI20 includes the 3rd with door, the 4th and door, the second nor gate.
The output end of the not gate N20 connects the first input end of the nor gate NOR20, the same OR gate XNOR20's
Output end connects second input of the nor gate NOR20, and the output end of the nor gate NOR20 connects the described 3rd and door
The second input, the input of the not gate N22 connects the first input end of the described 3rd and door, and the not gate N22's is defeated
Go out the second input of end connection the described 4th and door, the output end of second nor gate connects the d type flip flop Dff20's
D inputs, the d type flip flop Dff20'sOutput end connects the first input end and the not gate N20 of the described 3rd and door
Input.
The first input end that the input of the not gate N22 receives control signal CMD2H, the same OR gate XNOR20 is received
Second input of transmission the data DICOR, the same OR gate XNOR20 receives the data CMDQ, the d type flip flop
The clock input clock signal MQ of Dff20<1>, the reset terminal CLR reception reset signals of the d type flip flop Dff20
The Q output output verification signal CMDVALH to the described 3rd of PRCRL, the d type flip flop Dff20 and the first input end of door
And the input of the not gate N20.
The control signal CMD2H be used for the described 3rd with the first input end data of door and the described 4th and the of door
The gating of two fan-in evidences.
The data DICOR and data CMDQ presses bit check by the same OR gate XNOR20, if be verified as conversely,
Then the checking signal CMDVALH is low level, and feeds back to the not gate N20, continues to verify；If being verified as identical, institute
Checking signal CMDVALH is stated for high level, and feeds back to the not gate N20 and the described 3rd and door, it is electricity high to latch CMDVALH
It is flat.
Wherein in one embodiment, the data forwarding module of the common configuration data includes：NAND gate NAND30, together
OR gate XNOR30, d type flip flop Dff30.
The output end of the NAND gate NAND30 connects the first input end of the same OR gate XNOR30, the same to OR gate
The output end of XNOR30 connects the D inputs of the d type flip flop Dff30.
The NAND gate NAND30 first input ends reception control signal DATAH, the NAND gate NAND30 second are input into
End receives the checking signal CMDVALH, and second input of the same OR gate XNOR30 receives the data CMDQ, the D
The clock input clock signal MQ of trigger Dff30<0>, the Q output output data of the d type flip flop Dff30
CMD。
The control signal DATAH and checking signal CMDVALH is controlled described same by the NAND gate NAND30
The output of OR gate XNOR30, it is described same if the control signal DATAH and the checking signal CMDVALH are all high level
OR gate XNOR30 exports the inverted value of the data CMDQ；If it is not, then the same OR gate XNOR30 exports the data CMDQ；Institute
The inverted value of data CMDQ or described data CMDQ is stated in the clock signal MQ<0>Triggering under, from the d type flip flop
The Q output output of Dff30, as the data CMD.
Wherein in one embodiment, the data reorganization module includes：AND OR NOT gate AOI40, not gate N40；
The AND OR NOT gate AOI40 includes the 5th with door, the 6th and door, the 3rd nor gate；The 3rd nor gate output
The input of the end connection not gate N40.
Described 5th receives the private data DATA after being modulated through second modulation module, institute with the first input end of door
State the 5th and receive control signal DATAENH with the second input of door, the described 6th receives control letter with the first input end of door
Number COMENH, the described 6th receives the data CMD after being modulated through first modulation module with the second input of door, described non-
Door N40 outputs data to the ic output.
Wherein in one embodiment, the clock signal MQ<0>It is the private data DATA.
A kind of single wire transmission circuit of light emitting diode integrated circuit cascade data, including n described integrated circuit, point
Not Wei integrated circuit 1, integrated circuit 2 ... integrated circuit n, D1, D2 ... Dn be respectively the integrated circuit 1, integrated circuit 2 ... collection
Into the private data of circuit n, D1, D2 ... Dn digits are all n；Also include controller, the controller is used to send transmission number
According to C1C2D1D2 ..., Dn is to integrated circuit 1.
The output end DO of integrated circuit 1 connects the input DIN of integrated circuit 2, the output end DO connection collection of integrated circuit 2
Into the input DIN of the output end DO connection integrated circuits n of input DIN ... the integrated circuits n-1 of circuit 3.
Then the interception storage of integrated circuit 1 D1 exports C1C2D2D3 ..., and Dn to integrated circuit 2, the interception of integrated circuit 2 is stored
Then D2 exports C1C2D3D4 ... Dn the interception of integrated circuit 3 storage D3 and then exports C1C2D4D5 to integrated circuit 3 ... Dn is to collecting
Into circuit 4 ... integrated circuit n-1 interceptions storage Dn-1 and then output C1C2Dn to integrated circuit n.
Wherein in one embodiment, when the controller sends C1, checking signal CMDVALH, control signal CMD1H are
High level, control signal CMD2H, control signal DATAH, control signal COMENH, control signal DATAENH are low level.
When the controller sends C2, control signal CMD2H, control signal COMENH are high level, control signal
CMD1H, control signal DATAH, control signal DATAENH are low level, and the value of checking signal CMDVALH depends on C1's and C2
Check results, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal
CMDVALH always remains as low level.
When the controller sends D1, control signal DATAH, control signal COMENH are high level, control signal
CMD1H, control signal CMD2H, control signal DATAENH are low level, and the value of checking signal CMDVALH depends on C1's and C2
Check results, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal
CMDVALH always remains as low level.
When the controller sends D2D3 ... Dn, control signal CMD1H, control signal DATAENH are high level, control letter
Number CMD2H, control signal DATAH, control signal COMENH are low level, and the value of checking signal CMDVALH depends on C1 and C2
Check results, if it is high level that C1 and C2 verify errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal
CMDVALH always remains as low level.
The single wire transmission circuit of above-mentioned light emitting diode integrated circuit cascade signal, division and combination is torn open by transmission data
And, common configuration data and private data (display data) can be simultaneously sent in same frame data, data redundancy amount is few, compared with
Traditional single line communication, take MCU resources it is less.
The present invention is also verified to transmission data, is prevented effectively from probable bit error, improves the reliability of data.
Brief description of the drawings
Fig. 1 is the lsi internal circuit module map of an embodiment；
Fig. 2 is the lsi internal circuit module map of another embodiment；
Fig. 3 is the timing diagram of the Integrated circuit portion signal of an embodiment；
Fig. 4 is the lsi internal circuit common configuration data receiver storage module of an embodiment；
Fig. 5 is the lsi internal circuit correction verification module of an embodiment；
Fig. 6 is the data forwarding module of the lsi internal circuit common configuration data of an embodiment；
Fig. 7 is the lsi internal circuit data reorganization module of an embodiment；
Fig. 8 is the single wire transmission circuit of the light emitting diode integrated circuit cascade signal of an embodiment.
Specific embodiment
Below in conjunction with the accompanying drawings, specific embodiment of the invention is described in detail.
Fig. 1 is the lsi internal circuit module map of an embodiment.
The present embodiment is described as follows：
A kind of integrated circuit, the transmission data of common configuration data C1 and private data D1D2 ... Dn are included for processing
C1D1D2 ... Dn, it is characterised in that including：
Storage module 110 is received, for receiving and common configuration data C1 is stored；
Data forwarding module 130, the data after storage module 110 is processed are received for forwarding；
Data cutout module 160, for intercepting storage data D1 from private data D1D2 ... Dn；
Data reorganization module 170, for data D2D3 ... the Dn weights after common configuration data C1 and interception storage data
Group.
Fig. 2 is the lsi internal circuit module map of another embodiment.
The present embodiment is described as follows：
A kind of integrated circuit, the transmission data of common configuration data C1C2 and private data D1D2 ... Dn are included for processing
C1C2D1D2 ... Dn, it is characterised in that including：
Storage module 110 is received, for receiving and common configuration data C1 is stored；
Correction verification module 120, for receiving common configuration data C1 from the reception storage module 110, from integrated circuit
Data input pin receives common configuration data C2, and common configuration data C1, C2 are verified；
Data forwarding module 130, for forwarding the data after the verification of correction verification module 120；
First modulation module 140, for modulating the data after the verification；
Second modulation module 150, for modulating private data D1D2 ... Dn；
Data cutout module 160, for intercepting storage data D1 from private data D1D2 ... Dn；
Data reorganization module 170, for the data D2D3 ... Dn after common configuration data C1C2 and interception storage data
Restructuring
Embodiment is described in more detail below.
Fig. 3 is the timing diagram of the Integrated circuit portion signal of an embodiment.
Fig. 4 is the lsi internal circuit common configuration data receiver storage module 110 of an embodiment.
Receiving storage module 110 includes：Not gate N10, not gate N12, AND OR NOT gate AOI10, and m d type flip flop；M D
Trigger is respectively d type flip flop DFF1, d type flip flop DFF2 ... d type flip flops DFFm.
AND OR NOT gate AOI10 includes first with door 112, second and door 114, the first nor gate 116.
Not gate N10 output ends connection first and the second input of door 112, not gate N10 inputs connection second and door 114
First input end, the input of the output end connection not gate N12 of the first nor gate 116, the output end connection D of not gate N12 touches
The D inputs of hair device DFF1.
It is concatenation relation between d type flip flop DFF1, d type flip flop DFF2 ... d type flip flops DFFm, i.e.,：D type flip flop DFF1's
The D inputs of Q output connection d type flip flop DFF2, the D inputs of the Q output connection d type flip flop DFF3 of d type flip flop DFF2
The D inputs of the Q output connection d type flip flop DFFm of end ... d type flip flop DFFm-1.
The Q output connection first of d type flip flop DFFm and the first input end of door 112.
The input of not gate N10 receives control signal CMD1H, and control signal CMD1H high level is effective.Second with door 114
The second input receive transmission data DICOR, d type flip flop DFF1, d type flip flop DFF2 ... d type flip flops DFFm clock it is defeated
Enter end and receive clock signal MQ<1>, first input of the Q output output data CMDQ to first and door 112 of d type flip flop DFFm
End.
Control signal CMD1H is used to be input into the second of door 114 with the first input end data of door 112 and second to first
The gating of end data.
When controller sends data C1, CMD1H is high level, and the C1 of m-bit data is by AND OR NOT gate AOI10 and not gate
N12, in clock signal MQ<1>Triggering under, deposit by turn successively into d type flip flop DFF1, d type flip flop DFF2 ... d type flip flops
DFFm。
When controller sends data C2, CMD1H saltus steps are low level, AND OR NOT gate AOI10 gated data CMDQ, in clock
Signal MQ<1>Triggering under, data CMDQ is deposited into d type flip flop DFF1, d type flip flop DFF2 ... d type flip flops by turn successively
DFFm, the C1 of m-bit data is stored in m d type flip flop again.
Receiving storage module 110 is used to receive and store data C1, and is correction verification module 120 and data forwarding mould below
The output data C1 of block 130.
Fig. 5 is the lsi internal circuit correction verification module 120 of an embodiment.
Correction verification module 120 verification C2 whether be C1 inverted value.
Correction verification module 120 includes：Not gate N20, not gate N22, AND OR NOT gate AOI20, d type flip flop Dff20, same to OR gate
XNOR20, nor gate NOR20.
AND OR NOT gate AOI20 includes the 3rd with door the 122, the 4th and door 124, the second nor gate 126.
The first input end of the output end connection nor gate NOR20 of not gate N20, with OR gate XNOR20 output end connection or
Second input of not gate NOR20, the output end connection the 3rd of nor gate NOR20 and the second input of door 122, not gate N22
Input connection the 3rd and the first input end of door 122, the output end connection the 4th of not gate N22 and the second input of door 124
End, the D inputs of the output end connection d type flip flop Dff20 of the second nor gate 126, the Q output connection of d type flip flop Dff20 the
Three with the first input end and the input of not gate N20 of door 122.
The input of not gate N22 receives control signal CMD2H, and control signal CMD2H high level is effective.With OR gate XNOR20
First input end receive transmission data DICOR, with OR gate XNOR20 the second input receive data CMDQ, d type flip flop
The clock input clock signal MQ of Dff20<1>, reset terminal CLR reception the reset signals PRCRL, D of d type flip flop Dff20
The Q output output verification signal CMDVALH to the 3rd of trigger Dff20 and the first input end of door 122 and not gate N20's
Input.
Control signal CMD2H is used to be input into the second of door 124 with the first input end data of door 122 and the 4th to the 3rd
The gating of end data.
When controller sends data C1, checking signal CMDVALH is set as high level.
When controller sends data C2, CMD1H is changed into low level, in clock signal MQ<1>Triggering under, be deposited with D touch
Hair device DFF1, the C1 of d type flip flop DFF2 ... d type flip flops DFFm are exported from the Q output of d type flip flop DFFm by turn successively.This
When, C1 is exactly data CMDQ, while the first end and the second input with OR gate XNOR20 of input first and door 112.
Then the C1 of input first and door 112 deposits into d type flip flop again by AND OR NOT gate AOI10 and not gate N12
DFF1, d type flip flop DFF2 ... d type flip flops DFFm.
Be input into OR gate XNOR20 C1 and input verified by turn in same OR gate XNOR20 with the C2 of OR gate XNOR20, with or
Door XNOR20 output verification values.When controller sends data C2, CMD2H is high level, check value by nor gate NOR20 and
AND OR NOT gate AOI20, and in clock signal MQ<1>Triggering under, be input into d type flip flop Dff20, d type flip flop Dff20 Q output
Hold output verification signal CMDVALH.
Data C1 and data C2 presses bit check by same OR gate XNOR20, if be verified as conversely, if checking signal CMDVALH
It is low level, and feeds back to not gate N20, continues to verify；If being verified as identical, checking signal CMDVALH is high level, and instead
Not gate N20 and the 3rd and door 122 are fed to, latch CMDVALH is high level.That is, as long as data C1 and data C2 wherein goes out
CMDVALH, is just locked as low level by existing check errors.In whole group data transmission procedure, if there are not check errors,
Then CMDVALH always remains as high level.
Data C1 and C2 that correction verification module 120 passes through verification data head, judge whether data transfer mistake occurs and export
Checking signal CMDVALH, and circuit is made adjustment, it is possible to prevente effectively from probable bit error, improves the reliability of data.
Fig. 6 is the data forwarding module 130 of the lsi internal circuit common configuration data of an embodiment.
The data forwarding module 130 of common configuration data includes：NAND gate NAND30, with OR gate XNOR30, d type flip flop
Dff30。
The output end of NAND gate NAND30 is connected with the first input end of OR gate XNOR30, with the output end of OR gate XNOR30
The D inputs of connection d type flip flop Dff30.
NAND gate NAND30 first input ends receive control signal DATAH, and the inputs of NAND gate NAND30 second receive school
Signal CMDVALH is tested, data CMDQ is received with second input of OR gate XNOR30, the input end of clock of d type flip flop Dff30 connects
Receive clock signal MQ<0>, the Q output output data CMD of d type flip flop Dff30.
Control signal DATAH and checking signal CMDVALH is controlled with the output of OR gate XNOR30 by NAND gate NAND30,
If control signal DATAH and checking signal CMDVALH are all high level, with negating for OR gate XNOR30 output datas CMDQ
Value；If it is not, then with OR gate XNOR30 output datas CMDQ；The inverted value of data CMDQ or data CMDQ is in clock signal MQ<0>
Triggering under, exported from the Q output of d type flip flop Dff30, as data CMD.
When controller sends data C1, also it is input into without data CMDQ with second input of OR gate XNOR30, so this
When do not exported with the output end of OR gate XNOR30, data forwarding module 130 is not also exported.
When controller sends data C2, receive data CMDQ (i.e. C1) with second input of OR gate XNOR30 and be input into,
Now DATAH is low level, so NAND gate NAND30 output high level, touches with the output end output C1 to D of OR gate XNOR30
The D inputs of hair device Dff30, in clock signal MQ<0>Triggering under, exported from the Q output of d type flip flop Dff30, as number
According to CMD.
When controller sends data D1, receive data CMDQ (i.e. C1) with second input of OR gate XNOR30 and be input into,
Now DATAH is high level.If checking signal CMDVALH high level, then with OR gate XNOR30 output datas CMDQ (i.e. C1)
Inverted value (i.e. C2)；If it is not, then with OR gate XNOR30 output datas CMDQ (i.e. C1).Exported with the output end of OR gate XNOR30
The D inputs of C1 to d type flip flop Dff30, in clock signal MQ<0>Triggering under, the Q output from d type flip flop Dff30 is defeated
Go out, as data CMD.
Data forwarding module 130 determines forwarding C1 still according to the value of control signal DATAH and checking signal CMDVALH
C2, when controller sends data C2, if checking signal CMDVALH is low level, judges that data transfer occurs abnormal, then forward
C1.So, when data transfer to next integrated circuit, the data head that next integrated circuit is received is C1C1, then next collection
Correction verification module into circuit just can just judge that exception occurs in data transfer in a data of verification C1 and C2, save
Run time and MCU resources.
First modulation module 140 receive data CMD, through inner modulation after, the data CMD after modulation is exported to data weight
Group module 170.
Private data D1D2 ... Dn is DATA, and the process circuit of DATA includes：Second modulation module 150, data cutout mould
Block 160, data forwarding module 170.
Controller sends private data D1D2 ... Dn to modulation module 150, the data input after modulation to data cutout mould
Block 160, after the interception storage data of data cutout module 160 D1, the data D2D3 ... Dn after interception storage is input to data recombination
Module 170.
Fig. 7 is the lsi internal circuit data reorganization module 170 of an embodiment.
Data reorganization module 170 includes：AND OR NOT gate AOI40, not gate N40.
AND OR NOT gate AOI40 includes the 5th with door the 172, the 6th and door 174, the 3rd nor gate 176, the output of the 3rd nor gate
End connects the input of not gate N40.
5th receives through the modulated private data DATA of the second modulation module with the first input end of door 172, the 5th with
Second input of door 172 receives control signal DATAENH, and the 6th receives control signal with the first input end of door 174
COMENH, the 6th receives through the modulated data CMD of the first modulation module, not gate N40 output numbers with the second input of door 174
According to ic output DO.
When controller sends data C1, control signal DATAENH and control signal COMENH is low level, and DO outputs are low
Level.
When controller sends data C2, control signal DATAENH is low level, and control signal COMENH is high level, with
Nor gate AOI40 gated data CMD, i.e. C1.
When controller sends data D1, control signal DATAENH is low level, and control signal COMENH is high level, with
Nor gate AOI40 gated data CMD, data CMD or for C1 or be C2, are determined by the value of checking signal CMDVALH.
When controller sends data D2, control signal DATAENH switchs to high level, and control signal COMENH switchs to low electricity
It is flat, AND OR NOT gate AOI40 gating private data DATA, now private data DATA is data D2.
When controller sends data Dn, control signal DATAENH is high level, and control signal COMENH is low level, with
Nor gate AOI40 gates private data DATA, and now private data DATA is data Dn.
The saltus step that data reorganization module 170 passes through control signal DATAENH and control signal COMENH, controls AND OR NOT gate
The data of AOI40 gatings, have reached the effect for recombinating common configuration data C1C2 and private data.
In the present embodiment, clock signal MQ<0>It is private data DATA.
In the present embodiment, C1 receives storage module 110 and stores by the DIN inputs of integrated circuit.After C1 storages are finished,
Verified with C2 together input validation module 120.After verification is finished, 130 turns of data forwarding module is passed through according to check results
Data after hair verification.Data after verification are by exporting data C1C2, C1C2 after modulating after the modulation of the first modulation module 140
Input data recombination module 170.
D1D2 ... Dn are input into the second modulation module 150 and are modulated, and then the interception of data cutout module 160 storage D1, cuts
Take the data D2D3 ... Dn after storage and be input to data reorganization module 170.
C1C2 and D2D3 ... Dn are reassembled into C1C2D2D3 by data reorganization module 170 ... Dn, then by integrated circuit
DO is exported.
Fig. 8 is the single wire transmission circuit of the light emitting diode integrated circuit cascade signal of an embodiment.
A kind of single wire transmission circuit of light emitting diode integrated circuit cascade data, including n integrated circuit of the invention,
Respectively integrated circuit 1, integrated circuit 2 ... integrated circuit n, D1, D2 ... Dn are respectively the integrated circuit 1, integrated circuit 2 ...
The private data of integrated circuit n, D1, D2 ... Dn digits are all n；Also include controller, controller is used to send transmission data
C1C2D1D2 ... Dn are to integrated circuit 1.
The output end DO of integrated circuit 1 connects the input DIN of integrated circuit 2, the output end DO connection collection of integrated circuit 2
Into the input DIN of the output end DO connection integrated circuits n of input DIN ... the integrated circuits n-1 of circuit 3.
Then the interception storage of integrated circuit 1 D1 exports C1C2D2D3 ..., and Dn to integrated circuit 2, the interception of integrated circuit 2 is stored
Then D2 exports C1C2D3D4 ... Dn the interception of integrated circuit 3 storage D3 and then exports C1C2D4D5 to integrated circuit 3 ... Dn is to collecting
Into circuit 4 ... integrated circuit n-1 interceptions storage Dn-1 and then output C1C2Dn to integrated circuit n.
Controller sends reset signal, all integrated circuits each intercept be sent to after the data that are stored into are decoded it is luminous
Diode driving module simultaneously resets, and completes a data refresh cycle.
The sequential relationship of Integrated circuit portion signal in the present embodiment is described below.
Fig. 3 is the timing diagram of the Integrated circuit portion signal of an embodiment.
When controller sends C1, checking signal CMDVALH, control signal CMD1H are high level, control signal CMD2H, control
Signal DATAH processed, control signal COMENH, control signal DATAENH are low level.
When controller sends C2, control signal CMD2H, control signal COMENH are high level, control signal CMD1H, control
Signal DATAH processed, control signal DATAENH are low level, and the value of checking signal CMDVALH depends on the verification knot of C1 and C2
Really, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal CMDVALH mono-
Directly remain low level.
When controller sends D1, control signal DATAH, control signal COMENH are high level, control signal CMD1H, control
Signal CMD2H processed, control signal DATAENH are low level, and the value of checking signal CMDVALH depends on the verification knot of C1 and C2
Really, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal CMDVALH mono-
Directly remain low level.
When controller sends D2D3 ... Dn, control signal CMD1H, control signal DATAENH are high level, control signal
CMD2H, control signal DATAH, control signal COMENH are low level, and the value of checking signal CMDVALH depends on C1's and C2
Check results, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal
CMDVALH always remains as low level.
The single wire transmission circuit of above-mentioned light emitting diode integrated circuit cascade signal, division and combination is torn open by transmission data
And, common configuration data and display data can be simultaneously sent in same frame data, data redundancy amount is few, than traditional list
Line communicates, and takes MCU resources less.The single wire transmission circuit of above-mentioned light emitting diode integrated circuit cascade signal is also to transmission number
According to being verified, probable bit error is prevented effectively from, improves the reliability of data.
Embodiment described above only expresses several embodiments of the invention, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the scope of the claims of the present invention can not be interpreted as.It should be pointed out that for one of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Shield scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (9)
1. a kind of integrated circuit, the transmission data of common configuration data C1C2 and private data D1D2 ... Dn are included for processing
C1C2D1D2 ... Dn, it is characterised in that including：
Storage module is received, for receiving and common configuration data C1 is stored；
Correction verification module, for receiving common configuration data C1, the data input pin from integrated circuit from the reception storage module
Common configuration data C2 is received, and common configuration data C1, C2 are verified；
Data forwarding module, for forwarding the data after correction verification module verification；
First modulation module, for modulating through data forwarding module output through the data after correction verification module verification；
Second modulation module, for modulating private data D1D2 ... Dn；
Data cutout module, for intercepting storage number in the private data D1D2 ... Dn after being modulated through second modulation module
According to D1；
Data reorganization module, for the common configuration data C1C2 after being modulated through first modulation module and interception storage number
Data D2D3 ... Dn restructuring after.
2. integrated circuit according to claim 1, it is characterised in that the reception storage module includes：Not gate N10 is non-
Door N12, AND OR NOT gate AOI10, and m d type flip flop；M d type flip flop is respectively d type flip flop DFF1, d type flip flop
DFF2 ... d type flip flops DFFm；
The AND OR NOT gate AOI10 includes first with door, second and door, the first nor gate；
The not gate N10 output ends connect second input of described first and door, the not gate N10 inputs connection described the
Two connect the input of the not gate N12, the not gate N12 with the first input end of door, the output end of first nor gate
Output end connect the D inputs of the d type flip flop DFF1；
The Q output of the d type flip flop DFF1 connects the D inputs of the d type flip flop DFF2, and the Q of the d type flip flop DFF2 is defeated
The Q output for going out D inputs ... the d type flip flop DFFm-1 of the end connection d type flip flop DFF3 connects the d type flip flop
The D inputs of DFFm；
The Q output of the d type flip flop DFFm connects the first input end of described first and door；
The input of the not gate N10 receives control signal CMD1H, and described second receives the transmission with the second input of door
Common configuration data C1, the d type flip flop DFF1 in data C1C2D1D2 ... Dn, d type flip flop DFF2 ... d type flip flops DFFm
Clock input clock signal MQ<1>, the Q output output data CMDQ to described first of the d type flip flop DFFm
With the first input end of door；
The control signal CMD1H is used for defeated with the second of door with the first input end data of door and described second to described first
Enter the gating of end data, the data of gating are in the clock signal MQ<1>Triggering under, deposit by turn successively into the D triggering
Device DFF1, d type flip flop DFF2 ... d type flip flops DFFm.
3. integrated circuit according to claim 2, it is characterised in that the correction verification module verifies whether the C2 is described
The inverted value of C1.
4. integrated circuit according to claim 3, it is characterised in that the correction verification module includes：Not gate N20, not gate
N22, AND OR NOT gate AOI20, d type flip flop Dff20, with OR gate XNOR20, nor gate NOR20；
The AND OR NOT gate AOI20 includes the 3rd with door, the 4th and door, the second nor gate；
The output end of the not gate N20 connects the first input end of the nor gate NOR20, the output of the same OR gate XNOR20
Second input of the end connection nor gate NOR20, the output end of the nor gate NOR20 connects the of the described 3rd and door
Two inputs, the input of the not gate N22 connects the first input end of the described 3rd and door, the output end of the not gate N22
Second input of the described 4th and door is connected, the D of the output end connection d type flip flop Dff20 of second nor gate is defeated
Enter end, it is defeated with the first input end of door and the not gate N20 that the Q output of the d type flip flop Dff20 connects the described 3rd
Enter end；
The first input end that the input of the not gate N22 receives control signal CMD2H, the same OR gate XNOR20 receives described
Second input of common configuration data C2, the same OR gate XNOR20 in transmission data C1C2D1D2 ... Dn receives the number
According to CMDQ, the clock input clock signal MQ of the d type flip flop Dff20<1>, the reset terminal of the d type flip flop Dff20
CLR receive the Q output output verification signal CMDVALH to the described 3rd of reset signal PRCRL, the d type flip flop Dff20 with
The first input end of door and the input of the not gate N20；
The control signal CMD2H be used for the described 3rd with the first input end data of door and described 4th defeated with the second of door
Enter the gating of end data；
The common configuration data C2 and data CMDQ presses bit check by the same OR gate XNOR20, if being verified as phase
Instead, then the checking signal CMDVALH is low level, and feeds back to the not gate N20, continues to verify；If be verified as it is identical,
The checking signal CMDVALH is high level, and feeds back to the not gate N20 and the described 3rd and door, and it is height to latch CMDVALH
Level.
5. integrated circuit according to claim 4, it is characterised in that the data forwarding module bag of the common configuration data
Include：NAND gate NAND30, with OR gate XNOR30, d type flip flop Dff30；
The output end of the NAND gate NAND30 connects the first input end of the same OR gate XNOR30, the same OR gate XNOR30
Output end connect the D inputs of the d type flip flop Dff30；
The NAND gate NAND30 first input ends receive control signal DATAH, the inputs of NAND gate NAND30 second termination
The checking signal CMDVALH is received, second input of the same OR gate XNOR30 receives the data CMDQ, the D triggerings
The clock input clock signal MQ of device Dff30<0>, the Q output output data CMD of the d type flip flop Dff30；
The control signal DATAH and checking signal CMDVALH controls the same OR gate by the NAND gate NAND30
The output of XNOR30, if the control signal DATAH and the checking signal CMDVALH are all high level, the same to OR gate
XNOR30 exports the inverted value of the data CMDQ；If it is not, then the same OR gate XNOR30 exports the data CMDQ；The number
According to the inverted value of CMDQ or described data CMDQ in the clock signal MQ<0>Triggering under, from the Q of the d type flip flop Dff30
Output end is exported, used as the data CMD.
6. integrated circuit according to claim 5, it is characterised in that the data reorganization module includes：AND OR NOT gate
AOI40, not gate N40；
The AND OR NOT gate AOI40 includes the 5th with door, the 6th and door, the 3rd nor gate；The 3rd nor gate output end connects
Connect the input of the not gate N40；
Described 5th receives the private data DATA after being modulated through second modulation module with the first input end of door, and described the
Five receive control signal DATAENH with the second input of door, and the described 6th receives control signal with the first input end of door
COMENH, the described 6th receives through the modulated data CMD of first modulation module, the not gate with the second input of door
N40 outputs data to the ic output.
7. integrated circuit according to claim 6, it is characterised in that the clock signal MQ<0>It is the private data
DATA。
8. a kind of single wire transmission circuit of light emitting diode integrated circuit cascade data, it is characterised in that including n according to right
It is required that the integrated circuit described in 1 to 7 any one, respectively integrated circuit 1, integrated circuit 2 ... integrated circuit n, D1, D2 ... Dn divide
Not Wei the integrated circuit 1, the private data of integrated circuit 2 ... integrated circuit n, D1, D2 ... Dn digits all be n, also include
Controller, the controller is used to send transmission data C1C2D1D2 ... Dn to integrated circuit 1；
The output end DO of integrated circuit 1 connects the input DIN of integrated circuit 2, and the output end DO of integrated circuit 2 connects integrated electricity
The input DIN of the output end DO connection integrated circuits n of input DIN ... the integrated circuits n-1 on road 3；
Then the interception storage of integrated circuit 1 D1 exports C1C2D2D3 ..., and Dn to integrated circuit 2, it is right that the interception of integrated circuit 2 stores D2
After export C1C2D3D4 ... Dn to integrated circuit 3, the interception storage of integrated circuit 3 and then exports C1C2D4D5 at D3 ... Dn to integrated electricity
Then road 4 ... integrated circuit n-1 interception storages Dn-1 exports C1C2Dn to integrated circuit n.
9. the single wire transmission circuit of light emitting diode integrated circuit cascade data according to claim 8, it is characterised in that：
When the controller sends C1, checking signal CMDVALH, control signal CMD1H are high level, control signal CMD2H, control
Signal DATAH processed, control signal COMENH, control signal DATAENH are low level；
When the controller sends C2, control signal CMD2H, control signal COMENH are high level, control signal CMD1H, control
Signal DATAH processed, control signal DATAENH are low level, and the value of checking signal CMDVALH depends on the verification knot of C1 and C2
Really, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal CMDVALH mono-
Directly remain low level；
When the controller sends D1, control signal DATAH, control signal COMENH are high level, control signal CMD1H, control
Signal CMD2H processed, control signal DATAENH are low level, and the value of checking signal CMDVALH depends on the verification knot of C1 and C2
Really, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal CMDVALH mono-
Directly remain low level；
When the controller sends D2D3 ... Dn, control signal CMD1H, control signal DATAENH are high level, control signal
CMD2H, control signal DATAH, control signal COMENH are low level, and the value of checking signal CMDVALH depends on C1's and C2
Check results, if it is high level that C1 and C2 verifies errorless checking signal CMDVALH, if C1 and C2 verifies wrong checking signal
CMDVALH always remains as low level.
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| CN201310396363.7A CN103490762B (en) | 2013-09-03 | 2013-09-03 | The single wire transmission circuit of integrated circuit and light emitting diode integrated circuit cascade signal |
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| CN104517569B (en) * | 2014-12-15 | 2017-08-25 | 深圳市明微电子股份有限公司 | Display system of connecting and its data transmission method |
| CN110996461B (en) * | 2019-12-30 | 2021-03-02 | 南京浣轩半导体有限公司 | Single-wire LED data transmission display method and driving chip |
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| CN101052258A (en) * | 2006-04-07 | 2007-10-10 | 刘晓光 | Lamp light controlled network and control method |
| CN101340757A (en) * | 2008-07-21 | 2009-01-07 | 北京巨数数字技术开发有限公司 | Single line transmission protocol of lamp spot display chip concatenated signal |
| CN101339738A (en) * | 2008-07-21 | 2009-01-07 | 北京巨数数字技术开发有限公司 | Single line cascade chip for lamp point display |
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