CN103490762A - Integrated circuit and single-line transmission circuit of cascading signal of light emitting diode integrated circuit - Google Patents
Integrated circuit and single-line transmission circuit of cascading signal of light emitting diode integrated circuit Download PDFInfo
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Abstract
The invention discloses an integrated circuit which can be used for splitting and reorganizing data, and a single-line transmission circuit of a cascading signal of a light emitting diode integrated circuit, wherein the single-line transmission circuit comprises the integrated circuit. Transmission data are split and combined so that public configuration data and display data in the same frame of data can be sent simultaneously. Therefore, data redundancy is low, the efficiency of a communication line is improved effectively compared with traditional single-line communication, and few MCU resources are occupied.
Description
Technical field
The present invention relates to integrated circuit fields, particularly relate to a kind of integrated circuit and apply the single wire transmission circuit of the light-emitting diode integrated circuit cascade signal of this integrated circuit.
Background technology
The transmission of single wire transmission circuit data the repeating process of traditional light-emitting diode integrated circuit cascade signal are as follows:
Controller sends a frame configuration data C1C2C3C4 ... Cn, when integrated circuit 1 receives data C1, forward the data C2C3C4 of back ... Cn, integrated circuit 2 receives data C2, forward the data C3C4 of back ... Cn, integrated circuit 3 receives data C3, forwards the data C4C5 of back ... Cn ... by that analogy.If now controller sends long low level (RESET) signal, all integrated circuits will reset also the data (Ci received separately, i is 1～n) output of the rear control of decoding RGB port, complete a data refresh cycle, integrated circuit is got back to again the reception standby condition.C1 is the data that integrated circuit 1 receives, and generally is used for controlling the RGB configuration of LED, and every kind of color is used 8 bit data to control, and in general C1 has 24.C2 is the data that integrated circuit 2 receives, and C3 is the data that integrated circuit 3 receives ... Cn is the data that integrated circuit n receives.If be operated under the same state in order to configure all integrated circuits, C1, C2, C3, C4 ... Cn is identical data.As a frame configuration data C1C2C3C4 ... after Cn is sent, controller sends next frame and shows data D1D2D3D4 ... Dn.
The single wire transmission circuit of traditional light-emitting diode integrated circuit cascade signal, the Data duplication amount is large, takies the MCU resource more.And data are without verification, receive and all do not carry out verification with forwarding, error code easily appears.
Summary of the invention
Based on this, be necessary to provide a kind of MCU that can reduce to take the integrated circuit that resource is applied to the single wire transmission circuit of light-emitting diode integrated circuit cascade signal.
Also be necessary to provide a kind of and can reduce the integrated circuit that MCU takies the single wire transmission circuit that is applied to light-emitting diode integrated circuit cascade signal of resource energy checking data.
A kind of single wire transmission circuit of light-emitting diode integrated circuit cascade signal of this integrated circuit of application also is provided in addition.
A kind of integrated circuit, for the treatment of comprising common configuration data C1 and private data D1D2 ... the transmission data C1D1D2 of Dn ... Dn, is characterized in that, comprising:
Receive storage module, for receiving and store common configuration data C1;
Data forwarding module, for forwarding the data that receive after storage module is processed;
The data cutout module, for from private data D1D2 ... intercepting storage data D1 in Dn;
The data recombination module, for the data D2D3 after common configuration data C1 and intercepting storage data ... the Dn restructuring.
A kind of integrated circuit, for the treatment of comprising common configuration data C1C2 and private data D1D2 ... the transmission data C1C2D1D2 of Dn ... Dn comprises:
Receive storage module, for receiving and store common configuration data C1;
Correction verification module, for receiving common configuration data C1 from described reception storage module, from the data input pin of integrated circuit, receiving common configuration data C2, and carry out verification to described common configuration data C1, C2;
Data forwarding module, for forwarding the data after the correction verification module verification;
The first modulation module, for modulating the data after described verification;
The second modulation module, for modulating private data D1D2 ... Dn;
The data cutout module, for from private data D1D2 ... intercepting storage data D1 in Dn;
The data recombination module, for the data D2D3 after common configuration data C1C2 and intercepting storage data ... the Dn restructuring.
In embodiment, described reception storage module comprises: not gate N10, not gate N12, AND OR NOT gate AOI10, and m d type flip flop therein; M d type flip flop is respectively d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm.
Described AND OR NOT gate AOI10 comprise first with the door, second with, the first NOR gate.
Described not gate N10 output connect described first with the door the second input, described not gate N10 input connect described second with the door first input end, the output of described the first NOR gate connects the input of described not gate N12, and the output of described not gate N12 connects the D input of described d type flip flop DFF1.
The Q output of described d type flip flop DFF1 connects the D input of described d type flip flop DFF2, the Q output of described d type flip flop DFF2 connects the D input of described d type flip flop DFF3 ... the Q output of described d type flip flop DFFm-1 connects the D input of described d type flip flop DFFm.
The Q output of described d type flip flop DFFm connect described first with the door first input end.
The input reception control signal CMD1H of described not gate N10, described second receives described transmission data DICOR with the second input of door, described d type flip flop DFF1, d type flip flop DFF2 ... the input end of clock receive clock signal MQ of d type flip flop DFFm<1 >, the Q output of described d type flip flop DFFm output data CMDQ to described first with the first input end of door.
Described control signal CMD1H for to described first with the first input end data of door and described second with the gating of the second fan-in certificate of door, the data of gating are in described clock signal MQ<1 > triggering under, deposit by turn successively into described d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm.
In embodiment, whether the described C2 of correction verification module verification is the inverted value of described C1 therein.
In embodiment, described correction verification module comprises therein: not gate N20, not gate N22, AND OR NOT gate AOI20, d type flip flop Dff20, with or door XNOR20, NOR gate NOR20.
Described AND OR NOT gate AOI20 comprise the 3rd with the door, the 4th with the door, the second NOR gate.
The output of described not gate N20 connects the first input end of described NOR gate NOR20, described with or the output of door XNOR20 connect the second input of described NOR gate NOR20, the output of described NOR gate NOR20 connect the described the 3rd with the door the second input, the input of described not gate N22 connect the described the 3rd with the door first input end, the output of described not gate N22 connect the described the 4th with the door the second input, the output of described the second NOR gate connects the D input of described d type flip flop Dff20, described d type flip flop Dff20's
output connect the described the 3rd with the door first input end and the input of described not gate N20.
The input reception control signal CMD2H of described not gate N22, described with or the door XNOR20 first input end receive described transmission data DICOR, described with or the door XNOR20 first input end receive described data CMDQ, the input end of clock receive clock signal MQ of described d type flip flop Dff20<1>, the reset terminal CLR of described d type flip flop Dff20 receives reset signal PRCRL, described d type flip flop Dff20's
output output verification signal CMDVALH to the described the 3rd with the door first input end and the input of described not gate N20.
Described control signal CMD2H for to the described the 3rd with the first input end data of door and the described the 4th with the gating of the second fan-in certificate of door.
Described data DICOR and described data CMDQ by described with or a door XNOR20 press bit check, if be verified as on the contrary, described checking signal CMDVALH is high level, and feeds back to described not gate N20, the continuation verification; If be verified as identically, described checking signal CMDVALH is low level, and feed back to described not gate N20 and the described the 3rd with door, latching CMDVALH is low level.
In embodiment, the data forwarding module of described common configuration data comprises therein: NAND gate NAND30, with or door XNOR30, d type flip flop Dff30.
The output of described NAND gate NAND30 connect described with or the first input end of door XNOR30, described with or the output of door XNOR30 connect the D input of described d type flip flop Dff30.
Described NAND gate NAND30 first input end reception control signal DATAH, described NAND gate NAND30 first input end receives described checking signal CMDVALH, described with or the door XNOR30 the second input receive described data CMDQ, the input end of clock receive clock signal MQ of described d type flip flop Dff30<0 >, the Q output output data CMD of described d type flip flop Dff30.
Described control signal DATAH and described checking signal CMDVALH by described NAND gate NAND30 control described with or the output of door XNOR30, if described control signal DATAH and described checking signal CMDVALH are all high level, described with or door XNOR30 export the inverted value of described data CMDQ; If not, described with or the door XNOR30 export described data CMDQ; The inverted value of described data CMDQ or described data CMDQ is in described clock signal MQ<0 > triggering under, from the output of the Q output of described d type flip flop Dff30, as described data CMD.
In embodiment, described data recombination module comprises: AND OR NOT gate AOI40, not gate N40 therein;
Described AND OR NOT gate AOI40 comprise the 5th with the door, the 6th with the door, the 3rd NOR gate; Described the 3rd NOR gate output connects the input of described not gate N40.
The described the 5th receives the private data DATA after described the second modulation module modulation with the first input end of door, the described the 5th with the door the second input reception control signal DATAENH, the described the 6th with the door first input end reception control signal COMENH, the described the 6th receives the data CMD after described the first modulation module modulation with the second input of door, and described not gate N40 output data are to described ic output.
Therein in embodiment, described clock signal MQ<0 > be described private data DATA.
A kind of single wire transmission circuit of light-emitting diode integrated circuit cascade data, comprise n described integrated circuit, be respectively integrated circuit 1, integrated circuit 2 ... integrated circuit n, D1, D2 ... Dn is respectively described integrated circuit 1, integrated circuit 2 ... the private data of integrated circuit n, D1, D2 ... the Dn figure place is all the n position; Also comprise controller, described controller is for sending transmission data C1C2D1D2 ... Dn is to integrated circuit 1.
The output DO of integrated circuit 1 connects the input DIN of integrated circuit 2, and the output DO of integrated circuit 2 connects the input DIN of integrated circuit 3 ... the output DO of integrated circuit n-1 connects the input DIN of integrated circuit n.
In embodiment, when described controller sends C1, checking signal CMDVALH, control signal CMD1H are high level therein, and control signal CMD2H, control signal DATAH, control signal COMENH, control signal DATAENH are low level.
When described controller sends C2, control signal CMD2H, control signal COMENH are high level, control signal CMD1H, control signal DATAH, control signal DATAENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
When described controller sends D1, control signal DATAH, control signal COMENH are high level, control signal CMD1H, control signal CMD2H, control signal DATAENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
Described controller sends D2D3 ... during Dn, control signal CMD1H, control signal DATAENH are high level, control signal CMD2H, control signal DATAH, control signal COMENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
The single wire transmission circuit of above-mentioned light-emitting diode integrated circuit cascade signal, by fractionation and the merging to the transmission data, can send common configuration data and private data (demonstration data) in same frame data simultaneously, the data redundancy amount is few, than traditional single line communication, take the MCU resource less.
The present invention also carries out verification to the transmission data, effectively avoids probable bit error, has improved the reliability of data.
The accompanying drawing explanation
The lsi internal circuit module map that Fig. 1 is an embodiment;
The lsi internal circuit module map that Fig. 2 is another embodiment;
The sequential chart of the integrated circuit part signal that Fig. 3 is an embodiment;
The lsi internal circuit common configuration data receiver storage module that Fig. 4 is an embodiment;
The lsi internal circuit correction verification module that Fig. 5 is an embodiment;
The data forwarding module of the lsi internal circuit common configuration data that Fig. 6 is an embodiment;
The lsi internal circuit data recombination module that Fig. 7 is an embodiment;
The single wire transmission circuit of the light-emitting diode integrated circuit cascade signal that Fig. 8 is an embodiment.
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
The lsi internal circuit module map that Fig. 1 is an embodiment.
The present embodiment is described below:
A kind of integrated circuit, for the treatment of comprising common configuration data C1 and private data D1D2 ... the transmission data C1D1D2 of Dn ... Dn, is characterized in that, comprising:
Receive storage module 110, for receiving and store common configuration data C1;
The lsi internal circuit module map that Fig. 2 is another embodiment.
The present embodiment is described below:
A kind of integrated circuit, for the treatment of comprising common configuration data C1C2 and private data D1D2 ... the transmission data C1C2D1D2 of Dn ... Dn, is characterized in that, comprising:
Receive storage module 110, for receiving and store common configuration data C1;
The first modulation module 140, for modulating the data after described verification;
The second modulation module 150, for modulating private data D1D2 ... Dn;
Below embodiment is described in more detail.
The sequential chart of the integrated circuit part signal that Fig. 3 is an embodiment.
The lsi internal circuit common configuration data receiver storage module 110 that Fig. 4 is an embodiment.
Receiving storage module 110 comprises: not gate N10, not gate N12, AND OR NOT gate AOI10, and m d type flip flop; M d type flip flop is respectively d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm.
AND OR NOT gate AOI10 comprise first with door 112, second with the 114, first NOR gate 116.
The second input of not gate N10 output connection first and door 112, the first input end of not gate N10 input connection second and door 114, the output of the first NOR gate 116 connects the input of not gate N12, and the output of not gate N12 connects the D input of d type flip flop DFF1.
D type flip flop DFF1, d type flip flop DFF2 ... it between d type flip flop DFFm, is the serial connection relation, that is: the Q output of d type flip flop DFF1 connects the D input of d type flip flop DFF2, the Q output of d type flip flop DFF2 connects the D input of d type flip flop DFF3 ... the Q output of d type flip flop DFFm-1 connects the D input of d type flip flop DFFm.
The Q output connection first of d type flip flop DFFm and the first input end of door 112.
The input reception control signal CMD1H of not gate N10, control signal CMD1H high level is effective.Second receives transmission data DICOR with the second input of door 114, d type flip flop DFF1, d type flip flop DFF2 ... the input end of clock receive clock signal MQ of d type flip flop DFFm<1 >, the Q output output data CMDQ to the first of d type flip flop DFFm and the first input end of door 112.
Control signal CMD1H for to first with door 112 first input end data and second with the gating of the second fan-in certificate of 114.
When controller sends data C1, CMD1H is high level, and the C1 of m bit data is through AND OR NOT gate AOI10 and not gate N12, in clock signal MQ<1 > triggering under, deposit by turn successively into d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm.
When controller sends data C2, the CMD1H saltus step is low level, AND OR NOT gate AOI10 gated data CMDQ, in clock signal MQ<1 > triggering under, data CMDQ deposits successively by turn into d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm, the C1 of m bit data deposits m d type flip flop again in.
Receive storage module 110 for receiving and storage data C1, and be correction verification module 120 and the data forwarding module 130 output data C1 of back.
The lsi internal circuit correction verification module 120 that Fig. 5 is an embodiment.
Whether correction verification module 120 verification C2 are the inverted value of C1.
AND OR NOT gate AOI20 comprise the 3rd with the door the 122, the 4th with the door 124, second NOR gate 126.
The output of not gate N20 connects the first input end of NOR gate NOR20, output same or door XNOR20 connects the second input of NOR gate NOR20, the output connection the 3rd of NOR gate NOR20 and the second input of door 122, the input connection the 3rd of not gate N22 and the first input end of door 122, the output connection the 4th of not gate N22 and the second input of door 124, the output of the second NOR gate 126 connects the D input of d type flip flop Dff20, d type flip flop Dff20's
output connection the 3rd and the first input end of door 122 and the input of not gate N20.
The input reception control signal CMD2H of not gate N22, control signal CMD2H high level is effective.First input end same or door XNOR20 receives transmission data DICOR, first input end same or door XNOR20 receives data CMDQ, the input end of clock receive clock signal MQ of d type flip flop Dff20<1>, the reset terminal CLR of d type flip flop Dff20 receives reset signal PRCRL, d type flip flop Dff20's
output output verification signal CMDVALH to the three and the first input end of door 122 and the input of not gate N20.
Control signal CMD2H for to the 3rd with door 122 first input end data and the 4th with the gating of the second fan-in certificate of door 124.
When controller sends data C1, checking signal CMDVALH is set as high level.
When controller sends data C2, CMD1H becomes low level, in clock signal MQ<1 > triggering under, be deposited with d type flip flop DFF1, d type flip flop DFF2 ... the C1 of d type flip flop DFFm exports from the Q output of d type flip flop DFFm successively by turn.Now, C1 is exactly data CMDQ, input simultaneously first with door 112 first end and with or the second input of door XNOR20.
C1 process AND OR NOT gate AOI10 and the not gate N12 of input first and door 112, and then deposit into d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm.
Input with or the C1 of door XNOR20 and input with the C2 of door XNOR20 with or door XNOR20 verification by turn, with or door XNOR20 output verification value.When controller sends data C2, CMD2H is high level, and check value is through NOR gate NOR20 and AND OR NOT gate AOI20, and in clock signal MQ<1>triggering under, input d type flip flop Dff20, d type flip flop Dff20's
output output verification signal CMDVALH.
Data C1 and data C2 press bit check by same or a door XNOR20, if be verified as on the contrary, checking signal CMDVALH is high level, and feeds back to not gate N20, continues verification; If be verified as identically, checking signal CMDVALH is low level, and feed back to not gate N20 and the 3rd with door 122, latching CMDVALH is low level.That is, if data C1 and data C2 wherein one occur just CMDVALH being locked as to low level by check errors.In whole group of data transmission procedure, if check errors do not occur, CMDVALH remains high level always.
The data forwarding module 130 of the lsi internal circuit common configuration data that Fig. 6 is an embodiment.
The data forwarding module 130 of common configuration data comprises: NAND gate NAND30, same or door XNOR30, d type flip flop Dff30.
The output of NAND gate NAND30 connects first input end same or door XNOR30, and output same or door XNOR30 connects the D input of d type flip flop Dff30.
NAND gate NAND30 first input end reception control signal DATAH, NAND gate NAND30 first input end receives checking signal CMDVALH, the second input same or door XNOR30 receives data CMDQ, the input end of clock receive clock signal MQ of d type flip flop Dff30<0 >, the Q output output data CMD of d type flip flop Dff30.
Control signal DATAH and checking signal CMDVALH by NAND gate NAND30 control with or the output of door XNOR30, if control signal DATAH and checking signal CMDVALH are all high level, with or the inverted value of door XNOR30 output data CMDQ; If not, same or door XNOR30 exports data CMDQ; The inverted value of data CMDQ or data CMDQ is in clock signal MQ<0 > triggering under, from the output of the Q output of d type flip flop Dff30, as data CMD.
When controller sends data C1, the second input same or door XNOR30 does not also have data CMDQ input, so now same or output door XNOR30 does not have output, data forwarding module 130 is not exported yet.
When controller sends data C2, it is C1 that the second input same or door XNOR30 receives data CMDQ() input, now DATAH is low level, so NAND gate NAND30 exports high level, output same or door XNOR30 is exported the D input of C1 to d type flip flop Dff30, in clock signal MQ<0 > triggering under, from the output of the Q output of d type flip flop Dff30, as data CMD.
When controller sends data D1, it is C1 that the second input same or door XNOR30 receives data CMDQ() input, now DATAH is high level.If checking signal CMDVALH high level, with or door XNOR30 output data CMDQ(be C1) inverted value (being C2); If not, a same or door XNOR30 output data CMDQ(is C1).With or the output output C1 of door XNOR30 to the D input of d type flip flop Dff30, in clock signal MQ<0 triggering under, from the Q output output of d type flip flop Dff30, as data CMD.
The first modulation module 140 receives data CMD, after inner modulation, exports the data CMD after modulation to data recombination module 170.
Private data D1D2 ... Dn is DATA, and the treatment circuit of DATA comprises: the second modulation module 150, data cutout module 160, data forwarding module 170.
Controller sends private data D1D2 ... Dn is to modulation module 150, and the data after modulation input to data cutout module 160, after data cutout module 160 intercepting storage data D1, and the data D2D3 after intercepting stores ... Dn is input to data recombination module 170.
The lsi internal circuit data recombination module 170 that Fig. 7 is an embodiment.
AND OR NOT gate AOI40 comprises that the 5th connects the input of not gate N40 with door the 172, the 6th and door the 174, the 3rd NOR gate 176, the three NOR gate outputs.
The 5th receives with the first input end of door 172 the private data DATA modulated through the second modulation module, the 5th with door the second input reception control signal DATAENH of 172, the 6th with door 174 first input end reception control signal COMENH, the 6th receives with the second input of door 174 the data CMD modulated through the first modulation module, and not gate N40 output data are to ic output DO.
When controller sends data C1, control signal DATAENH and control signal COMENH are low level, the DO output low level.
When controller sends data C2, control signal DATAENH is low level, and control signal COMENH is high level, AND OR NOT gate AOI40 gated data CMD, i.e. C1.
When controller sends data D1, control signal DATAENH is low level, and control signal COMENH is high level, AND OR NOT gate AOI40 gated data CMD, and data CMD or be C1 or be C2, by the value decision of checking signal CMDVALH.
When controller sends data D2, control signal DATAENH transfers high level to, and control signal COMENH transfers low level to, AND OR NOT gate AOI40 gating private data DATA, and now private data DATA is data D2.
When controller sends data Dn, control signal DATAENH is high level, and control signal COMENH is low level, AND OR NOT gate AOI40 gating private data DATA, and now private data DATA is data Dn.
In the present embodiment, clock signal MQ<0 > be private data DATA.
In the present embodiment, C1 receives storage module 110 storages through the DIN input of integrated circuit.After C1 stores, together with C2, input validation module 120 is carried out verification.After verification, according to check results, pass through the data after data forwarding module 130 forwards verifications.Data after verification are the data C1C2 after the output modulation after the first modulation module 140 modulation, C1C2 input data recombination module 170.
D1D2 ... Dn inputs the second modulation module 150 and is modulated, and then 160 interceptings of data cutout module store D1, the data D2D3 after intercepting stores ... Dn is input to data recombination module 170.
The single wire transmission circuit of the light-emitting diode integrated circuit cascade signal that Fig. 8 is an embodiment.
A kind of single wire transmission circuit of light-emitting diode integrated circuit cascade data, comprise n integrated circuit of the present invention, be respectively integrated circuit 1, integrated circuit 2 ... integrated circuit n, D1, D2 ... Dn is respectively described integrated circuit 1, integrated circuit 2 ... the private data of integrated circuit n, D1, D2 ... the Dn figure place is all the n position; Also comprise controller, controller is for sending transmission data C1C2D1D2 ... Dn is to integrated circuit 1.
The output DO of integrated circuit 1 connects the input DIN of integrated circuit 2, and the output DO of integrated circuit 2 connects the input DIN of integrated circuit 3 ... the output DO of integrated circuit n-1 connects the input DIN of integrated circuit n.
Controller sends reset signal, and all integrated circuits, after the data decode that intercepting is stored into separately, sending to LED driving module and reset, complete a data refresh cycle.
The sequential relationship of integrated circuit part signal in the present embodiment is described below.
The sequential chart of the integrated circuit part signal that Fig. 3 is an embodiment.
When controller sends C1, checking signal CMDVALH, control signal CMD1H are high level, and control signal CMD2H, control signal DATAH, control signal COMENH, control signal DATAENH are low level.
When controller sends C2, control signal CMD2H, control signal COMENH are high level, control signal CMD1H, control signal DATAH, control signal DATAENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
When controller sends D1, control signal DATAH, control signal COMENH are high level, control signal CMD1H, control signal CMD2H, control signal DATAENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
Controller sends D2D3 ... during Dn, control signal CMD1H, control signal DATAENH are high level, control signal CMD2H, control signal DATAH, control signal COMENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
The single wire transmission circuit of above-mentioned light-emitting diode integrated circuit cascade signal, by fractionation and the merging to the transmission data, can send the common configuration data simultaneously and show data in same frame data, the data redundancy amount is few, than traditional single line communication, take the MCU resource less.The single wire transmission circuit of above-mentioned light-emitting diode integrated circuit cascade signal also carries out verification to the transmission data, effectively avoids probable bit error, has improved the reliability of data.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an integrated circuit, for the treatment of comprising common configuration data C1 and private data D1D2 ... the transmission data C1D1D2 of Dn ... Dn, is characterized in that, comprising:
Receive storage module, for receiving and store common configuration data C1;
Data forwarding module, for forwarding the data that receive after storage module is processed;
The data cutout module, for from private data D1D2 ... intercepting storage data D1 in Dn;
The data recombination module, for the data D2D3 after common configuration data C1 and intercepting storage data ... the Dn restructuring.
2. an integrated circuit, for the treatment of comprising common configuration data C1C2 and private data D1D2 ... the transmission data C1C2D1D2 of Dn ... Dn, is characterized in that, comprising:
Receive storage module, for receiving and store common configuration data C1;
Correction verification module, for receiving common configuration data C1 from described reception storage module, from the data input pin of integrated circuit, receiving common configuration data C2, and carry out verification to described common configuration data C1, C2;
Data forwarding module, for forwarding the data after the correction verification module verification;
The first modulation module, for modulating the data after described verification;
The second modulation module, for modulating private data D1D2 ... Dn;
The data cutout module, for from private data D1D2 ... intercepting storage data D1 in Dn;
The data recombination module, for the data D2D3 after common configuration data C1C2 and intercepting storage data ... the Dn restructuring.
3. integrated circuit according to claim 2, is characterized in that, described reception storage module comprises: not gate N10, not gate N12, AND OR NOT gate AOI10, and m d type flip flop; M d type flip flop is respectively d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm;
Described AND OR NOT gate AOI10 comprise first with the door, second with, the first NOR gate;
Described not gate N10 output connect described first with the door the second input, described not gate N10 input connect described second with the door first input end, the output of described the first NOR gate connects the input of described not gate N12, and the output of described not gate N12 connects the D input of described d type flip flop DFF1;
The Q output of described d type flip flop DFF1 connects the D input of described d type flip flop DFF2, the Q output of described d type flip flop DFF2 connects the D input of described d type flip flop DFF3 ... the Q output of described d type flip flop DFFm-1 connects the D input of described d type flip flop DFFm;
The Q output of described d type flip flop DFFm connect described first with the door first input end;
The input reception control signal CMD1H of described not gate N10, described second receives described transmission data DICOR with the second input of door, described d type flip flop DFF1, d type flip flop DFF2 ... the input end of clock receive clock signal MQ of d type flip flop DFFm<1 >, the Q output of described d type flip flop DFFm output data CMDQ to described first with the first input end of door;
Described control signal CMD1H for to described first with the first input end data of door and described second with the gating of the second fan-in certificate of door, the data of gating are in described clock signal MQ<1 > triggering under, deposit by turn successively into described d type flip flop DFF1, d type flip flop DFF2 ... d type flip flop DFFm.
4. integrated circuit according to claim 3, is characterized in that, whether the described C2 of described correction verification module verification is the inverted value of described C1.
5. integrated circuit according to claim 4, is characterized in that, described correction verification module comprises: not gate N20, not gate N22, AND OR NOT gate AOI20, d type flip flop Dff20, same or door XNOR20, NOR gate NOR20;
Described AND OR NOT gate AOI20 comprise the 3rd with the door, the 4th with the door, the second NOR gate;
The output of described not gate N20 connects the first input end of described NOR gate NOR20, described with or the output of door XNOR20 connect the second input of described NOR gate NOR20, the output of described NOR gate NOR20 connect the described the 3rd with the door the second input, the input of described not gate N22 connect the described the 3rd with the door first input end, the output of described not gate N22 connect the described the 4th with the door the second input, the output of described the second NOR gate connects the D input of described d type flip flop Dff20, described d type flip flop Dff20's
output connect the described the 3rd with the door first input end and the input of described not gate N20;
The input reception control signal CMD2H of described not gate N22, described with or the door XNOR20 first input end receive described transmission data DICOR, described with or the door XNOR20 first input end receive described data CMDQ, the input end of clock receive clock signal MQ of described d type flip flop Dff20<1>, the reset terminal CLR of described d type flip flop Dff20 receives reset signal PRCRL, described d type flip flop Dff20's
output output verification signal CMDVALH to the described the 3rd with the door first input end and the input of described not gate N20;
Described control signal CMD2H for to the described the 3rd with the first input end data of door and the described the 4th with the gating of the second fan-in certificate of door;
Described data DICOR and described data CMDQ by described with or a door XNOR20 press bit check, if be verified as on the contrary, described checking signal CMDVALH is high level, and feeds back to described not gate N20, the continuation verification; If be verified as identically, described checking signal CMDVALH is low level, and feed back to described not gate N20 and the described the 3rd with door, latching CMDVALH is low level.
6. integrated circuit according to claim 5, is characterized in that, the data forwarding module of described common configuration data comprises: NAND gate NAND30, same or door XNOR30, d type flip flop Dff30;
The output of described NAND gate NAND30 connect described with or the first input end of door XNOR30, described with or the output of door XNOR30 connect the D input of described d type flip flop Dff30;
Described NAND gate NAND30 first input end reception control signal DATAH, described NAND gate NAND30 first input end receives described checking signal CMDVALH, described with or the door XNOR30 the second input receive described data CMDQ, the input end of clock receive clock signal MQ of described d type flip flop Dff30<0 >, the Q output output data CMD of described d type flip flop Dff30;
Described control signal DATAH and described checking signal CMDVALH by described NAND gate NAND30 control described with or the output of door XNOR30, if described control signal DATAH and described checking signal CMDVALH are all high level, described with or door XNOR30 export the inverted value of described data CMDQ; If not, described with or the door XNOR30 export described data CMDQ; The inverted value of described data CMDQ or described data CMDQ is in described clock signal MQ<0 > triggering under, from the output of the Q output of described d type flip flop Dff30, as described data CMD.
7. integrated circuit according to claim 6, is characterized in that, described data recombination module comprises: AND OR NOT gate AOI40, not gate N40;
Described AND OR NOT gate AOI40 comprise the 5th with the door, the 6th with the door, the 3rd NOR gate; Described the 3rd NOR gate output connects the input of described not gate N40;
The described the 5th receives the private data DATA after described the second modulation module modulation with the first input end of door, the described the 5th with the door the second input reception control signal DATAENH, the described the 6th with the door first input end reception control signal COMENH, the described the 6th receives with the second input of door the data CMD modulated through described the first modulation module, and described not gate N40 output data are to described ic output.
8. integrated circuit according to claim 7, is characterized in that, described clock signal MQ<0 > be described private data DATA.
9. the single wire transmission circuit of a light-emitting diode integrated circuit cascade data; it is characterized in that; comprise that n according to the described integrated circuit of claim 1 to 8 any one; be respectively integrated circuit 1, integrated circuit 2 ... integrated circuit n; D1, D2 ... Dn is respectively described integrated circuit 1, integrated circuit 2 ... the private data of integrated circuit n; D1, D2 ... the Dn figure place is all the n position, also comprises controller, and described controller is for sending transmission data C1C2D1D2 ... Dn is to integrated circuit 1;
The output DO of integrated circuit 1 connects the input DIN of integrated circuit 2, and the output DO of integrated circuit 2 connects the input DIN of integrated circuit 3 ... the output DO of integrated circuit n-1 connects the input DIN of integrated circuit n;
Integrated circuit 1 intercepting stores D1 and then exports C1C2D2D3 ... Dn is to integrated circuit 2, integrated circuit 2 interceptings store D2 and then export C1C2D3D4 ... Dn is to integrated circuit 3, integrated circuit 3 interceptings store D3 and then export C1C2D4D5 ... Dn is to integrated circuit 4 ... integrated circuit n-1 intercepting stores Dn-1 and then exports C1C2Dn to integrated circuit n.
10. the single wire transmission circuit of light-emitting diode integrated circuit cascade data according to claim 9 is characterized in that:
When described controller sends C1, checking signal CMDVALH, control signal CMD1H are high level, and control signal CMD2H, control signal DATAH, control signal COMENH, control signal DATAENH are low level;
When described controller sends C2, control signal CMD2H, control signal COMENH are high level, control signal CMD1H, control signal DATAH, control signal DATAENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always;
When described controller sends D1, control signal DATAH, control signal COMENH are high level, control signal CMD1H, control signal CMD2H, control signal DATAENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always;
Described controller sends D2D3 ... during Dn, control signal CMD1H, control signal DATAENH are high level, control signal CMD2H, control signal DATAH, control signal COMENH are low level, the value of checking signal CMDVALH depends on the check results of C1 and C2, if the errorless checking signal CMDVALH of C1 and C2 verification is high level, if the wrong checking signal CMDVALH of C1 and C2 verification remains low level always.
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