CN108933788B - FPGA-based RSSP-II protocol MAC code rapid verification device - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/12—Applying verification of the received information
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- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
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- H—ELECTRICITY
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- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
- H04L9/3242—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC
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- H—ELECTRICITY
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Abstract
A RSSP-II protocol MAC code rapid verification device based on FPGA is characterized in that the FPGA1 and the FPGA2 are respectively programmed with the following modules through programming language hardware: the device comprises a data interface module, an MAC scheduling module, a DES module and a dual-channel comparison module. The DES module comprises a DES top module, a DES core module, a Key _ schedule sub-Key generation module and a crp single-round circulation module. The two-channel comparison module is used for communication between the two FPGAs to form a two-out-of-two structure, and when the two FPGA results are inconsistent, the two-channel comparison state mark is sent to the CPU through the data interface module; if the two channels are compared, the subsequent message transmission is carried out, otherwise, an error processing program is entered. The invention adopts a finite-state machine and a design method of a production line, fully considers the consumption of system resources on the basis of ensuring the processing speed, and achieves the balance of speed and area. The invention effectively reduces the CPU resource occupation of the RSSP-II protocol of the high-speed railway vehicle-ground wireless safety communication, greatly improves the data throughput, shortens the authentication time delay and has higher safety and reliability.
Description
Technical Field
The invention relates to the technical field of rail transit safety communication, in particular to a wireless communication System which is suitable for meeting severe requirements on safety and timeliness in the communication process of a CTCS-3 (China train Control System-3) level train operation Control System.
Background
In a communication interaction process between an RBC (radio Block center) radio Block center and a TSRS (temporal Speed Restriction Server) temporary Speed limiting server, between an RBC and an RBC device, and between the RBC device and a vehicle-mounted system device in a CTCS-3 level train control system, according to RSSP-II (Railway Signal Security Protocol-II) Railway Signal safety communication Protocol, the safety requirements for open network communication in EN50159-2 need to be met. And the two communication parties respectively run a message source verification safety program on a MASL message authentication safety layer and generate a message verification code to ensure the authenticity and the integrity of the message in transmission.
Currently, the mainstream message source verification method is to perform mac (message Authentication code) generation and verification in the CPU. However, the implementation of such CPU software programming has many disadvantages:
(1) CPU system resource occupation. The message verification code of the MASL layer takes the DES data encryption standard as a basic algorithm, and a large amount of system resources are consumed and processing time is occupied after multiple rounds of iteration and data processing processes in the generation process. If excessive resources are consumed in the MAC verification process, the CPU as a core arithmetic processing unit hinders the improvement of the processing capability of the device.
(2) The software programming approach is not efficient. The CPU programming mode is adopted to complete the message source verification process, which takes dozens of ms or even longer, and further shortening of the end-to-end communication time delay between the RBC and the vehicle-mounted equipment is limited.
Disclosure of Invention
The invention aims to provide a safe and high-speed verification device of RSSP-II protocol MAC code based on FPGA (field Programmable Gate array) aiming at freeing CPU resource occupation and greatly improving data throughput.
Because the traditional CPU software programming mode realizes that the message source verification process occupies CPU system resources, and the processing efficiency is not high, the method is not beneficial to further improving the performance and the processing capacity of the RBC train control equipment and further shortening the communication time delay between the RBC and the vehicle-mounted equipment.
The technical scheme adopted by the invention is as follows: an FPGA-based RSSP-II protocol MAC code rapid verification device, an FPGA1 communicates with a CPU1 and a wireless module through a UART in a chip, and the CPU1 communicates with a local peripheral control and communication circuit through a 16-bit parallel bus; the FPGA2 communicates with the CPU2 and the wireless module through a UART in a chip, and the CPU2 communicates with a local peripheral control and communication circuit through a 16-bit parallel bus; the dual-channel comparison between the FPGA1 and the FPGA2 is completed through the UART in the chip; the dual-channel comparison between the CPU1 and the CPU2 is completed through UART; the models of the CPU1 and the CPU2 are the same; the FPGA1 and the FPGA2 are both programmed with the following modules through programming language hardware:
a data interface module: the system comprises a CPU, a data processing unit and a data processing unit, wherein the data processing unit is used for receiving data to be processed of the CPU and double-channel MAC check data, and the data processing unit comprises plaintext data, key data, a writing mark and a data ending mark; two 16-to-64-bit data FIFOs are adopted in the data interface module, a control state machine is adopted to carry out state skip according to input data information, 64-bit plaintext and 3 round keys are respectively stored in different registers and transmitted to the MAC scheduling module, a series of control signals of the MAC scheduling module state machine are generated at the same time, and a write-permission mark is output;
and the MAC scheduling module: the DES module is used for generating control marks and register data distribution of the DES module and completing basic operation processes such as XOR operation and the like, and a control state machine is adopted to carry out state skip according to the received data and control marks of the data interface module and the data and control marks generated by the DES module; the MAC scheduling module sends the processed data and control information to the DES module, and controls data operation of the DES module and skip of a state machine;
a DES module: the lower-layer DES algorithm is used for generating the MAC verification code; the DES module comprises a DES top layer module, a DES _ core module, a key _ schedule sub-key generation module and a crp single-round circulation module;
DES top-level module: the instantiation and calling functions of the sub-modules are mainly completed;
DES _ core module: the system is used for finishing initial replacement operation, reverse initial replacement operation and 16-round circulation control, adopts a control state machine to carry out state skip according to control information from an MAC scheduling module, generates a round control mark, outputs a busy mark, an encryption and decryption finishing mark and a 64-bit round DES result, and respectively transmits the round DES result to the MAC scheduling module and the data interface module to carry out state machine control and operation processing;
the Key _ schedule sub-Key generation module: the round key is used for generating 16 rounds of iterative operations, and a pipeline design mode is adopted, namely a first-stage register is inserted behind each basic operation unit, 16 stages of registers are inserted in total, and the value of the previous-stage register is called when the next basic operation unit is executed to form the 16-stage register;
crp single round cycle module: the method is used for completing one round of basic operation in DES operation, including E permutation expansion, XOR operation, S box permutation and P box change; basic operations such as permutation and exclusive-or operation can be realized by using an assign statement, the S box is realized by adopting a table look-up method, the essence of the table look-up method is an RAM, the storage area is corresponding through address input, and 4-bit specific data is output;
a dual-channel comparison module: the two-channel comparison state mark is used for communication between the two FPGAs to form a two-out-of-two structure, and when the two FPGA results are inconsistent, the two-channel comparison state mark is sent to the CPU through the data interface module; if the two channels are compared, the subsequent message transmission is carried out, otherwise, an error processing program is entered.
The wireless module comprises a wireless transceiver and is communicated with the railway system wireless communication equipment.
The invention has the beneficial effects that:
compared with the prior art, the invention has the following advantages:
shortening message source verification time: the message source verification process is completed by using the FPGA-based MAC quick verification device, the time parameter of the FPGA-based MAC quick verification device can reach ns (nanosecond) magnitude, and the data throughput can be greatly improved.
Secondly, improving the reliability of the MAC verification code: and the state machine model is adopted to control interface data flow and MAC verification code generation, so that the correctness of various operation time sequences of the FPGA is ensured, and the reliable generation of the MAC verification code is ensured.
Freeing CPU system resources: the FPGA is used as a coprocessor to complete the MAC verification process, thereby being beneficial to liberating CPU resource occupation and improving the system performance of RBC equipment and train control equipment.
The application scene and range of the RSSP-II protocol are favorably expanded, for example, a railway signal network with more comprehensive coverage is established in the future, and if all communication nodes use the RSSP-II protocol for communication, the reliability and safety of the system are greatly enhanced under the condition that only a small amount of equipment is added.
Drawings
FIG. 1 is a schematic connection diagram of a rapid verification device for MAC codes of RSSP-II protocols based on FPGA;
FIG. 2 is the overall architecture and block partitioning of the MAC authentication code IP core in the RSSP-II protocol;
fig. 3 shows the structure of the DES module and the bottom module division.
Detailed Description
The core idea of the invention is to use FPGA as a coprocessor, design a rapid verification device of RSSP-II protocol MAC code, combine the advantage of FPGA parallel operation, liberate CPU system resources, facilitate the performance improvement of RBC, vehicle-mounted and TSRS equipment, and improve the data throughput. The specific implementation method of the FPGA-based RSSP-II protocol MAC code quick verification device is as follows.
Referring to fig. 1, a connection diagram of the RSSP-II protocol MAC code fast authentication apparatus is shown. The wireless module comprises a wireless transceiver and is communicated with the FPGA through an in-chip UART; the programmable logic array FPGA performs hardware programming and comprises a data interface module, an MAC scheduling module, a DES module and a dual-channel comparison module which are divided as shown in the figure 2; the channel comparison between the FPGAs passes through the UART in the chip; a 16-bit parallel bus is used between the CPU and the FPGA for data transmission; UART is also used for the dual-channel comparison between CPUs; the CPU and the peripheral control circuit use a 16-bit parallel bus to transmit data, and communicate with local external equipment by adopting external circuits such as optical fibers, 422 serial ports and the like.
The two wireless modules have the same model and simultaneously receive and transmit data.
The control state machine is arranged in the data interface module and forms the data interface module together with the data FIFO to realize data scheduling.
The error processing is to send an error flag bit to the CPU, and the CPU performs corresponding error processing including alarming, downtime and other operations. Is an output value of the dual-channel comparison module, so the module is not counted as software arranged in the FPGA or as a module in the FPGA.
The implementation process is as follows.
Firstly, the device receives wireless data of the wireless communication equipment of the railway system through a wireless module, wherein the wireless data comprises information, equipment numbers, secret keys and the like.
And secondly, the wireless module transmits the received data information to the FPGA through the UART in the chip to carry out MAC verification, and the verification process comprises the generation and verification of an MAC verification code. Two FPGAs are used in the device to form a two-out-of-two structure, two channels are compared between the two FPGAs, and if the results are inconsistent, a relevant error processing program is operated.
And thirdly, if the MAC is verified correctly, the FPGA transmits the message to the CPU through the on-chip bus, and the CPU drives a local external and communication circuit to perform local data distribution and control output. The CPU part also forms a two-out-of-two structure to ensure the safety of the system.
The core of the device is the design of an FPGA part, and referring to FIG. 2, the module division in the FPGA design is given. The FPGA completes the generation and verification process of the MAC verification code, and the module division comprises a data interface module, an MAC scheduling module, a DES module and a dual-channel comparison module.
The data interface module is used for receiving data to be processed by the CPU and double-channel MAC check data, and the data comprises plaintext data, key data, a writing mark, a data ending mark and the like. The plaintext and the key are both input by 16 bits, but the plaintext and the key used by the MAC verification code are 64 bits, so that two 16-to-64-bit data FIFOs (First In First out) are adopted In the data interface module, a control state machine is adopted to perform state skip according to input data information, the 64-bit plaintext and 3 round keys are respectively stored In different registers and transmitted to the MAC scheduling module, a series of control signals of the MAC scheduling module state machine are generated at the same time, and a write-allowed flag is output.
The MAC scheduling module is used for generating a control mark and register data allocation of the DES module and completing basic operation processes such as XOR operation and the like. Adopting a control state machine to carry out state skip according to the received data and control marks of the data interface module and the data and control marks generated by the DES module; and the MAC scheduling module sends the processed data and the control information to the DES module, and controls the data operation of the DES module and the jump of the state machine.
The DES module is used for realizing a bottom-layer DES algorithm generated by the MAC verification code and is the key of an IP core of the MAC verification code. Referring to fig. 3, the DES module includes a DES top module, a DES _ core module, a key _ schedule sub-key generation module, and a crp single-round loop module. The DES top-level module mainly completes the instantiation and calling functions of the sub-modules. The DES _ core module is used for completing initial replacement operation, reverse initial replacement operation and 16-round circulation control, a control state machine is adopted to carry out state skip according to control information from the MAC scheduling module, round control marks are generated, a busy mark, an encryption and decryption completion mark and a 64-bit round DES result are output and are respectively transmitted to the MAC scheduling module and the data interface module to carry out state machine control and operation processing. The Key _ schedule sub-Key generation module is used for generating a round Key of 16 rounds of iterative operations, and a pipeline design mode is adopted, namely a first-stage register is inserted behind each basic operation unit, 16-stage registers are inserted in total, and the value of the first-stage register is called to form the 16-stage register when the next basic operation unit is executed. The design of the production line is beneficial to improving the system efficiency and the operation processing speed. The crp single-round circulation module is used for completing one round of basic operation in DES operation, and comprises expansion E permutation, exclusive-or operation, S box permutation and P box change. Basic operations such as permutation and exclusive-or operation can be realized by using assign sentences, the S box is a unique nonlinear component in the block encryption algorithm, is a safety key of the whole encryption algorithm, and is realized by adopting a table look-up method, the table look-up method is essentially an RAM, the storage area is corresponded by address input, and 4-bit specific data is output.
The dual-channel comparison module is used for communication between the two FPGAs to form a two-out-of-two structure, and when the two FPGA results are inconsistent, the dual-channel comparison state mark is sent to the CPU through the data interface module. If the two channels are compared, the subsequent message transmission is carried out, otherwise, an error processing program is entered.
All the modules are combined in the top module, and the internal connection is as shown in fig. 2, namely, the design of the core FPGA part of the RSSP-II protocol MAC verification device is completed.
The key points of the technology of the invention are as follows:
1. FPGA partial design, module division and specific design of each module. The design idea of area and speed balance is comprehensively considered, a finite-state machine and a pipeline design method are adopted in the design, the consumption of system resources is fully considered on the basis of ensuring the processing speed, and the balance between the speed and the area is achieved.
2. The CPU + FPGA combined processing mode, the CPU and the interface matching, communication and logic control of the local external equipment.
3. The two-channel comparison process of the FPGA and the two-channel comparison of the CPU, and the two-out-of-two structural design can improve the safety and reliability of the system.
Claims (2)
1. An RSSP-II protocol MAC code rapid verification device based on FPGA is characterized in that the FPGA1 communicates with a CPU1 and a wireless module through UART in a chip, and the CPU1 communicates with a local peripheral control and communication circuit through a 16-bit parallel bus; the FPGA2 communicates with the CPU2 and the wireless module through a UART in a chip, and the CPU2 communicates with a local peripheral control and communication circuit through a 16-bit parallel bus; the dual-channel comparison between the FPGA1 and the FPGA2 is completed through the UART in the chip; the dual-channel comparison between the CPU1 and the CPU2 is completed through UART; the models of the CPU1 and the CPU2 are the same; the FPGA1 and the FPGA2 are both programmed with the following modules through programming language hardware:
a data interface module: the system comprises a CPU, a data processing unit and a data processing unit, wherein the data processing unit is used for receiving data to be processed of the CPU and double-channel MAC check data, and the data processing unit comprises plaintext data, key data, a writing mark and a data ending mark; two 16-to-64-bit data FIFOs are adopted in the data interface module, a control state machine is adopted to carry out state skip according to input data information, 64-bit plaintext and 3 round keys are respectively stored in different registers and transmitted to the MAC scheduling module, a series of control signals of the MAC scheduling module state machine are generated at the same time, and a write-permission mark is output;
and the MAC scheduling module: the device is used for generating a control mark of a DES module and distributing register data, and finishing the basic operation process of XOR operation; adopting a control state machine model to carry out state skip according to the received data and control marks of the data interface module and the data and control marks generated by the DES module; the MAC scheduling module sends the processed data and control information to the DES module, and controls data operation of the DES module and skip of a state machine;
a DES module: the lower-layer DES algorithm is used for generating the MAC verification code; the DES module comprises a DES top layer module, a DES _ core module, a key _ schedule sub-key generation module and a crp single-round circulation module;
DES top-level module: the instantiation and calling functions of the sub-modules are mainly completed;
DES _ core module: the system is used for finishing initial replacement operation, reverse initial replacement operation and 16-round circulation control, adopts a control state machine to carry out state skip according to control information from an MAC scheduling module, generates a round control mark, outputs a busy mark, an encryption and decryption finishing mark and a 64-bit round DES result, and respectively transmits the round DES result to the MAC scheduling module and the data interface module to carry out state machine control and operation processing;
the Key _ schedule sub-Key generation module: the round key is used for generating 16 rounds of iterative operations, and a pipeline design mode is adopted, namely a first-stage register is inserted behind each basic operation unit, 16 stages of registers are inserted in total, and the value of the previous-stage register is called when the next basic operation unit is executed to form the 16-stage register;
crp single round cycle module: the method is used for completing one round of basic operation in DES operation, including E permutation expansion, XOR operation, S box permutation and P box change; basic operations such as permutation and exclusive-or operation can be realized by using an assign statement, the S box is realized by adopting a table look-up method, the essence of the table look-up method is an RAM, the storage area is corresponding through address input, and 4-bit specific data is output;
a dual-channel comparison module: the two-channel comparison state mark is used for communication between the two FPGAs to form a two-out-of-two structure, and when the two FPGA results are inconsistent, the two-channel comparison state mark is sent to the CPU through the data interface module; if the two channels are compared, the subsequent message transmission is carried out, otherwise, an error processing program is entered.
2. The device for rapidly verifying the RSSP-II protocol MAC code based on the FPGA of claim 1, wherein the wireless module comprises a wireless transceiver, and the wireless module is communicated with a railway system wireless communication device.
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| CN113411198B (en) * | 2021-04-29 | 2022-07-15 | 卡斯柯信号有限公司 | Communication method and device based on dual channels and RSSP-I, electronic equipment and storage medium |
| CN113094762B (en) * | 2021-04-30 | 2021-12-07 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN113904789B (en) * | 2021-08-17 | 2024-03-29 | 卡斯柯信号有限公司 | Encryption method, equipment and storage medium of railway safety communication protocol |
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