CN108933788A - A kind of RSSP-II agreement MAC code fast verification device based on FPGA - Google Patents
A kind of RSSP-II agreement MAC code fast verification device based on FPGA Download PDFInfo
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- CN108933788A CN108933788A CN201810715086.4A CN201810715086A CN108933788A CN 108933788 A CN108933788 A CN 108933788A CN 201810715086 A CN201810715086 A CN 201810715086A CN 108933788 A CN108933788 A CN 108933788A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/12—Applying verification of the received information
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3236—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions
- H04L9/3242—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using cryptographic hash functions involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W12/00—Security arrangements; Authentication; Protecting privacy or anonymity
Abstract
A kind of RSSP-II agreement MAC code fast verification device based on FPGA has by programming language hardware programming with lower module in FPGA1 and FPGA2: data interface module, MAC scheduler module, DES module, binary channels comparison module.Wherein DES module includes DES backform block, DES core module, Key_schedule sub-key generation module, crp single-wheel loop module.Binary channels comparison module is used between two FPGA communicate, and constitutes two and takes two structures, when two FPGA results are inconsistent, send binary channels to CPU by data interface module and compares Status Flag；If comparing by binary channels, subsequent message transmission is carried out, otherwise enters error handler.The present invention fully takes into account the consumption of system resource on the basis of guaranteeing processing speed using the design method of finite state machine and assembly line, has reached the balance of speed and area.The cpu resource that the present invention effectively reduces high-speed railway car-ground radio secure communication RSSP-II agreement occupies, and data throughout is greatly improved, and authenticates time delay with shortening vehicle, has higher safety and reliability.
Description
Technical field
The present invention relates to rail traffic safety communication technology field, more particularly to being adapted to CTCS-3 (Chinese
Train Control System-3) there are rigors to the timely ductility of safety in grade train operation control system communication process
Wireless communication system.
Background technique
The radio block center (Radio Block Center) RBC and TSRS in CTCS-3 grades of train control systems
(Temporary Speed Restriction Server) temporary speed limitation server, RBC and RBC equipment, RBC equipment with it is vehicle-mounted
Between system equipment during communication interaction, according to RSSP-II (Railway Signal Security Protocol-II) iron
Signals security communication protocol regulation in road needs to meet in EN50159-2 for the safety requirements of open network communication.Communicating pair
It is separately operable message source verifying security procedure in MASL message identification safe floor, generates Message Authentication Code to guarantee message in transmission
Authenticity and integrity.
The message source verification method of mainstream is progress MAC (Message Authentication Code) in CPU at present
Generation and checking procedure.But there are many drawbacks for the implementation of this CPU software programming:
(1) cpu system resource occupation.MASL layers of Message Authentication Code is generated using DES data encryption standards as rudimentary algorithm
In the process through excessive wheel iteration and data handling procedure, needs to consume a large amount of system resource and occupy the processing time.CPU conduct
The operation processing unit of core, if the promotion by excessive resource cost in MAC checking procedure, to the processing capacity of equipment
It is an obstruction.
(2) software programming mode treatment effeciency is not high.Message source verification process is completed using CPU programming mode and needs tens
The ms even longer time, limit the further shortening of RBC Yu mobile unit end-to-end communication time delay.
Summary of the invention
The purpose of the present invention is aiming at the problems existing in the prior art, provide a kind of safety high speed based on FPGA
The verifying device of the RSSP-II agreement MAC code of (Field Programmable Gate Array), it is intended to liberate cpu resource and account for
With greatling improve data throughout.
Since traditional CPU software programming mode realizes that message source verification process occupies cpu system resource, and treatment effeciency is not
Height, be unfavorable for RBC column control equipment performance and processing capacity further promotion and RBC and vehicle equipment communication time delay into
One step shortens.
The technical scheme adopted by the invention is that: a kind of RSSP-II agreement MAC code fast verification device based on FPGA,
FPGA1 is communicated by UART in piece with CPU1 and wireless module, and CPU1 is contained by 16 parallel-by-bit buses with locally outer
System and telecommunication circuit communication；FPGA2 is communicated by UART in piece with CPU2 and wireless module, and CPU2 passes through 16 parallel-by-bits
Bus is communicated with local peripheral control and telecommunication circuit；It is completed compared with binary channels by UART in piece between FPGA1 and FPGA2；
It is completed compared with binary channels by UART between CPU1 and CPU2；The model of above-mentioned CPU1 and CPU2 is identical；Above-mentioned FPGA1 and FPGA2
In have by programming language hardware programming with lower module:
Data interface module: for receiving CPU pending data and binary channels MAC verification data, including it is clear data, close
Key data write mark, end-of-data mark；Two 16 turns 64 data FIFO are used inside data interface module, and are used
State of a control machine carries out state transition according to input data information, 64 plaintexts and 3 round key is stored in difference respectively and posted
Storage is simultaneously transmitted to MAC scheduler module, while generating a series of control signals of MAC scheduler module state machine, and export permission
Write mark；
MAC scheduler module: for generating control mark and the register data distribution of DES module, and XOR operation is completed
Equal basic operations process, using state of a control machine, according to the data of the data interface module received and control mark, and
The data and control that DES module generates indicate jumping for carry out state；MAC scheduler module sends out the data of processing and control information
It send to DES module, controls the data manipulation of DES module and jumping for state machine；
DES module: the bottom DES algorithm generated for realizing mac authentication code；DES module include DES top-level module,
DES_core module, key_schedule sub-key generation module, crp single-wheel loop module；
DES top-level module: the main instantiation for completing submodule and calling function；
DES_core module: for completing initial permutation operation, inverse initial permutation operation, 16 wheel loop controls, using control
State machine processed carries out state transition according to the control information from MAC scheduler module, generates wheel control mark, exports as busy mark
Will, encryption and decryption complement mark and 64 a wheel DES as a result, be respectively sent to MAC scheduler module and data interface module into
The control of row state machine and calculation process；
Key_schedule sub-key generation module: it for generating the round key of 16 wheel interative computations, is set using assembly line
Meter mode is inserted into level-one register that is, after each basic processing unit, is inserted into 16 grades of registers, next basic unit altogether
The register for calling the value of upper level register just to constitute 16 grades when execution；
Crp single-wheel loop module: for completing the wheel basic operation in DES operation, including extension E displacement, exclusive or fortune
It calculates, the displacement of S box and P box change；The basic operations such as displacement and XOR operation assign sentence can be used to realize, S box uses
Look-up table is realized that the essence of look-up table is a RAM, and the correspondence for carrying out memory block, the spy of output 4 are inputted by address
Fixed number evidence；
Binary channels comparison module: for being communicated between two FPGA, two is constituted and takes two structures, when two FPGA results are inconsistent
When, binary channels is sent to CPU by data interface module and compares Status Flag；If comparing by binary channels, subsequent disappear is carried out
Breath transmission, otherwise enters error handler.
The wireless module includes wireless transmitter, which is led to railway system's wireless telecom equipment
Letter.
The beneficial effects of the present invention are:
With existing Technical comparing, advantages of the present invention has the following:
1. shortening the message source verification time: authenticated using message source is completed based on the MAC fast verification device of FPGA
Journey, time parameter can achieve ns (nanosecond) magnitude, can greatly improve data throughout.
2. improving the reliability of mac authentication code: the circulation of adoption status machine model cootrol interface data and mac authentication code are raw
At, it is ensured that the correctness of all kinds of arithmetic operation timing of FPGA, it is ensured that reliable to generate mac authentication code.
3. liberation cpu system resource: using FPGA as coprocessor, complete mac authentication process, be conducive to liberate CPU
Resource occupation can promote the system performance of RBC equipment and column control equipment.
4. being conducive to extend the application scenarios and range of RSSP-II agreement, such as following establish covers more comprehensively iron
Road signal network, if each communication node is equally communicated using RSSP-II agreement, in the case where only increasing a small amount of equipment,
Greatly enhance the reliability and security of system.
Detailed description of the invention
Fig. 1 is the connection schematic diagram of the RSSP-II agreement MAC code fast verification device based on FPGA；
Fig. 2 is that the overall architecture and module of mac authentication code IP kernel in RSSP-II agreement divide；
Fig. 3 is that the framework of DES module and bottom module divide.
Specific embodiment
Core of the invention thought is to use FPGA as coprocessor, designs a kind of RSSP-II agreement MAC code and quickly tests
Card device liberates cpu system resource, is conducive to RBC, vehicle-mounted, TSRS equipment performance mentions in conjunction with the advantage of FPGA concurrent operation
It rises, improves data throughout.This RSSP-II agreement MAC code fast verification device concrete methods of realizing based on FPGA is as follows.
Referring to Fig. 1, the connection schematic diagram of RSSP-II agreement MAC code fast verification device is given.The wireless module packet
Wireless transmitter is included, is communicated with FPGA by UART in piece；Programmable logic array FPGA carries out hardware programming, including
It includes data interface module, MAC scheduler module, DES module, binary channels comparison module that module shown in Fig. 2, which divides,；Channel between FPGA
Compare through UART in piece；Carried out data transmission between CPU and FPGA using 16 parallel-by-bit buses；Binary channels is more same between CPU
Sample uses UART；CPU and peripheral control circuits are carried out data transmission using 16 parallel-by-bit buses, are adopted with local external device communication
With the external circuits such as optical fiber and 422 serial ports.
Two wireless module models are identical, and sending and receiving data simultaneously.
State of a control machine is inside data interface module and data FIFO collectively forms data interface module, realizes data
Scheduling.
Error handle is to send an error flag position to CPU, carries out corresponding error handle by CPU, including alarm, delay
The operation such as machine.It is an output valve of binary channels comparison module, therefore does not can be regarded as the software being placed in FPGA, also not as FPGA
Internal module.
Realization process is as follows.
The first step, the present apparatus by wireless module receive railway system's wireless telecom equipment wireless data, including message,
Device number, key etc..
The data information received is transferred to FPGA by UART in piece, carries out mac authentication by second step, wireless module,
Verification process includes the generation and verification of mac authentication code.Constitute two using two FPGA in device and take two structures, between two FPGA into
Row binary channels compares, and relevant error processing routine is run if result is inconsistent.
Third step, if mac authentication is correct, FPGA posts messages to CPU by on-chip bus, and CPU driving is local outer
Portion and communicating circuit carry out local data distribution and control output.CPU part equally constitutes two and takes two structures, with safeguards system
Safety.
Core is the design of FPGA portion in the present apparatus, and referring to fig. 2, the module given in FPGA design divides.FPGA
It is middle complete mac authentication code generation and checking procedure, module divide include data interface module, MAC scheduler module, DES module,
Binary channels comparison module.
The data interface module is for receiving CPU pending data and binary channels MAC verification data, including plaintext number
According to, key data, write mark, end-of-data mark etc..Here plaintext and key is all made of 16 inputs, but mac authentication
The plaintext and key that code uses are 64, therefore two 16 turns 64 data FIFO are used inside data interface module
(First In First Out), and state of a control machine is used, state transition is carried out according to input data information, it is bright by 64
Text and 3 round key are stored in different registers respectively and transmit to MAC scheduler module, while generating MAC scheduler module state machine
A series of control signals, and export allow to write mark.
The MAC scheduler module is used to generate control mark and the register data distribution of DES module, and completes exclusive or fortune
The basic operations processes such as calculation.Using state of a control machine, indicated according to the data of the data interface module received and control, and
The data and control that DES module generates indicate jumping for carry out state；MAC scheduler module sends out the data of processing and control information
It send to DES module, controls the data manipulation of DES module and jumping for state machine.
The bottom DES algorithm that the DES module generates for realizing mac authentication code is the key that mac authentication code IP kernel.
Referring to Fig. 3, DES module includes DES top-level module, DES_core module, key_schedule sub-key generation module, crp mono-
Take turns loop module.DES top-level module mainly completes instantiation and the calling function of submodule.DES_core module is for completing just
Beginning replacement operator, inverse initial permutation operation, 16 wheel loop controls, using state of a control machine, according to the control from MAC scheduler module
Information processed carries out state transition, generates wheel control mark, exports as busy mark, encryption and decryption complement mark and 64 wheels
DES is as a result, be respectively sent to MAC scheduler module and data interface module progress state machine control and calculation process.Key_
Schedule sub-key generation module is used to generate the round key of 16 wheel interative computations, using the pipeline design mode, i.e., every
It is inserted into level-one register after one basic processing unit, is inserted into 16 grades of registers altogether, is called when next basic unit executes
The value of level-one register just constitutes 16 grades of register.The design of assembly line is conducive to improve system effectiveness and calculation process speed
Degree.Crp single-wheel loop module is used to complete the wheel basic operation in DES operation, including extension E displacement, XOR operation, S box
Displacement and the variation of P box.The basic operations such as displacement and XOR operation assign sentence can be used to realize that S box is block encryption
Unique non-linear components in algorithm, are the safety-criticals of entire Encryption Algorithm, are realized using look-up table, the sheet of look-up table
Matter is a RAM, and the correspondence for carrying out memory block, the specific data of output 4 are inputted by address.
The binary channels comparison module is used between two FPGA communicate, and constitutes and two takes two structures, when two FPGA results not
When consistent, binary channels is sent to CPU by data interface module and compares Status Flag.If being compared by binary channels, after carrying out
Continuous message transmission, otherwise enters error handler.
Above-mentioned all modules are merged in top-level module, internal connection is as shown in Fig. 2, complete RSSP-II agreement
The design of the core FPGA portion of mac authentication device.
Key problem in technology point of the invention is:
1, FPGA portion designs, and module divides and the specific design of each module.Comprehensively consider area and velocity balance
Mentality of designing, using the design method of finite state machine and assembly line in design, on the basis of guaranteeing processing speed, sufficiently
In view of the consumption of system resource, the balance of speed and area is reached.
2, the combined treatment mode of CPU+FPGA, Interface Matching, communication and the logic control of CPU and local external equipment.
3, the binary channels comparison procedure of FPGA and the binary channels of CPU compare, and two, which take two structure design to be able to ascend, is
The safety and reliability of system.
Claims (2)
1. a kind of RSSP-II agreement MAC code fast verification device based on FPGA, which is characterized in that FPGA1 passes through UART in piece
It is communicated with CPU1 and wireless module, CPU1 is communicated by 16 parallel-by-bit buses with local peripheral control and telecommunication circuit；
FPGA2 is communicated by UART in piece with CPU2 and wireless module, and CPU2 is contained by 16 parallel-by-bit buses with locally outer
System and telecommunication circuit communication；It is completed compared with binary channels by UART in piece between FPGA1 and FPGA2；Binary channels between CPU1 and CPU2
Compare and is completed by UART；The model of above-mentioned CPU1 and CPU2 is identical；It is hard by programming language in above-mentioned FPGA1 and FPGA2
Part is programmed with lower module:
Data interface module: for receiving CPU pending data and binary channels MAC verification data, including clear data, cipher key number
According to, write mark, end-of-data mark；Two 16 turns 64 data FIFO are used inside data interface module, and using control
State machine carries out state transition according to input data information, 64 plaintexts and 3 round key is stored in different registers respectively
And it is transmitted to MAC scheduler module, while generating a series of control signals of MAC scheduler module state machine, and output allows to write mark
Will；
MAC scheduler module: for generating control mark and the register data distribution of DES module, and the bases such as XOR operation are completed
This calculating process；Using state of a control machine model, indicated according to the data of the data interface module received and control, and
The data and control that DES module generates indicate jumping for carry out state；MAC scheduler module sends out the data of processing and control information
It send to DES module, controls the data manipulation of DES module and jumping for state machine；
DES module: the bottom DES algorithm generated for realizing mac authentication code；DES module includes DES top-level module, DES_
Core module, key_schedule sub-key generation module, crp single-wheel loop module；
DES top-level module: the main instantiation for completing submodule and calling function；
DES_core module: for completing initial permutation operation, inverse initial permutation operation, 16 wheel loop controls, using control shape
State machine carries out state transition according to the control information from MAC scheduler module, generates and takes turns control mark, exports as busy mark, adds
Decryption complement mark and the one of 64 wheel DES are as a result, be respectively sent to MAC scheduler module and data interface module progress state
Machine control and calculation process；
Key_schedule sub-key generation module: for generating the round key of 16 wheel interative computations, using the pipeline design side
Formula is inserted into level-one register that is, after each basic processing unit, is inserted into 16 grades of registers altogether, and next basic unit executes
When call the value of upper level register just to constitute 16 grades of register；
Crp single-wheel loop module: for completing the wheel basic operation in DES operation, including extension E displacement, XOR operation, S
Box displacement and the variation of P box；The basic operations such as displacement and XOR operation assign sentence can be used to realize, S box is used and tabled look-up
Method is realized that the essence of look-up table is a RAM, and the correspondence for carrying out memory block, the certain number of output 4 are inputted by address
According to；
Binary channels comparison module: for communicating between two FPGA, composition two takes two structures, when two FPGA results are inconsistent,
Binary channels, which is sent, to CPU by data interface module compares Status Flag；If comparing by binary channels, subsequent message biography is carried out
It is defeated, otherwise enter error handler.
2. a kind of RSSP-II agreement MAC code fast verification device based on FPGA according to claim 1, feature exist
In the wireless module includes wireless transmitter, which is communicated with railway system's wireless telecom equipment.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113094762A (en) * | 2021-04-30 | 2021-07-09 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN113904789A (en) * | 2021-08-17 | 2022-01-07 | 卡斯柯信号有限公司 | Encryption method, equipment and storage medium of railway safety communication protocol |
| WO2022227472A1 (en) * | 2021-04-29 | 2022-11-03 | 卡斯柯信号有限公司 | Communication method and apparatus based on dual channel and rssp-i, and electronic device and storage medium |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102448059A (en) * | 2011-11-23 | 2012-05-09 | 南京航空航天大学 | Encryption and decryption circuit structure applied to ZigBee protocol and control method thereof |
| US20130054946A1 (en) * | 2011-08-25 | 2013-02-28 | Microsoft Corporation | Digital signing authority dependent platform secret |
| CN103675440A (en) * | 2013-05-22 | 2014-03-26 | 国家电网公司 | Power efficiency monitoring terminal and monitoring method thereof |
| CN103746976A (en) * | 2013-12-30 | 2014-04-23 | 上海自动化仪表股份有限公司 | Communication method for FPGA (Field Programmable Gate Array)-based diverse driving system |
| CN104135469A (en) * | 2014-07-04 | 2014-11-05 | 西南交通大学 | An improved solution for increasing safety of RSSP-II protocol |
| CN104166353A (en) * | 2014-08-18 | 2014-11-26 | 中国航天科技集团公司第九研究院第七七一研究所 | Multi-channel data collection control circuit and method for satellite |
| CN206096813U (en) * | 2016-04-18 | 2017-04-12 | 北京交大微联科技有限公司杭州分公司 | Trouble safety signal output device based on FPGA no. 2 gets two comparators |
| CN107911198A (en) * | 2017-11-15 | 2018-04-13 | 卡斯柯信号有限公司 | Interface realizing method based on safe coding Yu railway signal security protocol RSSP II |
-
2018
- 2018-07-03 CN CN201810715086.4A patent/CN108933788B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130054946A1 (en) * | 2011-08-25 | 2013-02-28 | Microsoft Corporation | Digital signing authority dependent platform secret |
| CN102448059A (en) * | 2011-11-23 | 2012-05-09 | 南京航空航天大学 | Encryption and decryption circuit structure applied to ZigBee protocol and control method thereof |
| CN103675440A (en) * | 2013-05-22 | 2014-03-26 | 国家电网公司 | Power efficiency monitoring terminal and monitoring method thereof |
| CN103746976A (en) * | 2013-12-30 | 2014-04-23 | 上海自动化仪表股份有限公司 | Communication method for FPGA (Field Programmable Gate Array)-based diverse driving system |
| CN104135469A (en) * | 2014-07-04 | 2014-11-05 | 西南交通大学 | An improved solution for increasing safety of RSSP-II protocol |
| CN104166353A (en) * | 2014-08-18 | 2014-11-26 | 中国航天科技集团公司第九研究院第七七一研究所 | Multi-channel data collection control circuit and method for satellite |
| CN206096813U (en) * | 2016-04-18 | 2017-04-12 | 北京交大微联科技有限公司杭州分公司 | Trouble safety signal output device based on FPGA no. 2 gets two comparators |
| CN107911198A (en) * | 2017-11-15 | 2018-04-13 | 卡斯柯信号有限公司 | Interface realizing method based on safe coding Yu railway signal security protocol RSSP II |
Non-Patent Citations (1)
| Title |
|---|
| 郭伟等: "RSSP-Ⅱ铁路信号安全通信协议的安全性分析", 《铁道学报》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022227472A1 (en) * | 2021-04-29 | 2022-11-03 | 卡斯柯信号有限公司 | Communication method and apparatus based on dual channel and rssp-i, and electronic device and storage medium |
| CN113094762A (en) * | 2021-04-30 | 2021-07-09 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN113094762B (en) * | 2021-04-30 | 2021-12-07 | 北京数盾信息科技有限公司 | Data processing method and device and signature verification server |
| CN113904789A (en) * | 2021-08-17 | 2022-01-07 | 卡斯柯信号有限公司 | Encryption method, equipment and storage medium of railway safety communication protocol |
| CN113904789B (en) * | 2021-08-17 | 2024-03-29 | 卡斯柯信号有限公司 | Encryption method, equipment and storage medium of railway safety communication protocol |
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| CN108933788B (en) | 2020-11-06 |
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