CN103489921A - Thin film transistor, manufacturing method thereof, array substrate and display device - Google Patents
Thin film transistor, manufacturing method thereof, array substrate and display device Download PDFInfo
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- CN103489921A CN103489921A CN201310456840.4A CN201310456840A CN103489921A CN 103489921 A CN103489921 A CN 103489921A CN 201310456840 A CN201310456840 A CN 201310456840A CN 103489921 A CN103489921 A CN 103489921A
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- 239000010409 thin film Substances 0.000 title claims abstract description 32
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- 230000037230 mobility Effects 0.000 description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 10
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- CXKCTMHTOKXKQT-UHFFFAOYSA-N cadmium oxide Inorganic materials [Cd]=O CXKCTMHTOKXKQT-UHFFFAOYSA-N 0.000 description 4
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- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052738 indium Inorganic materials 0.000 description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Abstract
The embodiment of the invention provides a thin film transistor, a manufacturing method of the thin film transistor, an array substrate and a display device and relates to the technical field of display. On the premise that the pixel aperture ratio is not influenced, the width to length ratio of a channel of the thin film transistor can be increased. The thin film transistor comprises source electrodes, drain electrodes, grid electrodes and a semiconductor active layer. The drain electrodes cover the periphery of the semiconductor active layer. The drain electrodes are located in the central area of the semiconductor active layer. An insulating layer is arranged between the source electrodes and the drain electrodes.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of thin-film transistor and manufacture method thereof, array base palte and display unit.
Background technology
TFT-LCD(Thin Film Transistor Liquid Crystal Display, thin film transistor-liquid crystal display) as a kind of panel display apparatus, because it has the characteristics such as little, low in energy consumption, the radiationless and cost of manufacture of volume is relatively low, and be applied to more and more in the middle of high-performance demonstration field.
In TFT-LCD, quality as the thin-film transistor TFT of switch element is particularly important, the general structure of TFT can be as shown in Figure 1, mainly comprise source electrode 101, drain 102 and grid 103, wherein, source electrode 101 usually adopts with layer metal material and makes with drain electrode 102, also has semiconductor active layer 11 between source drain region and gate metal layer, and the semiconductor active layer 11 that is arranged in grid 103 tops, zone forms shown in TFT raceway groove 10(Fig. 1 dotted line).In prior art, the material of making this semiconductor active layer 11 is amorphous silicon (A-Si).The mobility of a kind of like this TFT of structure is approximately 0.5cm2/Vs.Yet, along with the display device size becomes greatly gradually, require display device to there is more high-resolution and high-frequency drive performance.Therefore, require TFT to there is high mobility and high-performance.In order to improve the electron mobility of semiconductor active layer, usually adopting electron mobility is the conductor oxidate material of tens times of amorphous silicon layer mobilities, as IGZO(Indium Gallium Zinc Oxide, indium gallium zinc oxide), as the semiconductor active layer of TFT.
In prior art, adopt IGZO generally can adopt hole as shown in Figure 2 to hole mode (Hole Type) as the TFT structure of semiconductor active layer 11, wherein the source electrode 101 of TFT is electrically connected to IGZO semiconductor active layer 11 by via hole 21 and via hole 22 respectively with the drain electrode 102 of TFT; Perhaps column mode (Bar Typer) as shown in Figure 3, wherein the source electrode 101 of TFT and the drain electrode 102 of TFT cover the both sides of IGZO semiconductor active layers 11.Yet breadth length ratio (W:L) less of the TFT raceway groove 10 in above-mentioned two kinds of structures, therefore the time that the source electrode of TFT and drain electrode need in conducting is longer, response speed in the time of so can reducing the conducting of TFT raceway groove, thereby the display effect of reduction display unit.
Summary of the invention
Embodiments of the invention provide a kind of thin-film transistor and manufacture method, array base palte and display unit, under the prerequisite that does not affect pixel aperture ratio, can increase the breadth length ratio of thin film transistor channel.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the present invention provides a kind of thin-film transistor, comprises source electrode, drain and gate, and semiconductor active layer;
Described source electrode covers the surrounding of described semiconductor active layer, and described drain electrode is positioned at the central area of described semiconductor active layer, between described source electrode and drain electrode, is provided with insulating barrier.
The embodiment of the present invention a kind of array base palte is provided on the other hand, comprise: a plurality of pixel cells that are the matrix form arrangement that defined by grid line and data wire, described pixel cell comprises pixel electrode, also comprise any one thin-film transistor as above, the source electrode of described thin-film transistor is electrically connected to described data wire; The drain electrode of described thin-film transistor is electrically connected to described pixel electrode.
The embodiment of the present invention a kind of display unit is provided on the other hand, comprise any one array base palte as above.
The another aspect of the embodiment of the present invention provides a kind of manufacture method of thin-film transistor, and described method comprises:
Make semiconductor active layer on the substrate that is formed with successively grid and gate insulator;
Make metal level at the substrate surface that is formed with above-mentioned pattern, and form source electrode by composition technique; Wherein, described source electrode covers the surrounding of described semiconductor active layer, and exposes the central area of described semiconductor active layer;
Make insulating barrier at the substrate surface that is formed with above-mentioned pattern, and form the via hole of described insulating barrier by composition technique in the central area that is positioned at described semiconductor active layer;
Form drain electrode at the substrate surface that is formed with above-mentioned pattern, described drain electrode covers described via hole.
The embodiment of the present invention provides a kind of thin-film transistor and manufacture method, array base palte and display unit.This thin-film transistor comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can under the prerequisite that does not affect pixel aperture ratio, increase the breadth length ratio of thin film transistor channel, thus the response speed while improving the thin film transistor channel conducting, the display effect of lifting display unit.
The accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of a kind of TFT that Fig. 1 provides for prior art;
The structural representation of a kind of array base palte that Fig. 2 provides for prior art;
The structural representation of the another kind of array base palte that Fig. 3 provides for prior art;
The structural representation of a kind of TFT that Fig. 4 provides for the embodiment of the present invention;
A kind of array base palte plan structure schematic diagram that Fig. 5 provides for the embodiment of the present invention;
The another kind of TFT structural representation that Fig. 6 provides for the embodiment of the present invention;
The another kind of array base palte plan structure schematic diagram that Fig. 7 provides for the embodiment of the present invention;
The manufacture method flow chart of a kind of TFT that Fig. 8 provides for the embodiment of the present invention;
The manufacture method flow chart of the another kind of TFT that Fig. 9 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making under the creative work prerequisite the every other embodiment obtained, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of thin-film transistor TFT, and as shown in Figure 4, comprise source electrode 101, drain 102 and grid 103, and semiconductor active layer 11;
It should be noted that, the central area G of semiconductor active layer 11 can refer to the part that semiconductor active layer 11 is not covered by source electrode 101.
The thin-film transistor that the embodiment of the present invention provides, this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can under the prerequisite that does not affect pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
Further, insulating barrier 12 covers the top of source electrode 101 and semiconductor active layer 11, and is formed with via hole 14 above the G of the central area of semiconductor active layer 11; Drain electrode 102 is electrically connected to semiconductor active layer 11 by the via hole 14 that is positioned at semiconductor active layer 11 central area G.
The raceway groove of a kind of like this TFT of structure as shown in Figure 5, is annular channel, and the width of this raceway groove equals the girth in the cross section of via hole 14, and the length of raceway groove as shown in Figure 4, is the external diameter of via hole 14 distance L to semiconductor active layer 11 central area G peripheries.
A kind of like this TFT of structure, due to its width girth that is semiconductor active layer 11, so the breadth length ratio of this TFT is relatively large, thereby can reduce the source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.In addition, can also be under the prerequisite that does not affect pixel aperture ratio, increase the external diameter of via hole 14 by manufacture craft, perhaps reduce the area of the central area G of semiconductor active layer 11, make the length L of TFT raceway groove reduce, thereby the perimeter of section that perhaps can under the prerequisite that does not affect pixel aperture ratio, increase via hole 14 increases the width of TFT raceway groove, and then the response speed can improve the conducting of TFT raceway groove the time.
Further, this semiconductor active layer 11 can adopt oxide semiconductor material to make.For example: zinc oxide (ZnO), cadmium oxide (CdO), alundum (Al2O3) (Al2O3) or indium gallium zinc oxide (IGZO).The preferred IGZO of the embodiment of the present invention makes semiconductor active layer 11.So, the semiconductor active layer that adopts amorphous silicon (A-Si) to make compared to existing technology, the mobility that adopts the semiconductor active layer of IGZO is tens times of amorphous silicon semiconductor active layer mobility, it has good characteristic of semiconductor, thereby can improve mobility and the performance of TFT.
Further, as shown in Figure 6, this TFT can also comprise the etching barrier layer 15 between source electrode 101 and semiconductor active layer 11.
Wherein, source electrode 101 covers the surrounding of etching barrier layer 15, and etching barrier layer 15 covers the central area G of semiconductor active layer 11.Owing to when making source electrode 101, need to exposing the central area G of semiconductor active layer 11 patterns; therefore; the semiconductor active layer 11 that in the manufacturing process of source electrode 101, can be positioned at central area G by 15 pairs of etching barrier layers is protected, and avoids composition process-induced damage semiconductor active layer 11 in process of manufacture.
In the present invention, composition technique, can refer to comprise photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refer to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.The corresponding composition technique of formed structure choice in can be according to the present invention.
The girth that the width of the raceway groove of a kind of like this TFT of structure is via hole 14 cross sections, and the length of raceway groove as shown in the figure is the external diameter of via hole 14 distance L to etching barrier layer 15 pattern edges.So, the external diameter that can increase via hole 14 by manufacture craft makes the length L of TFT raceway groove reduce, perhaps can under the prerequisite that does not affect pixel aperture ratio, enlarge the area of etching barrier layer 15 so that the length of erosion barrier layer 15 pattern edge one circles increases, can reduce like this source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.
This TFT also comprises the gate insulator 13 between grid 103 and semiconductor active layer 11.So, can guarantee can not be short-circuited because of conduction between the hierarchical structure upper and lower at gate insulator 13.
The embodiment of the present invention a kind of array base palte is provided on the other hand, as shown in Figure 7, comprise: a plurality of pixel cells that are the matrix form arrangement that the grid line 30 intersected by transverse and longitudinal and data wire 31 are split to form, pixel cell comprises pixel electrode 32, also comprises any one TFT as above.Wherein the source electrode 101 of TFT is electrically connected to data wire 31; The drain electrode 102 of TFT is electrically connected to pixel electrode 32.
The identical beneficial effect of TFT because inventive embodiments provides a kind of array base palte to have to provide with previous embodiment of the present invention because TFT has been described in detail in the aforementioned embodiment, repeats no more herein.
The embodiment of the present invention provides array base palte.This array base palte comprises TFT, and this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can under the prerequisite that does not affect pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
Further, the drain electrode 102 of TFT can be structure as a whole with pixel electrode 32.So drain electrode 102 and pixel electrode 32 can be formed simultaneously, thereby the operation of simplification production and processing is enhanced productivity.
The embodiment of the present invention provides a kind of display unit, comprise any one array base palte as above, the identical beneficial effect of array base palte provided with previous embodiment of the present invention is provided, because array base palte has been described in detail in the aforementioned embodiment, repeats no more herein.
In embodiments of the present invention, display unit specifically at least can comprise liquid crystal indicator and organic LED display device, such as this display unit, can be any product or parts with Presentation Function such as liquid crystal display, LCD TV, DPF, mobile phone or panel computer.Wherein, the detailed construction of array base palte has been done detailed description in the aforementioned embodiment, repeats no more herein.
The embodiment of the present invention provides display unit.This display unit comprises the array base palte with TFT, and this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can under the prerequisite that does not affect pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
The embodiment of the present invention provides the manufacture method of a kind of TFT, and as shown in Figure 8, the method comprises:
S101, as shown in Figure 4 makes semiconductor active layer 11 on the substrate that is formed with successively grid 103 and gate insulator 13;
S102, at the substrate surface that is being formed with above-mentioned pattern, make metal level, and form source electrode 101 by composition technique; Wherein, source electrode 101 covers the surrounding of semiconductor active layers 11, and the central area G(that exposes semiconductor active layer 11 is as shown in dotted line frame in Fig. 4).
S103, at the substrate surface that is being formed with above-mentioned pattern, make insulating barrier 12, and form the via hole 14 of insulating barrier 12 at the central area G that is positioned at semiconductor active layer 11 by composition technique.
S104, at the substrate surface that is being formed with above-mentioned pattern, form drain electrode 102,102 covering via holes 14 drain.
It should be noted that, the central area G of semiconductor active layer 11 can refer to the part that semiconductor active layer 11 is not covered by source electrode 101.
The raceway groove of a kind of like this TFT of structure as shown in Figure 5, is annular channel, and the perimeter of section that the width of this raceway groove is via hole 14, and the length of raceway groove as shown in Figure 4 is the external diameter of via hole 14 distance L to semiconductor active layer 11 central area G peripheries.
A kind of like this TFT of structure, due to its width girth that is semiconductor active layer 11, so the breadth length ratio of this TFT is relatively large, thereby can reduce the source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.In addition, can also be under the prerequisite that does not affect pixel aperture ratio, increase the external diameter of via hole 14 by manufacture craft, perhaps reduce the area of the central area G of semiconductor active layer 11, make the length L of TFT raceway groove reduce, thereby or the perimeter of section that can under the prerequisite that does not affect pixel aperture ratio, increase via hole 14 width of TFT raceway groove is increased.The same like this response speed can improve the conducting of TFT raceway groove the time.
The embodiment of the present invention provides the manufacture method of a kind of TFT, and this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can under the prerequisite that does not affect pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
Further, this semiconductor active layer 11 can adopt oxide semiconductor material to make.For example: zinc oxide (ZnO), cadmium oxide (CdO), alundum (Al2O3) (Al2O3) or indium gallium zinc oxide (IGZO).The preferred IGZO of the embodiment of the present invention makes semiconductor active layer 11.So, the semiconductor active layer that adopts amorphous silicon (A-Si) to make compared to existing technology, the mobility that adopts the semiconductor active layer of IGZO is tens times of amorphous silicon semiconductor active layer mobility, it has good characteristic of semiconductor, thereby can improve mobility and the performance of TFT.
Further, before forming source electrode 101, the method also comprises: at the substrate surface that is formed with semiconductor active layer 11, by composition technique, form etching barrier layer 15.
Wherein, source electrode 101 covers the surrounding of etching barrier layer 15, and etching barrier layer 15 covers the central area G of semiconductor active layer 11.Owing to when making source electrode 101, need to exposing the central area G of semiconductor active layer 11 patterns; therefore; the semiconductor active layer 11 that in the manufacturing process of source electrode 101, can be positioned at central area G by 15 pairs of etching barrier layers is protected, and avoids composition process-induced damage semiconductor active layer 11 in process of manufacture.
The perimeter of section that the width of the raceway groove of a kind of like this TFT of structure is via hole 14, and the length of raceway groove as shown in the figure is the external diameter of via hole 14 distance L to etching barrier layer 15 pattern edges.So, the external diameter that can increase via hole 14 by manufacture craft makes the length L of TFT raceway groove reduce, perhaps can under the prerequisite that does not affect pixel aperture ratio, enlarge the area of etching barrier layer 15 so that the length of erosion barrier layer 15 pattern edge one circles increases, can reduce like this source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.
In addition, between the hierarchical structure of this TFT under the gate insulator 13 between grid 103 and semiconductor active layer 11 can guarantee to be located thereon, can not be short-circuited because of conduction.
Below in conjunction with Fig. 6 and Fig. 9, the manufacture process of this array base palte is described in detail.
The method of S201, employing sputter or evaporation prepares one deck gate metal film on the surface of transparency carrier 01, then by mask exposure and etching technics, complete the making of grid 103 patterns.
Wherein, the material for preparing the gate metal film generally includes at least one in molybdenum, aluminium, alumel or copper.
S202, be formed with the substrate surface of above-mentioned pattern, utilizing method deposition gate insulator 13 and the semiconductor active layer 11 of chemical vapour deposition (CVD).Then by mask exposure technique and etching technics, form semiconductor active layer 11 patterns;
Wherein, the material for preparing gate insulator can comprise silica, silicon nitride or silicon oxynitride etc.The material for preparing semiconductor active layer is oxide semiconductor, is preferably IGZO.
S203, at the substrate surface that is formed with above-mentioned pattern, by composition technique, form etching barrier layer 15 patterns.
The material that wherein prepares this etching barrier layer 15 can comprise silica, silicon nitride or silicon oxynitride etc.
S204, at the substrate surface that is formed with above-mentioned pattern by mask exposure technique and etching technics, the semiconductor active layer 11 that need to be connected with source electrode 101 exposes.
S205, at the substrate surface that is formed with above-mentioned pattern, by composition technique, form source electrode 101.
Wherein, source electrode 101 can expose the central area G of these semiconductor active layer 11 patterns.
S206, form the substrate surface of above-mentioned pattern, by mask exposure technique and etching technics, forming data wire 31 patterns, and around the TFT drain electrode 102 of etching barrier layer 15 1 circles, and be electrically connected to the semiconductor active layer 11 extended out.
S207, form the substrate surface of above-mentioned pattern, by a composition technique, forming passivation layer (as the insulating barrier 12 in Fig. 6).
Wherein, the material for preparing this passivation layer can comprise silicon nitride, silica or silicon oxynitride etc.
S208, form the substrate surface of above-mentioned pattern, by a composition technique, on the surface of institute's passivation layer, forming via hole 14.
Wherein, via hole 14 also together etches away etching barrier layer 15, and middle semiconductor layer is exposed.
S209, form the substrate surface of above-mentioned pattern, forming the pattern of pixel electrode 32 by composition technique.
Wherein, pixel electrode 32 is electrically connected to the source electrode 101 of TFT by via hole 14.
Adopt the manufacture method of a kind of like this TFT, this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can under the prerequisite that does not affect pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. a thin-film transistor, is characterized in that, comprises source electrode, drain and gate, and semiconductor active layer;
Described source electrode covers the surrounding of described semiconductor active layer, and described drain electrode is positioned at the central area of described semiconductor active layer, between described source electrode and drain electrode, is provided with insulating barrier.
2. thin-film transistor according to claim 1, is characterized in that, described insulating barrier covers the top of described source electrode and described semiconductor active layer, and be formed with via hole above the central area of described semiconductor active layer; Described drain electrode is electrically connected to described semiconductor active layer by the via hole that is positioned at described semiconductor active layer central area.
3. thin-film transistor according to claim 2, is characterized in that, also comprises the etching barrier layer between described source electrode and described semiconductor active layer;
Wherein, described source electrode covers the surrounding of described etching barrier layer, and described etching barrier layer covers the central area of described semiconductor active layer.
4. according to the described thin-film transistor of any one in claims 1 to 3, it is characterized in that, described semiconductor active layer adopts oxide semiconductor material to make.
5. an array base palte, comprise: a plurality of pixel cells that are the matrix form arrangement that defined by grid line and data wire, described pixel cell comprises pixel electrode, it is characterized in that, also comprise described thin-film transistor as arbitrary as claim 1-4, the source electrode of described thin-film transistor is electrically connected to described data wire; The drain electrode of described thin-film transistor is electrically connected to described pixel electrode.
6. array base palte according to claim 5, is characterized in that, the drain electrode of described thin-film transistor and described pixel electrode are structure as a whole.
7. a display unit, is characterized in that, comprises array base palte as described as claim 5 or 6.
8. the manufacture method of a thin-film transistor, is characterized in that, described method comprises:
Make semiconductor active layer on the substrate that is formed with successively grid and gate insulator;
Make metal level at the substrate surface that is formed with above-mentioned pattern, and form source electrode by composition technique; Wherein, described source electrode covers the surrounding of described semiconductor active layer, and exposes the central area of described semiconductor active layer;
Make insulating barrier at the substrate surface that is formed with above-mentioned pattern, and form the via hole of described insulating barrier by composition technique in the central area that is positioned at described semiconductor active layer;
Form drain electrode at the substrate surface that is formed with above-mentioned pattern, described drain electrode covers described via hole.
9. manufacture method according to claim 8, is characterized in that, described semiconductor active layer adopts oxide semiconductor material to make.
10. manufacture method according to claim 9, is characterized in that, before forming described source electrode, described method also comprises:
Form etching barrier layer at the substrate surface that is formed with described semiconductor active layer by composition technique;
Wherein, described source electrode covers the surrounding of described etching barrier layer, and described etching barrier layer covers the central area of described semiconductor active layer.
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| CN201310456840.4A CN103489921B (en) | 2013-09-29 | 2013-09-29 | A kind of thin-film transistor and manufacture method, array base palte and display unit |
| PCT/CN2013/089020 WO2015043082A1 (en) | 2013-09-29 | 2013-12-10 | Thin-film transistor and manufacturing method therefor, array substrate and display device |
| US14/404,061 US9461066B2 (en) | 2012-08-10 | 2013-12-10 | Thin film transistor and method of manufacturing the same, array substrate and display device |
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| CN201310456840.4A CN103489921B (en) | 2013-09-29 | 2013-09-29 | A kind of thin-film transistor and manufacture method, array base palte and display unit |
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Also Published As
| Publication number | Publication date |
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| WO2015043082A1 (en) | 2015-04-02 |
| CN103489921B (en) | 2016-02-17 |
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