CN203456471U - Thin-film transistor, array substrate and display device - Google Patents
Thin-film transistor, array substrate and display device Download PDFInfo
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- CN203456471U CN203456471U CN201320607504.0U CN201320607504U CN203456471U CN 203456471 U CN203456471 U CN 203456471U CN 201320607504 U CN201320607504 U CN 201320607504U CN 203456471 U CN203456471 U CN 203456471U
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Abstract
An embodiment of the utility model provides a thin-film transistor, an array substrate and a display device, relating to the technical field of displaying. Under the prerequisite of not affecting the pixel aperture ratio, the width to length ratio of a thin-film transistor channel can be increased. The thin-film transistor comprises a source, a drain, a grid, and a semiconductor active layer. The source covers the peripheral of the semiconductor active layer, the drain is located in the center area of the semiconductor active layer, and an insulation layer is arranged between the source and the drain.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of thin-film transistor, array base palte and display unit.
Background technology
TFT-LCD(Thin Film Transistor Liquid Crystal Display, thin film transistor-liquid crystal display) as a kind of panel display apparatus, because it has the features such as little, low in energy consumption, the radiationless and cost of manufacture of volume is relatively low, and be applied to more and more in the middle of high-performance demonstration field.
In TFT-LCD, quality as the thin-film transistor TFT of switch element is particularly important, the general structure of TFT can be as shown in Figure 1, mainly comprise source electrode 101, drain 102 and grid 103, wherein, source electrode 101 conventionally adopts with layer metal material and makes with drain electrode 102, also has semiconductor active layer 11 between source drain region and gate metal layer, and the semiconductor active layer 11 that is arranged in grid 103 tops, region forms shown in TFT raceway groove 10(Fig. 1 dotted line).In prior art, the material of making this semiconductor active layer 11 is amorphous silicon (A-Si).The mobility of a kind of like this TFT of structure is approximately 0.5cm
2/ Vs.Yet, along with display device size becomes greatly gradually, require display device to there is more high-resolution and high-frequency drive performance.Therefore, require TFT to there is high mobility and high-performance.In order to improve the electron mobility of semiconductor active layer, conventionally adopting electron mobility is the conductor oxidate material of tens times of amorphous silicon layer mobilities, as IGZO(Indium Gallium Zinc Oxide, indium gallium zinc oxide), as the semiconductor active layer of TFT.
In prior art, adopt IGZO generally can adopt hole as shown in Figure 2 to hole mode (Hole Type) as the TFT structure of semiconductor active layer 11, wherein the source electrode 101 of TFT and the drain electrode 102 of TFT are electrically connected to IGZO semiconductor active layer 11 by via hole 21 and via hole 22 respectively; Or column mode as shown in Figure 3 (Bar Typer), wherein the source electrode 101 of TFT and the drain electrode of TFT 102 cover the both sides of IGZO semiconductor active layer 11.Yet the breadth length ratio (W:L) of the TFT raceway groove 10 in above-mentioned two kinds of structures is relatively little, therefore the time that the source electrode of TFT and drain electrode need in conducting is longer, so the response speed in the time of can reducing the conducting of TFT raceway groove, thereby the display effect of reduction display unit.
Utility model content
Embodiment of the present utility model provides a kind of thin-film transistor, array base palte and display unit, not affecting under the prerequisite of pixel aperture ratio, can increase the breadth length ratio of thin film transistor channel.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
The one side of the utility model embodiment provides a kind of thin-film transistor, comprises source electrode, drain and gate, and semiconductor active layer;
Described source electrode covers the surrounding of described semiconductor active layer, and described drain electrode is positioned at the central area of described semiconductor active layer, between described source electrode and drain electrode, is provided with insulating barrier.
The utility model embodiment provides a kind of array base palte on the other hand, comprise: a plurality of pixel cells that are matrix form arrangement that defined by grid line and data wire, described pixel cell comprises pixel electrode, also comprise any one thin-film transistor as above, the source electrode of described thin-film transistor is electrically connected to described data wire; The drain electrode of described thin-film transistor is electrically connected to described pixel electrode.
The utility model embodiment provides a kind of display unit on the other hand, comprises any one array base palte as above.
The utility model embodiment provides a kind of thin-film transistor, array base palte and display unit.This thin-film transistor comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can not affect under the prerequisite of pixel aperture ratio, increase the breadth length ratio of thin film transistor channel, thus the response speed while improving thin film transistor channel conducting, the display effect of lifting display unit.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of a kind of TFT that Fig. 1 provides for prior art;
The structural representation of a kind of array base palte that Fig. 2 provides for prior art;
The structural representation of the another kind of array base palte that Fig. 3 provides for prior art;
The structural representation of a kind of TFT that Fig. 4 provides for the utility model embodiment;
A kind of array base palte plan structure schematic diagram that Fig. 5 provides for the utility model embodiment;
The another kind of TFT structural representation that Fig. 6 provides for the utility model embodiment;
The another kind of array base palte plan structure schematic diagram that Fig. 7 provides for the utility model embodiment;
The manufacture method flow chart of a kind of TFT that Fig. 8 provides for the utility model embodiment;
The manufacture method flow chart of the another kind of TFT that Fig. 9 provides for the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model embodiment provides a kind of thin-film transistor TFT, and as shown in Figure 4, comprise source electrode 101, drain 102 and grid 103, and semiconductor active layer 11;
It should be noted that, the central area G of semiconductor active layer 11 can refer to the part that semiconductor active layer 11 is not covered by source electrode 101.
The thin-film transistor that the utility model embodiment provides, this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can not affect under the prerequisite of pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
Further, insulating barrier 12 covers the top of source electrode 101 and semiconductor active layer 11, and is formed with via hole 14 above the G of the central area of semiconductor active layer 11; Drain electrode 102 is electrically connected to semiconductor active layer 11 by being positioned at the via hole 14 of semiconductor active layer 11 central area G.
The raceway groove of a kind of like this TFT of structure as shown in Figure 5, is annular channel, and the width of this raceway groove equals the girth in the cross section of via hole 14, and the length of raceway groove as shown in Figure 4, is the external diameter of via hole 14 distance L to semiconductor active layer 11 central area G peripheries.
A kind of like this TFT of structure, because its width is the girth of semiconductor active layer 11, so the breadth length ratio of this TFT is relatively large, thereby can reduce the source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.In addition, can also not affect under the prerequisite of pixel aperture ratio, by manufacture craft, increase the external diameter of via hole 14, or reduce the area of the central area G of semiconductor active layer 11, the length L of TFT raceway groove is reduced, thereby or the perimeter of section that can increase via hole 14 under the prerequisite that does not affect pixel aperture ratio increases the width of TFT raceway groove, and then the response speed can improve the conducting of TFT raceway groove time.
Further, this semiconductor active layer 11 can adopt oxide semiconductor material to make.For example: zinc oxide (ZnO), cadmium oxide (CdO), alundum (Al2O3) (Al2O3) or indium gallium zinc oxide (IGZO).The preferred IGZO of the utility model embodiment makes semiconductor active layer 11.So, the semiconductor active layer that adopts amorphous silicon (A-Si) to make compared to existing technology, the mobility that adopts the semiconductor active layer of IGZO is tens times of amorphous silicon semiconductor active layer mobility, it has good characteristic of semiconductor, thereby can improve mobility and the performance of TFT.
Further, as shown in Figure 6, this TFT can also comprise the etching barrier layer 15 between source electrode 101 and semiconductor active layer 11.
Wherein, source electrode 101 covers the surrounding of etching barrier layer 15, and etching barrier layer 15 covers the central area G of semiconductor active layer 11.Owing to need to expose the central area G of semiconductor active layer 11 patterns when making source electrode 101; therefore; the semiconductor active layer 11 that can be positioned at central area G by 15 pairs of etching barrier layers in the manufacturing process of source electrode 101 is protected, and avoids composition process-induced damage semiconductor active layer 11 in process of manufacture.
In the utility model, composition technique, can refer to comprise photoetching process, or, comprise photoetching process and etch step, can also comprise printing, ink-jet etc. other are used to form the technique of predetermined pattern simultaneously; Photoetching process, refers to that utilize photoresist, mask plate, the exposure machine etc. of technical processs such as comprising film forming, exposure, development form the technique of figure.Can be according to the corresponding composition technique of formed structure choice in the utility model.
The width of the raceway groove of the TFT of structure is the girth in via hole 14 cross sections like this, and the length of raceway groove as shown in the figure, is the external diameter of via hole 14 distance L to etching barrier layer 15 pattern edges.So, the external diameter that can increase via hole 14 by manufacture craft reduces the length L of TFT raceway groove, or can under the prerequisite that does not affect pixel aperture ratio, expand the area of etching barrier layer 15 so that the length of erosion barrier layer 15 pattern edge one circles increases, can reduce like this source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.
This TFT also comprises the gate insulator 13 between grid 103 and semiconductor active layer 11.So, can guarantee can not be short-circuited because of conduction between the upper and lower hierarchical structure of gate insulator 13.
The utility model embodiment provides a kind of array base palte on the other hand, as shown in Figure 7, comprise: a plurality of pixel cells that are matrix form arrangement that the grid line 30 being intersected by transverse and longitudinal and data wire 31 are split to form, pixel cell comprises pixel electrode 32, also comprises any one TFT as above.Wherein the source electrode 101 of TFT is electrically connected to data wire 31; The drain electrode 102 of TFT is electrically connected to pixel electrode 32.
The identical beneficial effect of TFT because utility model embodiment provides a kind of array base palte to have to provide with the utility model previous embodiment because TFT has been described in detail in the aforementioned embodiment, repeats no more herein.
The utility model embodiment provide array base palte.This array base palte comprises TFT, and this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can not affect under the prerequisite of pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
Further, the drain electrode 102 of TFT can be structure as a whole with pixel electrode 32.So drain electrode 102 and pixel electrode 32 can be formed simultaneously, thereby the operation of simplification production and processing is enhanced productivity.
The utility model embodiment provides a kind of display unit, comprise any one array base palte as above, the identical beneficial effect of array base palte providing with the utility model previous embodiment is provided, because array base palte has been described in detail in the aforementioned embodiment, repeats no more herein.
In the utility model embodiment, display unit specifically at least can comprise liquid crystal indicator and organic LED display device, such as this display unit, can be any product or parts with Presentation Function such as liquid crystal display, LCD TV, DPF, mobile phone or panel computer.Wherein, the detailed structure of array base palte has been done detailed description in the aforementioned embodiment, repeats no more herein.
The utility model embodiment provide display unit.This display unit comprises the array base palte with TFT, and this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can not affect under the prerequisite of pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
The utility model embodiment provides the manufacture method of a kind of TFT, and as shown in Figure 8, the method comprises:
S101, as shown in Figure 4 makes semiconductor active layer 11 on the substrate that is formed with successively grid 103 and gate insulator 13;
S102, at the substrate surface that is being formed with above-mentioned pattern, make metal level, and form source electrode 101 by composition technique; Wherein, source electrode 101 covers the surrounding of semiconductor active layer 11, and the central area G(that exposes semiconductor active layer 11 is as shown in dotted line frame in Fig. 4).
S103, at the substrate surface that is being formed with above-mentioned pattern, make insulating barrier 12, and at the central area G that is positioned at semiconductor active layer 11, form the via hole 14 of insulating barrier 12 by composition technique.
S104, at the substrate surface that is being formed with above-mentioned pattern, form drain electrode 102,102 covering via holes 14 drain.
It should be noted that, the central area G of semiconductor active layer 11 can refer to the part that semiconductor active layer 11 is not covered by source electrode 101.
The raceway groove of a kind of like this TFT of structure as shown in Figure 5, is annular channel, and the width of this raceway groove is the perimeter of section of via hole 14, and the length of raceway groove as shown in Figure 4, is the external diameter of via hole 14 distance L to semiconductor active layer 11 central area G peripheries.
A kind of like this TFT of structure, because its width is the girth of semiconductor active layer 11, so the breadth length ratio of this TFT is relatively large, thereby can reduce the source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.In addition, can also not affect under the prerequisite of pixel aperture ratio, by manufacture craft, increase the external diameter of via hole 14, or reduce the area of the central area G of semiconductor active layer 11, the length L of TFT raceway groove is reduced, thereby or the perimeter of section that can increase via hole 14 under the prerequisite that does not affect pixel aperture ratio the width of TFT raceway groove is increased.The same like this response speed can improve the conducting of TFT raceway groove time.
The utility model embodiment provides the manufacture method of a kind of TFT, and this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can not affect under the prerequisite of pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
Further, this semiconductor active layer 11 can adopt oxide semiconductor material to make.For example: zinc oxide (ZnO), cadmium oxide (CdO), alundum (Al2O3) (Al2O3) or indium gallium zinc oxide (IGZO).The preferred IGZO of the utility model embodiment makes semiconductor active layer 11.So, the semiconductor active layer that adopts amorphous silicon (A-Si) to make compared to existing technology, the mobility that adopts the semiconductor active layer of IGZO is tens times of amorphous silicon semiconductor active layer mobility, it has good characteristic of semiconductor, thereby can improve mobility and the performance of TFT.
Further, before forming source electrode 101, the method also comprises: at the substrate surface that is formed with semiconductor active layer 11, by composition technique, form etching barrier layer 15.
Wherein, source electrode 101 covers the surrounding of etching barrier layer 15, and etching barrier layer 15 covers the central area G of semiconductor active layer 11.Owing to need to expose the central area G of semiconductor active layer 11 patterns when making source electrode 101; therefore; the semiconductor active layer 11 that can be positioned at central area G by 15 pairs of etching barrier layers in the manufacturing process of source electrode 101 is protected, and avoids composition process-induced damage semiconductor active layer 11 in process of manufacture.
The width of the raceway groove of the TFT of structure is a perimeter of section for via hole 14 like this, and the length of raceway groove as shown in the figure, is the external diameter of via hole 14 distance L to etching barrier layer 15 pattern edges.So, the external diameter that can increase via hole 14 by manufacture craft reduces the length L of TFT raceway groove, or can under the prerequisite that does not affect pixel aperture ratio, expand the area of etching barrier layer 15 so that the length of erosion barrier layer 15 pattern edge one circles increases, can reduce like this source electrode 101 of TFT and the time that drain electrode 102 needs in the time of conducting, thus the response speed while improving the conducting of TFT raceway groove.
In addition between the hierarchical structure of this TFT under the gate insulator 13 between grid 103 and semiconductor active layer 11 can guarantee to be located thereon, can not be short-circuited because of conduction.
Below in conjunction with Fig. 6 and Fig. 9, the manufacture process of this array base palte is described in detail.
The method of S201, employing sputter or evaporation is prepared one deck gate metal film on the surface of transparency carrier 01, then by mask exposure and etching technics, complete the making of grid 103 patterns.
Wherein, the material of preparing gate metal film generally includes at least one in molybdenum, aluminium, alumel or copper.
S202, be formed with the substrate surface of above-mentioned pattern, utilizing method deposition gate insulator 13 and the semiconductor active layer 11 of chemical vapour deposition (CVD).Then by mask exposure technique and etching technics, form semiconductor active layer 11 patterns;
Wherein, the material of preparing gate insulator can comprise silica, silicon nitride or silicon oxynitride etc.The material of preparing semiconductor active layer is oxide semiconductor, is preferably IGZO.
S203, at the substrate surface that is formed with above-mentioned pattern, by a composition technique, form etching barrier layer 15 patterns.
The material of wherein preparing this etching barrier layer 15 can comprise silica, silicon nitride or silicon oxynitride etc.
S204, at the substrate surface that is formed with above-mentioned pattern by mask exposure technique and etching technics, the semiconductor active layer 11 that need to be connected with source electrode 101 exposes.
S205, at the substrate surface that is formed with above-mentioned pattern, by a composition technique, form source electrode 101.
Wherein, source electrode 101 can expose the central area G of these semiconductor active layer 11 patterns.
S206, form the substrate surface of above-mentioned pattern, by mask exposure technique and etching technics, forming data wire 31 patterns, and around the TFT drain electrode 102 of etching barrier layer 15 1 circles, and be electrically connected to the semiconductor active layer 11 extending out.
S207, form the substrate surface of above-mentioned pattern, by a composition technique, forming passivation layer (as the insulating barrier 12 in Fig. 6).
Wherein, the material of preparing this passivation layer can comprise silicon nitride, silica or silicon oxynitride etc.
S208, form the substrate surface of above-mentioned pattern, by a composition technique, on the surface of institute's passivation layer, forming via hole 14.
Wherein, via hole 14 also together etches away etching barrier layer 15, and middle semiconductor layer is exposed.
S209, form the substrate surface of above-mentioned pattern, by composition technique, forming the pattern of pixel electrode 32.
Wherein, pixel electrode 32 is electrically connected to the source electrode 101 of TFT by via hole 14.
The manufacture method that adopts a kind of like this TFT, this TFT comprises source electrode, drain and gate, and semiconductor active layer.Wherein source electrode covers the surrounding of semiconductor active layer, and drain electrode is positioned at the central area of semiconductor active layer, between source electrode and drain electrode, is provided with insulating barrier.So, can not affect under the prerequisite of pixel aperture ratio, increase the breadth length ratio of TFT raceway groove, thus the response speed while improving the conducting of TFT raceway groove, the display effect of lifting display unit.
The above; it is only embodiment of the present utility model; but protection range of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement, within all should being encompassed in protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of described claim.
Claims (7)
1. a thin-film transistor, is characterized in that, comprises source electrode, drain and gate, and semiconductor active layer;
Described source electrode covers the surrounding of described semiconductor active layer, and described drain electrode is positioned at the central area of described semiconductor active layer, between described source electrode and drain electrode, is provided with insulating barrier.
2. thin-film transistor according to claim 1, is characterized in that, described insulating barrier covers the top of described source electrode and described semiconductor active layer, and is formed with via hole above the central area of described semiconductor active layer; Described drain electrode is electrically connected to described semiconductor active layer by being positioned at the via hole of described semiconductor active layer central area.
3. thin-film transistor according to claim 2, is characterized in that, also comprises the etching barrier layer between described source electrode and described semiconductor active layer;
Wherein, described source electrode covers the surrounding of described etching barrier layer, and described etching barrier layer covers the central area of described semiconductor active layer.
4. according to the thin-film transistor described in any one in claims 1 to 3, it is characterized in that, described semiconductor active layer adopts oxide semiconductor material to make.
5. an array base palte, comprise: a plurality of pixel cells that are matrix form arrangement that defined by grid line and data wire, described pixel cell comprises pixel electrode, it is characterized in that, also comprise the thin-film transistor as described in as arbitrary in claim 1-4, the source electrode of described thin-film transistor is electrically connected to described data wire; The drain electrode of described thin-film transistor is electrically connected to described pixel electrode.
6. array base palte according to claim 5, is characterized in that, the drain electrode of described thin-film transistor and described pixel electrode are structure as a whole.
7. a display unit, is characterized in that, comprises the array base palte as described in claim 5 or 6.
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| CN201320607504.0U CN203456471U (en) | 2013-09-29 | 2013-09-29 | Thin-film transistor, array substrate and display device |
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| CN201320607504.0U CN203456471U (en) | 2013-09-29 | 2013-09-29 | Thin-film transistor, array substrate and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103489921A (en) * | 2013-09-29 | 2014-01-01 | 合肥京东方光电科技有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| US9461066B2 (en) | 2012-08-10 | 2016-10-04 | Boe Technology Group Co., Ltd. | Thin film transistor and method of manufacturing the same, array substrate and display device |
| CN109300957A (en) * | 2018-09-30 | 2019-02-01 | 京东方科技集团股份有限公司 | A kind of oled substrate and transparent display |
-
2013
- 2013-09-29 CN CN201320607504.0U patent/CN203456471U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9461066B2 (en) | 2012-08-10 | 2016-10-04 | Boe Technology Group Co., Ltd. | Thin film transistor and method of manufacturing the same, array substrate and display device |
| CN103489921A (en) * | 2013-09-29 | 2014-01-01 | 合肥京东方光电科技有限公司 | Thin film transistor, manufacturing method thereof, array substrate and display device |
| WO2015043082A1 (en) * | 2013-09-29 | 2015-04-02 | 合肥京东方光电科技有限公司 | Thin-film transistor and manufacturing method therefor, array substrate and display device |
| CN103489921B (en) * | 2013-09-29 | 2016-02-17 | 合肥京东方光电科技有限公司 | A kind of thin-film transistor and manufacture method, array base palte and display unit |
| CN109300957A (en) * | 2018-09-30 | 2019-02-01 | 京东方科技集团股份有限公司 | A kind of oled substrate and transparent display |
| US11812640B2 (en) | 2018-09-30 | 2023-11-07 | Boe Technology Group Co., Ltd. | Display substrate having a projection of the display layer located within a projection of a light shielding layer, display device and transparent display including the same |
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