CN103488146A - BMK telemetry data switching selection module with channel selection function - Google Patents
BMK telemetry data switching selection module with channel selection function Download PDFInfo
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Abstract
Provided is a BMK telemetry data switching selection module with the channel selection function. The BMK telemetry data switching selection module with the channel selection function comprises an FPGA subunit, a power supply subunit, a channel strobing control address buffering subunit, a BMK telemetry data receiving sub-module, a BMK telemetry data forwarding sub-module, an indicating circuit sub-module and a clock circuit, wherein the power supply subunit is arranged on the upper left portion of the FPGA subunit, the channel strobing control address buffering subunit is arranged on the left side of the FPGA subunit, the BMK telemetry data receiving sub-module is arranged below the FPGA subunit, the BMK telemetry data forwarding sub-module is arranged above the FPGA subunit, the indicating circuit sub-module is arranged on the upper right portion of the FPGA subunit, and the clock circuit is arranged on the right side of the FPGA subunit. According to the BMK telemetry data switching selection module with the channel selection function, the number of BMK telemetry data acquisition cards is greatly reduced when collection is carried out on BMK telemetry data sent by more than one tested product, hardware cost is reduced, the number of bus expansion slots of a test computer system is reduced, and the BMK telemetry data switching selection module with the channel selection function is high in cost performance , and can be conveniently used in an integrated mode.
Description
Technical field
The present invention relates to a kind of BMK telemetry switching with channel selecting function and select module, for a plurality of channel B MK telemetries that for example, send more than 1 cover (: 5 overlap) test product, realize that programmed control multiselect one (for example: 5 select 1) switching distributes the control function, then exports the BMK Telemetry Data Acquisition cartoon road in testing computer system to.Thereby can realize the time-sharing multiplex to an acquisition channel of BMK Telemetry Data Acquisition card, and the telemetry of the BMK more than 1 passage that a plurality of test products are sent is carried out serial acquisition.This structure is very beneficial for improving the testing efficiency of many cover products, significantly reduces the cost of test macro or equipment, economizes on resources, saves space.The invention belongs to compunication, computer-aided test and field of automatic testing.
Background technology
Telemetry is that the close-in measurement value of object parameter is transferred to the technology that remote measuring station is realized telemeasurement, is an integrated technology utilizing sensing technology, the communication technology and data processing technique.Be mainly used in that disperse or the inaccessible measurand of centralized detecting, as remote as the measurand distance, environment of living in is severe, or in high-speed motion state.Utilize remote measurement can realize concentrating monitoring, improve automatization level, raise labour productivity, improve working conditions, improve the scheduling quality.Remote measurement, for scientific research provides a kind of important means of testing, makes originally to be difficult to the research project of being surveyed, and obtains important dynamic property data, at aspects such as national economy, scientific research and military technologies, is used widely.
In contemporary guided missile telemetry measuring technology, telemetry is mainly to carry out data transmission with the BMK type, is called: the BMK telemetry.The BMK telemetry is a typical unidirectional bus structure, is mainly used in connecting a large amount of than low-speed device, is divided into transmit leg and take over party.BMK typical data transfer rate is approximately 1Mbit/s, and the interval of transmitting 1 8bits byte is 1us.The base unit that the BMK data transmit is a 8bits byte.
The BMK telemetry has adopted 8 bit address/data line BMK0～BMK7, adds CS1, CS2, tri-control lines of EN, comes timesharing to realize the transmission of 8 bit address and 16 bit data, and the timing waveform of BMK data output as shown in Figure 11.The maximum 256x3 bytes of BMK data that every frame is continuous, the time interval representative value between frame and frame is 5ms, as shown in Figure 12.
Between signal EN low period, by the various combination of identification signal CS1 and CS2, address, a data high position, data low level are screened.When CS1 is high CS2 when low, the data representation address bit on current bus; When the CS1 signal is low and CS2 signal while being high, the data representation data most-significant byte on current bus; When the CS1 signal be low and the CS2 signal when low, the data representation data least-significant byte on current bus.
So just reached the requirement that 8 bit data address buss transmit 16 bit parallel data.The low effective pulse width representative value of CS1, CS2 is 1us, and EN is low, and the effective pulse width representative value is 0.75us.For improving reliability and the security of data transmission, the BMK telemetry adopts the differential transfer mode, and every 1 road signal is furnished with the 5VCC datum.So the BMK telemetry comprises 11 tunnel address/data/control signals and 11 road accompaniment signals, the signal sum is altogether 22 road signals.
In missile ground test and emulation, the BMK telemetry plays very important effect, and nearly all test result and simulation algorithm are all closely bound up with the BMK telemetry.Particularly in the high low temperature test process of guided missile associated components, wish to take full advantage of the volume of high-low temperature chamber, will overlap product more and put into high-low temperature chamber and tested in batches, in the hope of compression verification time significantly.Now, just need to the BMK telemetry of many covers product be gathered.If adopt the method for configuration polylith Telemetry Data Acquisition card in testing computer system, a large amount of software and hardware resources had both been wasted, be limited to the extended capability of testing computer system simultaneously, the Telemetry Data Acquisition card quantity increased is very limited, can not meet the BMK Telemetry Data Acquisition demand of a large amount of (for example: >=5 overlap) test product.At present, also there is no a kind of module that can realize multichannel BMK telemetry multiselect one switching distribution function.
Module is selected in a kind of BMK telemetry switching with channel selecting function the present invention relates to, and can realize that to the BMK telemetry sent more than 1 test product multiselect one (for example: 5 select 1) switches distribution and controls, and exports BMK Telemetry Data Acquisition card to.Thereby only need configuring a distant BMK survey data collecting card, testing computer system just can realize the serial acquisition function to the BMK telemetry of many covers test product transmission.
Summary of the invention
1, purpose: the object of the present invention is to provide a kind of BMK telemetry switching with channel selecting function to select module, make an acquisition channel of a BMK Telemetry Data Acquisition card in testing computer system, can be under programmed control by the switching of BMK telemetry, select the module acquisition time to receive to send more than 1 test product more than 1 channel B MK telemetry, realize that programmed control multiselect one (for example: 5 select 1) switching to the BMK telemetry distributes to control.
2, technical scheme: module is selected in a kind of BMK telemetry switching with channel selecting function of the present invention, and this module comprises: FPGA subelement, Power supply subelement, passage gating are controlled the address buffer subelement, the BMK telemetry receives submodule, the forwarding of BMK telemetry submodule, indicating circuit submodule and clock circuit.Position annexation between them and concrete signal trend are: centered by the FPGA subelement; The Power supply subelement is positioned at the upper left side of FPGA subelement, and it provides direct supply for FPGA subelement, passage gating are controlled the address buffer subelement, the BMK telemetry receives submodule, BMK telemetry forwarding submodule, indicating circuit submodule and clock circuit; The passage gating is controlled the left side that the address buffer subelement is positioned at the FPGA subelement, for giving the FPGA subelement, provides the passage gating to control address, controls and selects BMK telemetry receiving cable; The BMK telemetry receives submodule and is positioned at FPGA subelement below, for receiving outside BMK telemetry and being transferred to the FPGA subelement; The BMK telemetry forwards submodule and is positioned at FPGA subelement top, for the BMK telemetry that receives the output of FPGA subelement and export to BMK telemetry receiving card; The indicating circuit submodule is positioned at FPGA subelement upper right side, for receiving the signal about pilot lamp of FPGA subelement output; Clock circuit is positioned at FPGA subelement right side, for the FPGA subelement provides necessary clock signal.
Described FPGA subelement is to select Cyclone III Series FPGA---EP3C40F484C8N.This FPGA subelement for example, is realized distributing the control function more than multiselect one switching of a channel B MK telemetry by hardware program language (: Verilog or VHDL), namely realizes the function of a data selector switch.This data selector has more than more than one input channel, and each input channel comprises 11 road signals; This data selection has an output channel, and each output channel comprises 11 road signals.The output channel Zhong 11 road signals of this data selector are controlled by the geocoding of outside input with the corresponding gating of 11 road signal of which input channel.This data selector is only controlled which input channel and output channel gating, any one input channel is not carried out to decoding, decode operation.
Described Power supply subelement is to select two DC/DC power transfer module, is respectively LT1587CM-3.3 and AMS1117-1.5, and direct current+5V is converted to respectively to direct current+3.3V ﹑+1.5V.It is for providing necessary direct current supply to whole module.
It is that the passage gating of outside input is controlled address or manual toggle switch is set to the buffering that the passage gating is controlled address that described passage gating is controlled the address buffer subelement.It receives the passage gating of outside input and controls address, or sets the passage gating by manual toggle switch and control address, and inputs to the FPGA subelement.The buffering of the passage gating of outside input being controlled to address is to utilize chip 74LCX541MTC, and this chip can also increase driving force in addition.Manual toggle switch is set to the passage gating, and to control the buffering of address be mainly that making corresponding address is high level or low level by gauge tap manually.
Described BMK telemetry receives submodule, the optocoupler receiving circuit more than 1 cover, consists of, and wherein opto-coupler chip is selected the HCPL-063L of Agilent company.Every suit optocoupler receiving circuit Jun You 11 road optocoupler receiving circuits, input to the FPGA subelement after one channel B MK telemetry Zhong 22 road signals are converted to 11 road single-ended signals, but do not change the sequential between the address/data/control signal in a channel B MK telemetry.Each road optocoupler receiving circuit one end is connected with channel B MK telemetry Zhong mono-a road accompaniment signal, and the other end is connected with channel B MK telemetry Zhong mono-a tunnel address/data/control signal.Wherein, the output circuit level of every suit optocoupler receiving circuit is LVTTL level or Transistor-Transistor Logic level.Wherein, described every suit optocoupler receiving circuit, when BMK telemetry Zhong mono-tunnel address/data/control signal is high level i.e. " 1 ", the not conducting of optocoupler receiving circuit, what corresponding optocoupler was exported is exactly high level; When BMK telemetry Zhong mono-tunnel address/data/control signal is low level " 0 ", the light emitting diode conducting, what corresponding optocoupler was exported is exactly low level.
Described BMK telemetry forwards submodule and is comprised of the SOIC of TI company packaged chip ULN2803ADW.It is transformed to by 11 road signals of an output channel output of data selector in the FPGA subelement channel B MK telemetry that contains 22 road signals, wherein has 11 road signals to be+5V, then exports to BMK telemetry receiving card.
Described indicating circuit submodule comprises passage pilot lamp group and FPGA test pilot lamp group.It is used to indicate the passage gating and controls address from outside input or toggle switch, and designation data selector switch gating which channel B MK telemetry.To FPGA, test indication is mainly that implementation status to FPGA internal hardware program is judged, according to the demonstration situation of pilot lamp and hardware program, whether the whether consistent determining program of the logic control of pilot lamp is moved to sideslip.
Described clock circuit is to select OSC series crystal oscillator.Its clocking, and input to the FPGA subelement.
3, advantage and effect: module is selected in a kind of BMK telemetry switching with channel selecting function of the present invention, its advantage and effect are: can control function to realizing that more than a channel B MK telemetry program control or manual multiselect one switching distributes, therefore just can realize an acquisition channel time-sharing multiplex of a BMK Telemetry Data Acquisition card, and then can realize the serial acquisition function of the BMK telemetry to sending more than a set of test product.Thereby the quantity of the Telemetry Data Acquisition card in the time of can significantly reducing the BMK Telemetry Data Acquisition sent more than a set of test product, saved hardware cost, saved the bus expansion slot (as: pci bus expansion slot or cpci bus expansion slot) of testing computer system, and cost performance is high, be convenient to integrated use.
The accompanying drawing explanation
The concrete principle assumption diagram of the present invention shown in Fig. 1
The layout of whole PCB design of the present invention shown in Fig. 2
Figure 3 shows that the PCB hierarchical design schematic diagram of the control circuit board in Fig. 2
Figure 4 shows that hardware global design block diagram of the present invention
Figure 5 shows that FPGA subelement configuration module port definition schematic diagram in Fig. 2
Figure 6 shows that in Fig. 4, the BMK telemetry receives the submodule design drawing
Figure 7 shows that in Fig. 4, the BMK telemetry forwards the submodule design drawing
Figure 8 shows that the DB37 gang socket front elevation in Fig. 2
Figure 9 shows that the VHDCI50 gang socket front elevation in Fig. 2
Figure 10 shows that 6U Eurocard board front panel front elevation in Fig. 2
Figure 11 shows that the timing waveform of BMK telemetry
Figure 12 shows that frame and the frame structure sketch schematic diagram of BMK telemetry
In figure, concrete label declaration is as follows:
The some electronic devices and components of 201 control circuit board 202
The gang socket of 203DB37 signal gang socket 204VDHCI50 signal
2056U Eurocard board front panel 401FPGA submodule
402 passage gatings are controlled address buffer subelement 403BMK telemetry and are received submodule
The 404BMK telemetry forwards submodule 405 Power supply subelements
406 indicating circuit submodule 407 clock circuits
The definition of 501FPGA chip JTAG configured port
The definition of 502FPGA chip AS configured port
The fixing pincers of 1001 front panels 1002 attachment screws
Embodiment
See Fig. 1, Fig. 2, Fig. 4, module is selected in a kind of BMK telemetry switching with channel selecting function of the present invention, and this module comprises: FPGA subelement, Power supply subelement, passage gating are controlled the address buffer subelement, the BMK telemetry receives submodule, the forwarding of BMK telemetry submodule, indicating circuit submodule and clock circuit.Position annexation between them is that position annexation and the concrete signal trend between them is: centered by the FPGA subelement; The Power supply subelement is positioned at the upper left side of FPGA subelement, for FPGA subelement, passage gating are controlled the address buffer subelement, the BMK telemetry receives submodule, BMK telemetry forwarding submodule, indicating circuit submodule and clock circuit, provides direct supply; The passage gating is controlled the left side that the address buffer subelement is positioned at the FPGA subelement, for giving the FPGA subelement, provides the passage gating to control address, controls and selects BMK telemetry receiving cable; The BMK telemetry receives submodule and is positioned at FPGA subelement below, for receiving outside BMK telemetry and being transferred to the FPGA subelement; The BMK telemetry forwards submodule and is positioned at FPGA subelement top, for the BMK telemetry that receives the output of FPGA subelement and export to BMK telemetry receiving card; The indicating circuit submodule is positioned at FPGA subelement upper right side, for receiving the signal about pilot lamp of FPGA subelement output; Clock circuit is positioned at FPGA subelement right side, for the FPGA subelement provides necessary clock signal.
Due to a plurality of channel B MK telemetries that the present invention be directed to a plurality of test products transmissions, realize that one switching of programmed control multiselect distributes the control function.But can not do and illustrate in embodiment, therefore with 5, select 1 switching to distribute and control as an example.
See Fig. 2, hardware of the present invention comprises a control circuit board 201, some electronic devices and components 202, a DB37 signal gang socket 203, five VHDCI50 connector bodies 204, a standard 6U Eurocard board front panel 205.
Described control circuit board 201 adopts standard Eurocard physical construction, the 6U external form, and board is of a size of 233.35mm * 160mm, thickness 1.8mm.
See Fig. 3, described control circuit board 201 adopts the making sheet of standard FR-4 material, 4 layers of PCB design, ground floor (L1) is signals layer 1, and the second layer (L2) is stratum, and the 3rd layer (L3) is bus plane, the 4th layer (L4) is signals layer 2, and each flaggy thickness is as shown in table 1 below.
Each laminate thickness of table 1
| Level number | Type | Thickness (mils) |
| L1 | ? | 0.60 |
| ? | Prepreg | 4.00 |
| L2 | ? | 1.20 |
| ? | Central layer | 53.4 |
| L3 | ? | 1.20 |
| ? | Prepreg | 4.00 |
| L4 | ? | 0.60 |
Described some electronic devices and components 202 all are welded on described control circuit board, be divided into 7 unit according to function: the FPGA subelement, the passage gating is controlled the address buffer subelement, the BMK telemetry receives submodule, the BMK telemetry forwards submodule, the Power supply subelement, indicating circuit submodule, clock circuit.
See Fig. 4, described FPGA subelement 401 is selected the high-performance of altera corp, Cyclone III Series FPGA---the EP3C40F484C8N of high performance-price ratio.Use Verilog HDL programming development, realize the selection to the BMK telemetry, this data selector has five input channels, and each input channel comprises 11 road signals; This data selector has an output channel, and each output channel comprises 11 road signals.The output channel Zhong 11 road signals of this data selector are controlled by the geocoding of outside input with the corresponding gating of 11 road signal of which input channel, but this data selector is only controlled which input channel and output channel gating, any one input channel is not carried out to decoding, decode operation.The FPGA configuration module is divided into JTAG and two kinds of patterns of AS.JTAG is the on-line debugging pattern, power on available, but power down information all loses, and JTAG download port pinout as shown in Figure 5; AS is the program Solidification pattern, uses the EEPROM save routine, and the FPGA power down is not lost, and the rear FPGA that powers on can read configurator from EEPROM, and EEPROM selects the EPCS4 chip, and AS download port pinout as shown in Figure 5.
Described passage gating is controlled address buffer subelement 402, and the passage gating that receives outside input is controlled address, or sets the passage gating by manual toggle switch and control address, and inputs to the FPGA subelement.Specifically utilize A0-A2 to control the passage of selecting the BMK telemetry data transmission.Its particular content is as shown in table 2 below.Due to the restriction of field condition, A0-A2 easily produces the interference burr, need come anti-interference by program.
The passage gating of the outside input of table 2 is controlled
| A0 | A1 | A2 | |
| 0 | 0 | 0 | |
| 0 | 0 | 1 | Selector |
| 0 | 1 | 0 | Selector |
| 0 | 1 | 1 | Selector channel 3BMK telemetry |
| 1 | 0 | 0 | Selector |
| 1 | 0 | 1 | Selector |
| 1 | 1 | 0 | Manually automatically switch |
| 1 | 1 | 1 | Reset |
Wherein, when manual control, utilize M0-M2 to realize controlling.Particular content is as shown in table 3 below.
Table 3 manually passage gating is controlled
| M0 | M1 | M2 | |
| 0 | 0 | 1 | Selector |
| 0 | 1 | 0 | Selector |
| 0 | 1 | 1 | Selector |
| 1 | 0 | 0 | Selector |
| 1 | 0 | 1 | Selector channel 5BMK telemetry |
Described BMK telemetry receives submodule 403, by 5 cover optocoupler receiving circuits, formed, every cover optocoupler receiving circuit Jun You 11 road optocoupler receiving circuits, input to the FPGA subelement after one channel B MK telemetry Zhong 22 road signals are converted to 11 road single-ended signals, but do not change the sequential between the address/data/control signal in a channel B MK telemetry.The output circuit level of every suit optocoupler receiving circuit is the LVTTL level.Opto-coupler chip is selected the SO-8 encapsulation opto-coupler chip HCPL-063L of Agilent company.HCPL-063L includes 2 road optocoupler passages, employing+3.3V power supply, and output terminal is the LVTTL level after pull-up resistor, directly enters the pin of FPGA subelement.As shown in Figure 6.
Wherein, described every suit optocoupler receiving circuit, when BMK telemetry Zhong mono-tunnel address/data/control signal is high level i.e. " 1 ", the not conducting of optocoupler receiving circuit, what corresponding optocoupler was exported is exactly high level; When BMK telemetry Zhong mono-tunnel address/data/control signal is low level " 0 ", the light emitting diode conducting, what corresponding optocoupler was exported is exactly low level.
Described BMK telemetry forwards submodule 404, and 11 road signals of an output channel output of data selector in the FPGA subelement are transformed to a channel B MK telemetry that contains 22 road signals, then sends.In fact the BMK telemetry forwards submodule is exactly 11 road OC gate output circuits, and its control signal is from the FPGA subelement.The OC gate output circuit is selected the SOIC of TI company packaged chip ULN2803ADW.Monolithic ULN2803ADW includes 8 road OC doors.Simultaneously, the BMK telemetry forwards submodule and also draws 11 tunnels+5V signal, to realize the output accompaniment signal.As shown in Figure 7.
Wherein, when the FPGA subelement is output as high level, the OC door is output as low level, enters BMK Telemetry Data Acquisition card together with accompaniment signal; When the FPGA subelement is output as low level, the OC door is output as high level, enters BMK Telemetry Data Acquisition card together with accompaniment signal.
Described Power supply subelement 405, select LT1587CM-3.3 and be separately converted to+3.3V of AMS1117-1.5 handle+5V voltage and+1.5V voltage for necessary direct current supply is provided to whole module.Level transferring chip+3.3V all is designed with decoupling capacitor, respectively comprises 1 10uF filter capacitor and 1 0.1uF filter capacitor with+1.5V input and output pin.
Described indicating circuit submodule 406, comprise passage pilot lamp group and FPGA test pilot lamp group.It is used to indicate the passage gating and controls address from outside input or toggle switch, and designation data selector switch gating which channel B MK telemetry.Represent the BMK telemetry of selector channel 1 when LED1 is bright; Represent the BMK telemetry of selector channel 2 when LED2 is bright; Represent the BMK telemetry of selector channel 3 when LED3 is bright; Represent the BMK telemetry of selector channel 4 when LED4 is bright; Represent the BMK telemetry of selector channel 5 when LED5 is bright. be mainly that implementation status to FPGA internal hardware program is judged to FPGA test indication, according to the demonstration situation of pilot lamp and hardware program, whether the whether consistent determining program of the logic control of pilot lamp moved to sideslip.
Described clock circuit 407, for generation of clock signal, and input to the FPGA subelement.Select OSC series crystal oscillator, produce the frequency of 40MHz.
Described DB37 signal gang socket 203, have double 37 pins, is welded on described control circuit board 201 left side edge places, for transmitting the BMK telemetry.The BMK telemetry has 11 signal wires and comprises three parts: enable signal EN, byte judgement signal C1 and C2, and data/address multiplex data line D0-D7.According to C1, what C2 judged the BMK telemetry data transmission is any content, as the free time, and address, the most-significant byte data, the least-significant byte data, now D0-D7 is just corresponding data.BMK telemetry after reception is interconnected by the gang socket of DB37 signal and external unit.DB37 signal gang socket 203 interface definitions are as shown in table 4 below.Figure 8 shows that the DB37 gang socket front elevation in Fig. 2.
Table 4DB socket aperture interface definition
Described five VHDCI50 connector bodies 204, there are double 50 looper pins, be welded on described control circuit board 201 right side edge places, the air plug by the rack back finally interconnects with certain corresponding a set of private adapter respectively mutually respectively, for receiving the BMK telemetry.Therefore five VHDCI50 attachment unit interface definition are identical as shown in table 5 below.Figure 9 shows that the VHDCI50 gang socket front elevation in Fig. 2.
Table 5VHDCI50 socket aperture interface definition
See Figure 10, described 6U Eurocard board front panel 205 meets IEEE1101.1 and IEEE1101.10 standard, front panel 205 with the EMC O-ring seal to reduce electromagnetic interference (EMI).Front panel 205 is fixed on described control circuit panel edges by 2 attachment screws 1002, near described VHDCI50 connector body 204 1 sides, simultaneously by the fixing installation fastness that guarantees of front panel drawing-aid device 1001.Figure 11 shows that the timing waveform of BMK telemetry, Figure 12 shows that frame and the frame structure sketch schematic diagram of BMK telemetry.
Claims (1)
1. module is selected in the BMK telemetry switching with channel selecting function, and it is characterized in that: this module comprises: FPGA subelement, Power supply subelement, passage gating are controlled the address buffer subelement, the BMK telemetry receives submodule, the forwarding of BMK telemetry submodule, indicating circuit submodule and clock circuit; Centered by the FPGA subelement, the Power supply subelement is positioned at the upper left side of FPGA subelement, and it provides direct supply for FPGA subelement, passage gating are controlled the address buffer subelement, the BMK telemetry receives submodule, BMK telemetry forwarding submodule, indicating circuit submodule and clock circuit; The passage gating is controlled the left side that the address buffer subelement is positioned at the FPGA subelement, for giving the FPGA subelement, provides the passage gating to control address, controls and selects BMK telemetry receiving cable; The BMK telemetry receives submodule and is positioned at FPGA subelement below, for receiving outside BMK telemetry and being transferred to the FPGA subelement; The BMK telemetry forwards submodule and is positioned at FPGA subelement top, for the BMK telemetry that receives the output of FPGA subelement and export to BMK telemetry receiving card; The indicating circuit submodule is positioned at FPGA subelement upper right side, for receiving the signal about pilot lamp of FPGA subelement output; Clock circuit is positioned at FPGA subelement right side, for the FPGA subelement provides necessary clock signal;
Described FPGA subelement is to select Cyclone III Series FPGA---EP3C40F484C8N, this FPGA subelement is realized distributing the control function more than multiselect one switching of a channel B MK telemetry by hardware program language, namely realizes the function of a data selector switch; This data selector has more than one input channel, and each input channel comprises 11 road signals; This data selection has an output channel, and each output channel comprises 11 road signals; The output channel Zhong 11 road signals of this data selector are controlled by the geocoding of outside input with the corresponding gating of 11 road signal of which input channel; This data selector is only controlled which input channel and output channel gating, any one input channel is not carried out to decoding, decode operation;
Described Power supply subelement is to select two DC/DC power transfer module, is respectively LT1587CM-3.3 and AMS1117-1.5, and direct current+5V is converted to respectively to direct current+3.3V ﹑+1.5V, and it is for providing necessary direct current supply to whole module;
It is that the passage gating of outside input is controlled address or manual toggle switch is set to the buffering that the passage gating is controlled address that described passage gating is controlled the address buffer subelement; It receives the passage gating of outside input and controls address, or sets the passage gating by manual toggle switch and control address, and inputs to the FPGA subelement; The buffering of the passage gating of outside input being controlled to address is to utilize chip 74LCX541MTC, this chip can also increase driving force in addition, manual toggle switch is set to the passage gating, and to control the buffering of address be mainly that making corresponding address is high level or low level by gauge tap manually;
Described BMK telemetry receives submodule, by the optocoupler receiving circuit more than 1 cover, formed, wherein opto-coupler chip is selected HCPL-063L, every suit optocoupler receiving circuit Jun You 11 road optocoupler receiving circuits, input to the FPGA subelement after one channel B MK telemetry Zhong 22 road signals are converted to 11 road single-ended signals, but do not change the sequential between the address/data/control signal in a channel B MK telemetry; Each road optocoupler receiving circuit one end is connected with channel B MK telemetry Zhong mono-a road accompaniment signal, and the other end is connected with channel B MK telemetry Zhong mono-a tunnel address/data/control signal; Wherein, the output circuit level of every suit optocoupler receiving circuit is LVTTL level or Transistor-Transistor Logic level; Wherein, described every suit optocoupler receiving circuit, when BMK telemetry Zhong mono-tunnel address/data/control signal is high level i.e. " 1 ", the not conducting of optocoupler receiving circuit, what corresponding optocoupler was exported is exactly high level; When BMK telemetry Zhong mono-tunnel address/data/control signal is low level " 0 ", the light emitting diode conducting, what corresponding optocoupler was exported is exactly low level;
Described BMK telemetry forwards submodule and is comprised of SOIC packaged chip ULN2803ADW, it is transformed to by 11 road signals of an output channel output of data selector in the FPGA subelement channel B MK telemetry that contains 22 road signals, wherein there are 11 road signals to be+5V, then export to BMK telemetry receiving card;
Described indicating circuit submodule comprises passage pilot lamp group and FPGA test pilot lamp group; It is used to indicate the passage gating and controls address from outside input or toggle switch, and designation data selector switch gating which channel B MK telemetry, to FPGA, test indication is mainly that implementation status to FPGA internal hardware program is judged, according to the demonstration situation of pilot lamp and hardware program, whether the whether consistent determining program of the logic control of pilot lamp is moved to sideslip;
Described clock circuit is to select OSC series crystal oscillator, its clocking, and input to the FPGA subelement.
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| CN201310435166.1A CN103488146B (en) | 2013-09-23 | 2013-09-23 | A kind of BMK telemetry with channel selecting function switches selects module |
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| CN201310435166.1A CN103488146B (en) | 2013-09-23 | 2013-09-23 | A kind of BMK telemetry with channel selecting function switches selects module |
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| CN103488146B CN103488146B (en) | 2015-11-11 |
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| CN104539281A (en) * | 2014-10-28 | 2015-04-22 | 北京航空航天大学 | Dual-port RAM (Random-Access Memory) reading-writing channel switching and distributing module having program-controlled function |
| CN105300271A (en) * | 2015-10-09 | 2016-02-03 | 天津市英贝特航天科技有限公司 | Multichannel RDC angle measurement CPCI insertion card |
| CN106125582A (en) * | 2016-08-26 | 2016-11-16 | 山东穆柯传感器有限公司 | A kind of controller controlling multiple Press line |
| CN110045270A (en) * | 2019-05-11 | 2019-07-23 | 宁波吉田智能洁具科技有限公司 | Integral type detects encapsulating line |
| CN110955628A (en) * | 2019-11-18 | 2020-04-03 | 上海卫星工程研究所 | Analog quantity telemetering acquisition method and acquisition system based on sampling address |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104539281A (en) * | 2014-10-28 | 2015-04-22 | 北京航空航天大学 | Dual-port RAM (Random-Access Memory) reading-writing channel switching and distributing module having program-controlled function |
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| CN110045270B (en) * | 2019-05-11 | 2024-05-17 | 宁波吉田智能洁具科技有限公司 | Integrated detection glue filling line |
| CN110955628A (en) * | 2019-11-18 | 2020-04-03 | 上海卫星工程研究所 | Analog quantity telemetering acquisition method and acquisition system based on sampling address |
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