CN103457613A - 包括eet反馈的数据处理系统及方法 - Google Patents

包括eet反馈的数据处理系统及方法 Download PDF

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Publication number
CN103457613A
CN103457613A CN2013101059826A CN201310105982A CN103457613A CN 103457613 A CN103457613 A CN 103457613A CN 2013101059826 A CN2013101059826 A CN 2013101059826A CN 201310105982 A CN201310105982 A CN 201310105982A CN 103457613 A CN103457613 A CN 103457613A
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CN
China
Prior art keywords
data
circuit
error count
output
side error
Prior art date
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Pending
Application number
CN2013101059826A
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English (en)
Chinese (zh)
Inventor
张帆
王昌立
韩洋
杨少华
吴学宾
夏海涛
金明
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Avago Technologies International Sales Pte Ltd
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Infineon Technologies North America Corp
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Filing date
Publication date
Application filed by Infineon Technologies North America Corp filed Critical Infineon Technologies North America Corp
Publication of CN103457613A publication Critical patent/CN103457613A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6331—Error control coding in combination with equalisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1128—Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H04L1/005—Iterative decoding, including iteration between signal detection and decoding operation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/067—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Error Detection And Correction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Debugging And Monitoring (AREA)
CN2013101059826A 2012-05-30 2013-03-29 包括eet反馈的数据处理系统及方法 Pending CN103457613A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/483,100 US20130322578A1 (en) 2012-05-30 2012-05-30 Systems and Methods for Data Processing Including EET Feedback
US13/483,100 2012-05-30

Publications (1)

Publication Number Publication Date
CN103457613A true CN103457613A (zh) 2013-12-18

Family

ID=48082849

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2013101059826A Pending CN103457613A (zh) 2012-05-30 2013-03-29 包括eet反馈的数据处理系统及方法

Country Status (6)

Country Link
US (1) US20130322578A1 (enExample)
EP (1) EP2670074A3 (enExample)
JP (1) JP2013251038A (enExample)
KR (1) KR20130135045A (enExample)
CN (1) CN103457613A (enExample)
TW (1) TW201349756A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9378765B2 (en) 2014-04-03 2016-06-28 Seagate Technology Llc Systems and methods for differential message scaling in a decoding process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5912898A (en) * 1997-02-27 1999-06-15 Integrated Device Technology, Inc. Convolutional interleaver/de-interleaver
CN1387323A (zh) * 2001-05-17 2002-12-25 松下电器产业株式会社 纠错装置和纠错方法
US20040228021A1 (en) * 2003-05-15 2004-11-18 Fujitsu Limited Magnetic disk apparatus, read gate optimization method and program
CN101866672A (zh) * 2009-04-17 2010-10-20 Lsi公司 用于预测存储介质故障的系统和方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5912898A (en) * 1997-02-27 1999-06-15 Integrated Device Technology, Inc. Convolutional interleaver/de-interleaver
CN1387323A (zh) * 2001-05-17 2002-12-25 松下电器产业株式会社 纠错装置和纠错方法
US20040228021A1 (en) * 2003-05-15 2004-11-18 Fujitsu Limited Magnetic disk apparatus, read gate optimization method and program
CN101866672A (zh) * 2009-04-17 2010-10-20 Lsi公司 用于预测存储介质故障的系统和方法

Also Published As

Publication number Publication date
TW201349756A (zh) 2013-12-01
US20130322578A1 (en) 2013-12-05
JP2013251038A (ja) 2013-12-12
EP2670074A3 (en) 2014-10-29
KR20130135045A (ko) 2013-12-10
EP2670074A2 (en) 2013-12-04

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Owner name: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) CORPORAT

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES CORP.

Effective date: 20150805

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20150805

Address after: Singapore Singapore

Applicant after: Avago Technologies General IP (Singapore) Pte. Ltd.

Address before: California, USA

Applicant before: LSI Corp.

WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20131218

WD01 Invention patent application deemed withdrawn after publication