CN103441750B - High-low voltage area signal transmission system - Google Patents
High-low voltage area signal transmission system Download PDFInfo
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- CN103441750B CN103441750B CN201310327115.7A CN201310327115A CN103441750B CN 103441750 B CN103441750 B CN 103441750B CN 201310327115 A CN201310327115 A CN 201310327115A CN 103441750 B CN103441750 B CN 103441750B
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Abstract
A kind of high-low voltage area signal transmission system, for reducing the power consumption of height nip signal transmission, including: logic produces circuit, the first time delay produces circuit, the second time delay produces circuit, pulse is adopted along circuit, just nip signal circuit, burr filter circuit, state latching circuit, upper bridge output driving circuit and lower bridge output driving circuit；State latching circuit connects burr filter circuit and upper bridge output driving circuit respectively, and when state latching circuit receives the first high level, state latching circuit controls to open described upper bridge output driving circuit；When receiving the second high level, control to close described upper bridge output driving circuit.Lower bridge output driving circuit, opens according to described second delay control signal and closes.Thus, after above-mentioned high-low voltage area signal transmission system can reduce power consumption, and built-in Dead Time, simplify circuit, improve capacity of resisting disturbance so that just the transmission of nip signal is the most reliable.
Description
Technical field
The present invention relates to height nip signal transmission technology, particularly relate to the height nip letter of a kind of low-power consumption
Number transmission system.
Background technology
In motor-drive circuit, single-chip microcomputer the motor drive signal provided is due to by single-chip microcomputer work electricity
The restriction of pressure, it is impossible to directly drive supply voltage to be up to tens volts or even the field effect transistor of a few hectovolt.Therefore pass
The discrete component drive scheme of system provides a kind of height nip signal transmission technology.It is now widely used for electricity
Machine drives, and especially drives the motor being driven to represent with bladeless fan motor to drive with electric vehicle motor.Example
As, in traditional height nip signal transmission technology, use the direct current of 15V to drive circuitry, Vdc
Powering to field effect transistor, HS is upper bridge MOS switch control signal, and LS is that lower bridge MOS switch controls letter
Number.Diode D2 and filter capacitor C4 is boostrap circuit, provides to the boost-Phase of upper bridge drive circuit
Floating power supply.This circuit design power consumption is big, and drive circuit is easily out of order, and comparison of coherence is poor, drives
The anti-interference of circuit is poor.And the device of discrete device drive circuit is more, take PCB surface long-pending relatively big,
Processing and maintenance complexity.
Summary of the invention
Based on this, it is necessary to provide the high-low voltage area signal transmission system of a kind of low-power consumption, simple in construction.
A kind of high-low voltage area signal transmission system, for reducing the power consumption of height nip signal transmission, including:
Logic produces circuit, is used for generating bridge control signal and lower bridge control signal；
First time delay produces circuit, produces circuit with described logic and is connected, receives described upper bridge control signal also
Described upper bridge control signal is carried out delay process and generates the first delay control signal；
Second time delay produces circuit, produces circuit with described logic and is connected, receives described lower bridge control signal also
Described lower bridge control signal is carried out delay process and generates the second delay control signal；
Pulse is adopted along circuit, is used for receiving described first delay control signal, to described first delays time to control letter
Number gathering rising edge or trailing edge generates burst pulse high level signal；
Just nip signal circuit, is used for receiving described burst pulse high level signal, and by described narrow arteries and veins
Level signal of leaping high carries out processing generation burst pulse low level signal；
Burr filter circuit, for filtering the burr signal in described burst pulse low level signal；Wherein said
Burr filter circuit exports the first high level when receiving the burst pulse low level signal gathering rising edge generation,
Output second high electricity when described burr filter circuit receives the burst pulse low level signal gathering trailing edge generation
Flat；
State latching circuit, connects described burr filter circuit and described upper bridge output driving circuit, and is connecing
When receiving described first high level, signal is opened in output, controls to open described upper bridge output driving circuit, is receiving
Export shutdown signal during described second high level, control to close described upper bridge output driving circuit；And
Lower bridge output driving circuit, opens according to described second delay control signal and closes.
Wherein in an embodiment, described logic produces circuit and includes logic module, described logic module bag
Including two inputs and two outfans, two inputs of described logic module input bridge input letter respectively
Number and lower bridge input signal, two outfans of described logic module export bridge control signal and Xia Qiao respectively
Control signal.
Wherein in an embodiment, described first time delay produces circuit and includes time delay module De1, described time delay
The input of module De1 receives described logic and produces the upper bridge control signal of circuit, described time delay module De1
Outfan adopt along circuit to described pulse for the first delay control signal exported.
Wherein in an embodiment, described second time delay produces circuit and includes time delay module De2, described time delay
The input of module De2 receives described logic and produces the lower bridge control signal of circuit, described time delay module De2
Outfan for the second delay control signal is exported to described lower bridge output driving circuit.
Wherein in an embodiment, described pulse is adopted and is included that pulse is adopted along module Pu1 along circuit, described pulse
Adopt and include input, power input, earth terminal, the first outfan and the second outfan along module Pu1；
Described pulse adopts the input along module Pu1 for receiving described first delay control signal；Described pulse is adopted
Power input along module Pu1 is used for connecing positive source, and the ground connection that described pulse is adopted along module Pu1 terminates
Ground, the first outfan that described pulse is adopted along module Pu1 gathers, for exporting, the burst pulse height that rising edge generates
Level signal, the second outfan that described pulse is adopted along module Pu1 gathers the narrow of trailing edge generation for exporting
Pulse high level signal.
Wherein in an embodiment, described height nip signal circuit includes field effect transistor M46, field
Effect pipe M45, current-limiting resistance R23, current-limiting resistance R24, divider resistance R27, divider resistance R28, two
Pole pipe D16, diode D17, diode D18 and diode D19；
The grid of described field effect transistor M45 gathers, for receiving, the burst pulse high level signal that rising edge generates,
The source electrode of described field effect transistor M45 connects another termination of described current-limiting resistance R24, described current-limiting resistance R24
Ground, the Substrate ground of described field effect transistor M45, the drain electrode of described field effect transistor M45 connects described divider resistance
The VB end of another termination floating power supply of R27, described divider resistance R27, described diode D18 and institute
The two ends of described divider resistance R27, wherein, described diode D18 it are parallel to after stating diode D19 series connection
Negative pole meet the VB end of floating power supply, the positive pole of described diode D19 and described divider resistance R27 and institute
The common port stating field effect transistor M45 connects, described field effect transistor M45, described divider resistance R27 and described
The common port of diode D19 is for exporting the burst pulse low level signal gathering rising edge generation to described hair
Thorn filter circuit；
The grid of described field effect transistor M46 gathers, for receiving, the burst pulse high level signal that trailing edge generates,
The source electrode of described field effect transistor M46 connects another termination of described current-limiting resistance R23, described current-limiting resistance R23
Ground, the Substrate ground of described field effect transistor M46, the drain electrode of described field effect transistor M46 connects described divider resistance
The VB end of another termination floating power supply of R28, described divider resistance R28, described diode D16 and institute
The two ends of described divider resistance R28, wherein, described diode D16 it are parallel to after stating diode D17 series connection
Negative pole meet the VB end of floating power supply, the positive pole of described diode D17 and described divider resistance R28 and institute
The common port stating field effect transistor M46 connects, described field effect transistor M46, described divider resistance R28 and described
The common port of diode D17 is for exporting the burst pulse low level signal gathering trailing edge generation to described hair
Thorn filter circuit.
Wherein in an embodiment, described burr filter circuit includes burr filtration module Pu2, described burr
Filtration module Pu2 includes first input end, the second input, the first outfan, the second outfan and power supply
End；The first input end of described burr filtration module Pu2 is for receiving the narrow arteries and veins that described collection rising edge generates
Rushing low level signal, second input of described burr filtration module Pu2 is used for receiving described collection trailing edge
The burst pulse low level signal generated, described first outfan is for receiving what described collection rising edge generated
Exporting high level during burst pulse low level signal, described second outfan is receiving the generation of described collection trailing edge
Burst pulse low level signal time output high level, the power end of described burr filtration module Pu2 is connected to float
Between VB end and the VS end in galvanic electricity source.
Wherein in an embodiment, described state latching circuit include nor gate NOR1, nor gate NOR2,
Resistance R26, resistance R25 and field effect transistor M43；
The logic input B end of described nor gate NOR1 and the logic input B end of described nor gate NOR2 divide
Yong Yu not receive the first high level and second high level of described burr filter circuit, described nor gate NOR1
The logic input A end of logic output Y end and described nor gate NOR2 be connected, described nor gate NOR1
The logic output Y end of logic input A end and described nor gate NOR2 be connected；Described nor gate NOR1
And the power end of described nor gate NOR2 is all connected between the VB end of floating power supply and VS end；
Described resistance R26 is series at the logic output Y end of described nor gate NOR1 and the VB of floating power supply
Between end, described resistance R25 is series at described nor gate NOR2 logic output Y end and floating power supply
VS end；The grid of described field effect transistor M43 connects the logic output Y end of described nor gate NOR1, described
The source electrode of field effect transistor M43, drain electrode and substrate are all connected with the VB end of floating power supply；
Described nor gate NOR2 logic output Y end, described nor gate NOR1 logic input A end and
The outfan that common port is described state latching circuit of described resistance R25.
Wherein in an embodiment, described upper bridge output driving circuit includes not gate N1, not gate N2, non-
Door N3, not gate N4, not gate N5, not gate N6, field effect transistor M20, field effect transistor M44, field effect
Pipe M48 and electric capacity C2；
Described not gate N1, described not gate N2 and described not gate N3 are series at the output of described state latching circuit
Between end and the grid of described field effect transistor M20；
Described not gate N4, described not gate N5 and described not gate N6 are series at the output of described state latching circuit
Between end and the grid of described field effect transistor M44；The drain electrode of described field effect transistor M20 and described field effect transistor
The drain electrode of M44 connects, and the source electrode of described field effect transistor M20 and substrate connect the VB end of floating power supply, described
The source electrode of field effect transistor M44 and substrate connect the VS end of floating power supply, and described electric capacity C2 is parallel to described field effect
Should be between grid and the source electrode of pipe M48；The grid of described field effect transistor M48 connects described field effect transistor M20
The common port of drain electrode and the drain electrode of described field effect transistor M44, the source electrode of described field effect transistor M48 and substrate
Connecing the VS end of floating power supply, the drain electrode of described field effect transistor M48 meets power supply VH；
Wherein, described field effect transistor M20 is P-channel field-effect transistor (PEFT) pipe, field effect transistor M44 and described field effect
Pipe M48 is N-channel field effect transistor.
Wherein in an embodiment, described lower bridge output driving circuit includes not gate N7, not gate N8, non-
Door N9, not gate N10, not gate N11, not gate N12, field effect transistor M21, field effect transistor M47, field effect
Should pipe M49 and electric capacity C3；
Described not gate N7, described not gate N8 and described not gate N9 are series at described second time delay and produce circuit
Between the grid of outfan and described field effect transistor M21；
Described not gate N10, described not gate N11 and described not gate N12 are series at described second time delay and produce electricity
Between outfan and the grid of described field effect transistor M47 on road；The drain electrode of described field effect transistor M21 is with described
The drain electrode of field effect transistor M47 connects, and the source electrode of described field effect transistor M21 connects the VCC end of power supply, described
The source ground of field effect transistor M47, described electric capacity C3 is parallel to grid and the source of described field effect transistor M49
Between pole；The grid of described field effect transistor M49 connects the drain electrode of described field effect transistor M21 and described field effect transistor
The common port of the drain electrode of M47, the source ground of described field effect transistor M49, the leakage of described field effect transistor M49
Pole output voltage signal VS；
Wherein, described field effect transistor M21 is P-channel field-effect transistor (PEFT) pipe, field effect transistor M47 and described field effect
Pipe M49 is N-channel field effect transistor.
Above-mentioned high-low voltage area signal transmission system produces bridge control signal and lower bridge control on circuit evolving by logic
Signal processed, then by the first time delay produce circuit and the second time delay produce circuit tackle mutually upper bridge control signal and
Lower bridge control signal carries out delay process, such that it is able to arrange the Dead Time of upper and lower bridge.Upper bridge control signal
After time delay successively via pulse adopt along circuit, just nip signal circuit, burr filter circuit,
State latching circuit and upper bridge output control circuit process.Corresponding, adopt in pulse and gather rising edge along circuit
During the burst pulse high level signal generated, just the output of nip transmission circuit gathers the burst pulse that rising edge generates
Burst pulse high level signal be exported to state latching circuit, shape after the filtering of low level signal, burr filter circuit
State latch cicuit receives and exports high level, the output of upper bridge after gathering the burst pulse high level signal that rising edge generates
Drive circuit receives high level conducting output voltage signal VH now.In like manner, adopt along circuit collection in pulse
When trailing edge generates burst pulse high level signal, upper bridge output driving circuit stops voltage output i.e. pass and closes bridge.
And lower bridge output driving circuit directly is controlled to open and close by lower bridge control signal.Thus, above-mentioned high-low pressure
After district's signal transmission system can reduce power consumption, and built-in Dead Time, simplify circuit, improve anti-dry
Disturb ability so that just the transmission of nip signal is the most reliable.
Accompanying drawing explanation
Fig. 1 is the module map of high-low voltage area signal transmission system；
Fig. 2 is the circuit theory diagrams of high-low voltage area signal transmission system；
Fig. 3 is that in an embodiment, the schematic diagram along circuit is adopted in pulse；
Fig. 4 is the schematic diagram of burr filter circuit in an embodiment.
Detailed description of the invention
As it is shown in figure 1, be the module map of high-low voltage area signal transmission system.
A kind of high-low voltage area signal transmission system, for reducing the power consumption of height nip signal transmission, including:
Logic produces circuit 101, is used for generating bridge control signal and lower bridge control signal.
First time delay produces circuit 103, produces circuit 101 with described logic and is connected, and receives described upper bridge and controls
Described upper bridge control signal is also carried out delay process and generates the first delay control signal by signal.
Second time delay produces circuit 105, produces circuit 101 with described logic and is connected, and receives described lower bridge and controls
Described lower bridge control signal is also carried out delay process and generates the second delay control signal by signal.
Pulse is adopted along circuit 107, is used for receiving described first delay control signal, to described first delays time to control
Signals collecting rising edge or trailing edge generate burst pulse high level signal.
Just nip signal circuit 109, is used for receiving described burst pulse high level signal, and by described narrow
Pulse high level signal carries out processing generation burst pulse low level signal.
Burr filter circuit 111, for filtering the burr signal in described burst pulse low level signal；Wherein institute
State output first high electricity when burr filter circuit receives the burst pulse low level signal gathering rising edge generation
Flat, output second when described burr filter circuit receives the burst pulse low level signal gathering trailing edge generation
High level.
State latching circuit 113, connects described burr filter circuit 111 and upper bridge output driving circuit 115,
And signal is opened in output when receiving described first high level, control to open described upper bridge output driving circuit
115, the output shutdown signal when receiving described second high level, control to close described upper bridge output driving circuit
115；And
Lower bridge output driving circuit 117, opens according to described second delay control signal and closes.
Specifically, logic produces circuit 101 and is used for generating bridge control signal and lower bridge control signal, described
Upper bridge control signal is transferred to produce the described first time delay generation circuit that circuit 101 is connected with described logic
103, described lower bridge control signal is transferred to produce the second time delay generation electricity that circuit 101 is connected with described logic
Road 105.
Described upper bridge control signal is carried out delay process generation first and prolongs by described first time delay generation circuit 103
Time control signal, described first delay control signal be transferred to described first time delay produce circuit 103 be connected
Described pulse adopt along circuit 107.
Described lower bridge control signal is carried out delay process generation second and prolongs by described second time delay generation circuit 105
Time control signal, described second delay control signal be transferred to described second time delay produce circuit 105 be connected
Described lower bridge output driving circuit 117；Described lower bridge output driving circuit 117 is according to described second time delay control
Signal processed is opened and is closed.
Described pulse is adopted, along circuit 107, described first delay control signal collection rising edge is generated burst pulse height
Level signal and collection trailing edge generate burst pulse high level signal；Gather the burst pulse height electricity that rising edge generates
The burst pulse high level signal that ordinary mail number and collection trailing edge generate exports to be adopted along circuit 107 to described pulse
The described height nip signal circuit 109 connected.
Described height nip signal circuit 109 to gather rising edge generate burst pulse high level signal and
After the burst pulse high level signal that collection trailing edge generates processes, generate and gather the narrow arteries and veins that rising edge generates
Rush low level signal and gather the burst pulse low level signal that trailing edge generates；Gather the narrow arteries and veins that rising edge generates
Rush low level signal and gather trailing edge generate burst pulse low level signal export to described height nip believe
The described burr filter circuit 111 that number transmission circuit 109 connects.
Described burr filter circuit 111 is for filtering the burst pulse low level signal gathering rising edge generation and adopting
Burr signal in the burst pulse low level signal that collection trailing edge generates；Described burr filter circuit 111 receives
To gather rising edge generate burst pulse low level signal time export the first high level, described burr filter circuit
The second high level is exported when receiving the burst pulse low level signal gathering trailing edge generation.
Described state latching circuit 113 connects described burr filter circuit 111 respectively and the output of described upper bridge drives
Circuit 115, when described state latching circuit 113 receives the first high level, described state latching circuit 113
Signal is opened in outfan output, controls to open described upper bridge output driving circuit 115, described state latching circuit
During 113 reception the second high level, the outfan output shutdown signal of described state latching circuit 113, control to close
Close described upper bridge output driving circuit 115.
Logic produces circuit 101 and is used for generating bridge control signal and lower bridge control signal.Upper bridge control signal
For controlling the open and close of the field effect transistor of upper bridge.Lower bridge control signal is for controlling the field effect of lower bridge
The open and close of pipe.
First time delay produces circuit 103 for upper bridge control signal is carried out delay process.
Second time delay produces circuit 105 for lower bridge control signal is carried out delay process.
After the delay process that the first time delay produces circuit 103 and the second time delay generation circuit 105, it is possible to
Realize built-in Dead Time, simplify the driver of circuit.
The the first delays time to control letter producing circuit 103 output along circuit 107 for gathering the first time delay is adopted in pulse
Number.Corresponding, when gathering the first delay control signal of rising edge, generate rising edge burst pulse high level
Signal.When gathering the first delay control signal of trailing edge, generate trailing edge burst pulse high level signal.
Just nip signal circuit 109 receives and gathers the burst pulse high level signal of rising edge generation and adopt
Collect the burst pulse high level signal that trailing edge generates, and correspondence processes, generate and gather what rising edge generated
The burst pulse low level signal that burst pulse low level signal and collection trailing edge generate.
Pulse adopt along circuit 107 output for rising edge burst pulse high level signal time, just nip signal
Transmission circuit 109 exports field effect transistor and opens signal.Pulse adopt along circuit 107 output narrow for trailing edge
During pulse high level signal, just nip signal circuit 109 exports field effect transistor shutdown signal.
Burr filter circuit 111 is under filtering the burst pulse low level signal gathering rising edge generation and gathering
Fall burr signal along the burst pulse low level signal generated, it is to avoid burr signal is to follow-up state latch
The triggering of circuit 113 impacts.
State latching circuit 113 is for controlling upper bridge output according to the level signal of burr filter circuit 111 output
The output signal of drive circuit 115.Corresponding, when state latching circuit 113 receives the first high level, control
In system, signal is opened in bridge output driving circuit 115 output.When state latching circuit 113 receives the second high level,
In control, bridge output driving circuit 115 exports shutdown signal.
Incorporated by reference to Fig. 2.
Logic produces circuit 101 and includes that logic module L, described logic module L include two inputs and two
Individual outfan, two inputs of described logic module L input bridge input signal HS and the input of lower bridge respectively
Signal LS, two outfans of described logic module L are respectively upper bridge control signal HIN and lower bridge controls letter
Number LIN.
First time delay produces the input termination that circuit 103 includes time delay module De1, described time delay module De1
Receiving described logic and produce the upper bridge control signal of circuit 101, the outfan of described time delay module De1 is used for will
First delay control signal exports to be adopted along circuit 107 to described pulse.
Second time delay produces the input termination that circuit 105 includes time delay module De2, described time delay module De2
Receiving described logic and produce the lower bridge control signal of circuit 101, the outfan of described time delay module De2 is used for will
Second delay control signal exports to described lower bridge output driving circuit 117.
Pulse is adopted and is included that pulse is adopted along module Pu1 along circuit 107, and described pulse is adopted and included input along module Pu1
End, power input, earth terminal, the first outfan and the second outfan；Described pulse is adopted along module Pu1
Input be used for receiving described first delay control signal；The power supply that described pulse is adopted along module Pu1 inputs
End is used for connecing positive source, and the earth terminal ground connection along module Pu1 is adopted in described pulse, and described pulse is adopted along module
First outfan of Pu1 gathers the burst pulse high level signal PGPH that rising edge generates, described arteries and veins for exporting
The second outfan that punching is adopted along module Pu1 gathers, for exporting, the burst pulse high level signal that trailing edge generates
NGPH。
Incorporated by reference to Fig. 3, wherein in an embodiment, inside built-up circuit such as figure along circuit 107 are adopted in pulse
Shown in 3.Pulse is adopted and is included along circuit 107: field effect transistor M22-M42 and field effect transistor M50-M68.?
Effect pipe M22-M42 and field effect transistor M50-M68 use cascade.The function along circuit 107 is adopted in pulse
The rising edge of Gather and input signal I and trailing edge, generate a corresponding burst pulse high level signal respectively, its
The rising edge burst pulse of middle PGPH correspondence input signal, the trailing edge burst pulse of NGPH correspondence input signal.
For the input signal of different duty, pulse is adopted and all can be processed along circuit 107, as long as there being rising edge
Or the input of trailing edge, output will produce the burst pulse high level signal of corresponding rising edge and trailing edge.
Just nip signal circuit 109 includes field effect transistor M46, field effect transistor M45, current-limiting resistance
R23, current-limiting resistance R24, divider resistance R27, divider resistance R28, diode D16, diode D17,
Diode D18 and diode D19.
The grid of described field effect transistor M45 gathers, for receiving, the burst pulse high level signal that rising edge generates,
The source electrode of described field effect transistor M45 connects another termination of described current-limiting resistance R24, described current-limiting resistance R24
Ground, the Substrate ground of described field effect transistor M45, the drain electrode of described field effect transistor M45 connects described divider resistance
The VB end of another termination floating power supply of R27, described divider resistance R27, described diode D18 and institute
The two ends of described divider resistance R27, wherein, described diode D18 it are parallel to after stating diode D19 series connection
Negative pole meet the VB end of floating power supply, the positive pole of described diode D19 and described divider resistance R27 and institute
The common port stating field effect transistor M45 connects, described field effect transistor M45, described divider resistance R27 and described
The common port of diode D19 is for exporting the burst pulse low level signal gathering rising edge generation to described hair
Thorn filter circuit 111.
The grid of described field effect transistor M46 gathers, for receiving, the burst pulse high level signal that trailing edge generates,
The source electrode of described field effect transistor M46 connects another termination of described current-limiting resistance R23, described current-limiting resistance R23
Ground, the Substrate ground of described field effect transistor M46, the drain electrode of described field effect transistor M46 connects described divider resistance
The VB end of another termination floating power supply of R28, described divider resistance R28, described diode D16 and institute
The two ends of described divider resistance R28, wherein, described diode D16 it are parallel to after stating diode D17 series connection
Negative pole meet the VB end of floating power supply, the positive pole of described diode D17 and described divider resistance R28 and institute
The common port stating field effect transistor M46 connects, described field effect transistor M46, described divider resistance R28 and described
The common port of diode D17 is for exporting the burst pulse low level signal gathering trailing edge generation to described hair
Thorn filter circuit 111.
Just the input port of nip signal transmission module 109 meets PGPH and NGPH, and output port exports
PGPL and NGPL.The rising edge burst pulse of PGPH correspondence input signal, for opening upper bridge field effect transistor
Control signal.The trailing edge burst pulse of NGPH correspondence input signal, for closing the control closing bridge field effect transistor
Signal.Resistance R23 and resistance R24 is current-limiting resistance, can also allow field effect transistor M46 and field effect simultaneously
Pipe M45(NLDMOS) drive current curve more smooth with the change of grid voltage.Divider resistance R27
It is used for when corresponding input signal PGPH and NGPH input high level pulse with divider resistance R28,
Field effect transistor M46 and field effect transistor M45(NLDMOS) drain electrode produce a low level pulse respectively.
Due to field effect transistor M46 and field effect transistor M45(NLDMOS) easily produce during opening and closing
Bigger displacement current, has bigger voltage pulsation on divider resistance R27 and divider resistance R28, because of
This respectively between divider resistance R27 and NGPL, increase between divider resistance R28 and PGPL two anti-
To pressure for Zener diode D17 and D18 between 5.4V～7V and D16 and D19, respectively by dividing potential drop electricity
Maximum pressure drop on resistance R27 and divider resistance 28 is limited in 10.8V～14V, it is to avoid subordinate's burr filter circuit
Gate oxide in 111 is breakdown.
Burr filter circuit 111 includes that burr filtration module Pu2, described burr filtration module Pu2 include first
Input, the second input, the first outfan, the second outfan and power end；Described burr filtration module
The first input end of Pu2 is for receiving the burst pulse low level signal that described collection rising edge generates, described burr
Second input of filtration module Pu2 is used for receiving the burst pulse low level signal that described collection trailing edge generates,
Described first outfan is for the output height when receiving the burst pulse low level signal that described collection rising edge generates
Level, described second outfan is output when receiving the burst pulse low level signal that described collection trailing edge generates
High level, the power end of described burr filtration module Pu2 is connected between the VB end of floating power supply and VS end.
Incorporated by reference to Fig. 4.Wherein in an embodiment, the inside of burr filter circuit 111 forms such as Fig. 4 institute
Show.Burr filter circuit 111 includes:
Burr filter circuit 111 is for filtering the burr signal at NLDMOS drain node.When burr filters
When the input I1 of circuit 111 inputs a low level pulse signal, in burr filter circuit 111
Delay circuit, produces a high level pulse through time delay at outfan YN1, and this time delay is low level
The pulsewidth of burr filtering, all can be filtered less than the low level pulse of this time delay.According to actually used
The size of NLDMOS and resistance value may select suitable filtering pulsewidth, can filter NLDMOS drain electrode joint
The low level burr signal produced at Dian.When the input I1 of burr filter circuit 111 inputs a high level
During pulse signal, the delay circuit in burr filter circuit 111, one can be produced at output YN1
Through the low level pulse of time delay, this time delay is more much smaller than little filtering pulsewidth, is formed for circuit design structure
Time delay.In like manner, the corresponding relation between input I2 and outfan YN2 and input I1 and outfan YN1
Corresponding relation the same.
State latching circuit 113 includes nor gate NOR1, nor gate NOR2, resistance R26, resistance R25
And field effect transistor M43.
The logic input B end of described nor gate NOR1 and the logic input B end of described nor gate NOR2 divide
Yong Yu not receive the first high level and second high level of described burr filter circuit, described nor gate NOR1
The logic input A end of logic output Y end and described nor gate NOR2 be connected, described nor gate NOR1
The logic output Y end of logic input A end and described nor gate NOR2 be connected；Described nor gate NOR1
And the power end of described nor gate NOR2 is all connected between the VB end of floating power supply and VS end.
Described resistance R26 is series at the logic output Y end of described nor gate NOR1 and the VB of floating power supply
Between end, described resistance R25 is series at described nor gate NOR2 logic output Y end and floating power supply
VS end；The grid of described field effect transistor M43 connects the logic output Y end of described nor gate NOR1, described
The source electrode of field effect transistor M43, drain electrode and substrate are all connected with the VB end of floating power supply.
Described nor gate NOR2 logic output Y end, described nor gate NOR1 logic input A end and
The outfan that common port is described state latching circuit of described resistance R25.
The operation principle of state latch circuit 113 is: state latch circuit 113 is used for generating latch and opens
Open signal and shutdown signal.After state latch circuit 113 is initialized, outfan VOUT is low level,
When inputing to latch when input YN1 produces a high level pulse, corresponding to upper bridge field effect transistor
Opening signal, output VOUT voltage can be set to high level, and is always maintained at high level state until inputting
End YN2 produces after a high level pulse inputs to state latch circuit 113 and just can redirect as low level；
When inputing to state latch circuit 113 when input YN2 produces a high level pulse, corresponding to upper
The shutdown signal of bridge field effect transistor, output VOUT voltage can be set to low level, and be always maintained at low level shape
State is until input YN1 one high level pulse of generation just can redirect after inputing to state latch circuit 113
High level.
Upper bridge output driving circuit 115 includes not gate N1, not gate N2, not gate N3, not gate N4, not gate
N5, not gate N6, field effect transistor M20, field effect transistor M44, field effect transistor M48 and electric capacity C2.
Described not gate N1, described not gate N2 and described not gate N3 are series at described state latching circuit 113
Outfan and the grid of described field effect transistor M20 between.
Described not gate N4, described not gate N5 and described not gate N6 are series at described state latching circuit 113
Outfan and the grid of described field effect transistor M44 between；The drain electrode of described field effect transistor M20 and described field
The drain electrode of effect pipe M44 connects, and the source electrode of described field effect transistor M20 and substrate connect the VB end of floating power supply,
The source electrode of described field effect transistor M44 and substrate connect the VS end of floating power supply, and described electric capacity C2 is parallel to described
Between grid and the source electrode of field effect transistor M48；The grid of described field effect transistor M48 connects described field effect transistor
The drain electrode of M20 and the common port of the drain electrode of described field effect transistor M44, the source electrode of described field effect transistor M48 and
Substrate connects the VS end of floating power supply, the drain electrode output voltage signal VH of described field effect transistor M48.
Wherein, described field effect transistor M20 is P-channel field-effect transistor (PEFT) pipe, field effect transistor M44 and described field effect
Pipe M48 is N-channel field effect transistor.
Lower bridge output driving circuit 117 includes not gate N7, not gate N8, not gate N9, not gate N10, not gate
N11, not gate N12, field effect transistor M21, field effect transistor M47, field effect transistor M49 and electric capacity C3.
Described not gate N7, described not gate N8 and described not gate N9 are series at described second time delay and produce circuit
Between outfan and the grid of described field effect transistor M21 of 107.
Described not gate N10, described not gate N11 and described not gate N12 are series at described second time delay and produce electricity
Between outfan and the grid of described field effect transistor M47 on road 107；The drain electrode of described field effect transistor M21 with
The drain electrode of described field effect transistor M47 connects, and the source electrode of described field effect transistor M21 connects the VCC end of power supply,
The source ground of described field effect transistor M47, described electric capacity C3 is parallel to the grid of described field effect transistor M49
And between source electrode；The grid of described field effect transistor M49 connects the drain electrode of described field effect transistor M21 and imitates with described field
Should the common port of drain electrode of pipe M47, the source electrode of described field effect transistor M49 and Substrate ground, described field effect
The drain electrode output voltage signal VS of pipe M49.
Wherein, described field effect transistor M21 is P-channel field-effect transistor (PEFT) pipe, field effect transistor M47 and described field effect
Pipe M49 is N-channel field effect transistor.
Based on above-mentioned all embodiments, the operation principle of high-low voltage area signal transmission system is as follows:
Upper bridge input signal HS and lower bridge input signal LS produce circuit 101 by logic and carry out logical process
Bridge control signal HIN and lower bridge control signal LIN in rear generation.Upper bridge control signal HIN and lower bridge control
Signal LIN control respectively correspondence the unlatching of upper bridge field effect transistor, closedown and the unlatching of lower bridge field effect transistor,
Close.
Wherein, upper bridge input signal transmitting procedure is: upper bridge control signal HIN produces electricity through the first time delay
After the delay process on road, generate the first delay control signal HINS with certain time-delay.First delays time to control
Signal HINS generates two paths of signals after extra pulse is adopted and processed along circuit 107: gather the narrow arteries and veins that rising edge produces
The burst pulse high level signal NGPH produced after level signal PGPH of leaping high and collection trailing edge.PGPH pair
Should control the unlatching of upper bridge field effect transistor, NGPH correspondence controls the closedown of upper bridge field effect transistor.PGPH and
NGPH all gives the height nip signal circuit 109 with low-power consumption, with this electricity of burst pulse form control
Field effect transistor M45 and the open and close of M46 in road.
Therefore, although floating power supply supply voltage is the highest, signal is being passed by the height nip signal of low-power consumption
Transmission of electricity road 109 time, its power consumption much smaller than traditional discrete element circuit produced by power consumption, burst pulse pass through
After field effect transistor M45 and M46, the drain electrode of scene effect pipe M45 and M46 produces burst pulse low level signal,
The most corresponding PGPL and NGPL.Then exported to state latching circuit 113 by burr filter circuit 111.
Burr filter circuit 113 is for filtering due to the drain node of scene effect pipe during floating ground quick changes in voltage
The burr signal that place produces, in order to avoid making state latching circuit 113 false triggering.And state latching circuit 113 is used
Signal is opened and closed in latching field effect transistor, and by the State-output of latch to the drive circuit of next stage.
Once be lockable, opening and closing state just need to wait until that contrary state triggers state latching circuit 113, shape
The output of state latch cicuit 113 just can overturn, thus completion logic control signal from low-pressure area to higher-pressure region
Signal is changed.State latching circuit 113 exports the field that can drive upper bridge to upper bridge output driving circuit 115
Effect pipe.
Lower bridge driving principle: lower bridge control signal LIN produces after circuit 105 delay process through the second time delay,
Generate the second delay control signal, be then passed to lower bridge output driving circuit and can drive the field effect transistor of lower bridge.
By arranging Shang Qiao and the delay circuit of lower bridge, bridge field effect transistor and lower bridge field effect transistor can be set
Conducting Dead Time, eliminate Single Chip Microcomputer (SCM) program and be designed the trouble of Dead Time, the program of simplifying sets
Meter.
Wherein, when Dead Time is PWM output, in order to make the upper bridge field effect transistor and lower bridge field effect transistor will not
The protective time slot arranged because switching speed problem simultaneously turns on, when being commonly also referred to pwm response
Between.
Based on above-mentioned all embodiments, the running voltage difference scope between low-pressure area VCC and gnd is
10V～20V, the running voltage difference scope between VB and VS of higher-pressure region is 10～20V, and floating ground is to gnd
Running voltage difference scope be 0V～600V.
Power supply the principle about floating power supply VB-VS: low-pressure area power supply after the conducting of lower bridge field effect transistor
Electric capacity between VB and VS is charged by VCC by forward-biased diode.Voltage can be produced between VB and VS
Difference VCC-Vz(Vz is forward-biased diode pressure drop).After the lower upper bridge signal of bridge unlatching is closed in input, Xia Qiaochang
Effect pipe is closed, and upper bridge field effect transistor is opened.Voltage between VB and VS is held essentially constant, so due to
The rising of VS voltage, the voltage follow VS voltage of VB rises.Finally, the voltage of VB can be arrived by bootstrapping
VH+VCC-Vz, waits until that input pass is closed after bridge opens lower bridge, VS voltage by toward drop-down, VB voltage follow
VS voltage declines, and during upper bridge opens and closes, the capacitance charge amount between VB and VS is consumed
A part, when VB voltage drops to less than VCC-Vz, VCC again can be to electric capacity by forward-biased diode
It is charged, is thus circulated along with the change of input signal.
First delay control signal enters pulse and adopts along circuit 107, and pulse is adopted along circuit 107 Gather and input signal
Rising edge and trailing edge, respectively generate a corresponding burst pulse high level signal, burst pulse high level believe
Number it is input to field effect transistor M45 and the grid of M46 of the height nip signal circuit 109 of low-power consumption,
The drain electrode making field effect transistor M45 and M46 produces low level pulse.Low level pulse is through burr filter circuit
RS state latching circuit 113 is given after 111 filtering.Next stage is given in the output of RS state latching circuit 113
Drive circuit, the unlatching signal of the rising edge burst pulse correspondence field effect transistor wherein latched, the trailing edge of latch
The shutdown signal of burst pulse correspondence field effect transistor, resistance R25, resistance R26 and field effect transistor M43 are state
Latch cicuit 113 initializing circuit.
Above-mentioned high-low voltage area signal transmission system by logic produce circuit 101 generate upper bridge control signal and under
Bridge control signal, is then produced circuit 103 by the first time delay and the second time delay produces in the reply of circuit 105 phase
Bridge control signal and lower bridge control signal carry out delay process, during such that it is able to arrange the dead band of bridge switch
Between.Upper bridge control signal is adopted along circuit 107, just nip signal transmission electricity via pulse after time delay successively
Road 109, burr filter circuit 111, state latching circuit 113 and upper bridge output control circuit 115 process.
Corresponding, when pulse is adopted and is gathered, along circuit 107, the burst pulse high level signal that rising edge generates, high-low pressure
District's transmission circuit 109 output gathers burst pulse low level signal, the burr filter circuit 111 that rising edge generates
Export burst pulse high level signal after filtering to receive gather to state latching circuit 113, state latching circuit 113
Export high level after the burst pulse high level signal that rising edge generates, upper bridge output driving circuit 115 receives this
Time high level conducting output voltage signal VH.In like manner, pulse adopt along circuit 107 gather trailing edge generate
Burst pulse high level signal time, upper bridge output driving circuit stop voltage output i.e. close closes bridge.And lower bridge
Output driving circuit 117 directly is controlled to open and close by lower bridge control signal.Thus, above-mentioned height nip
After signal transmission system can reduce power consumption, and built-in Dead Time, simplify circuit, improve anti-interference
Ability so that just the transmission of nip signal is the most reliable.
Embodiment described above only have expressed the several embodiments of the present invention, and it describes more concrete and detailed,
But therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that, for this area
Those of ordinary skill for, without departing from the inventive concept of the premise, it is also possible to make some deformation and
Improving, these broadly fall into protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be with appended
Claim is as the criterion.
Claims (10)
1. a high-low voltage area signal transmission system, for reducing the power consumption of height nip signal transmission, it is special
Levy and be, including:
Logic produces circuit, is used for generating bridge control signal and lower bridge control signal；
First time delay produces circuit, produces circuit with described logic and is connected, receives described upper bridge control signal also
Described upper bridge control signal is carried out delay process and generates the first delay control signal；
Second time delay produces circuit, produces circuit with described logic and is connected, receives described lower bridge control signal also
Described lower bridge control signal is carried out delay process and generates the second delay control signal；
Pulse is adopted along circuit, is used for receiving described first delay control signal, to described first delays time to control letter
Number gathering rising edge or trailing edge generates burst pulse high level signal；
Just nip signal circuit, is used for receiving described burst pulse high level signal, and by described narrow arteries and veins
Level signal of leaping high carries out processing generation burst pulse low level signal；
Burr filter circuit, for filtering the burr signal in described burst pulse low level signal；Wherein said
Burr filter circuit exports the first high level when receiving the burst pulse low level signal gathering rising edge generation,
Output second high electricity when described burr filter circuit receives the burst pulse low level signal gathering trailing edge generation
Flat；
Upper bridge output driving circuit, controls to open and close according to the signal of state latching circuit output；
State latching circuit, connects described burr filter circuit and described upper bridge output driving circuit, and is connecing
When receiving described first high level, signal is opened in output, controls to open described upper bridge output driving circuit, is receiving
Export shutdown signal during described second high level, control to close described upper bridge output driving circuit；
Lower bridge output driving circuit, controls to open and close according to described second delay control signal.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described logic
Produce circuit include that logic module, described logic module include two inputs and two outfans, described in patrol
Two inputs collecting module input bridge input signal and lower bridge input signal respectively, described logic module
Two outfans export bridge control signal and lower bridge control signal respectively.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described first
Time delay produces circuit and includes that the input of time delay module De1, described time delay module De1 receives described logic and produces
The upper bridge control signal of raw circuit, the outfan of described time delay module De1 is for by the first delay control signal
Output is adopted along circuit to described pulse.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described second
Time delay produces circuit and includes that the input of time delay module De2, described time delay module De2 receives described logic and produces
The lower bridge control signal of raw circuit, the outfan of described time delay module De2 is for by the second delay control signal
Output is to described lower bridge output driving circuit.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described pulse
Adopting and include that pulse is adopted along module Pu1 along circuit, described pulse is adopted and is included that input, power supply input along module Pu1
End, earth terminal, the first outfan and the second outfan；Described pulse adopt along module Pu1 input for
Receive described first delay control signal；Described pulse adopts the power input along module Pu1 for connecing power supply
Positive pole, described pulse adopts the earth terminal ground connection along module Pu1, and it is first defeated that described pulse is adopted along module Pu1
Going out end and gather, for exporting, the burst pulse high level signal that rising edge generates, described pulse is adopted along module Pu1
Second outfan gathers, for exporting, the burst pulse high level signal that trailing edge generates.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described height
Nip signal circuit includes field effect transistor M46, field effect transistor M45, current-limiting resistance R23, current limliting electricity
Resistance R24, divider resistance R27, divider resistance R28, diode D16, diode D17, diode D18
And diode D19；
The grid of described field effect transistor M45 gathers, for receiving, the burst pulse high level signal that rising edge generates,
The source electrode of described field effect transistor M45 connects another termination of described current-limiting resistance R24, described current-limiting resistance R24
Ground, the Substrate ground of described field effect transistor M45, the drain electrode of described field effect transistor M45 connects described divider resistance
The VB end of another termination floating power supply of R27, described divider resistance R27, described diode D18 and institute
The two ends of described divider resistance R27, wherein, described diode D18 it are parallel to after stating diode D19 series connection
Negative pole meet the VB end of floating power supply, the positive pole of described diode D19 and described divider resistance R27 and institute
The common port stating field effect transistor M45 connects, described field effect transistor M45, described divider resistance R27 and described
The common port of diode D19 is for exporting the burst pulse low level signal gathering rising edge generation to described hair
Thorn filter circuit；
The grid of described field effect transistor M46 gathers, for receiving, the burst pulse high level signal that trailing edge generates,
The source electrode of described field effect transistor M46 connects another termination of described current-limiting resistance R23, described current-limiting resistance R23
Ground, the Substrate ground of described field effect transistor M46, the drain electrode of described field effect transistor M46 connects described divider resistance
The VB end of another termination floating power supply of R28, described divider resistance R28, described diode D16 and institute
The two ends of described divider resistance R28, wherein, described diode D16 it are parallel to after stating diode D17 series connection
Negative pole meet the VB end of floating power supply, the positive pole of described diode D17 and described divider resistance R28 and institute
The common port stating field effect transistor M46 connects, described field effect transistor M46, described divider resistance R28 and described
The common port of diode D17 is for exporting the burst pulse low level signal gathering trailing edge generation to described hair
Thorn filter circuit.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described burr
Filter circuit include burr filtration module Pu2, described burr filtration module Pu2 include first input end, second
Input, the first outfan, the second outfan and power end；The first of described burr filtration module Pu2 is defeated
Enter end for receiving the burst pulse low level signal that described collection rising edge generates, described burr filtration module Pu2
The second input for receiving the burst pulse low level signal that described collection trailing edge generates, described first defeated
Go out end output high level when the burst pulse low level signal generated at the described collection rising edge of reception, described
Second outfan is output high level, institute when receiving the burst pulse low level signal that described collection trailing edge generates
The power end stating burr filtration module Pu2 is connected between the VB end of floating power supply and VS end.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described state
Latch cicuit includes nor gate NOR1, nor gate NOR2, resistance R26, resistance R25 and field effect transistor
M43；
The logic input B end of described nor gate NOR1 and the logic input B end of described nor gate NOR2 divide
Yong Yu not receive the first high level and second high level of described burr filter circuit, described nor gate NOR1
The logic input A end of logic output Y end and described nor gate NOR2 be connected, described nor gate NOR1
The logic output Y end of logic input A end and described nor gate NOR2 be connected；Described nor gate NOR1
And the power end of described nor gate NOR2 is all connected between the VB end of floating power supply and VS end；
Described resistance R26 is series at the logic output Y end of described nor gate NOR1 and the VB of floating power supply
Between end, described resistance R25 is series at described nor gate NOR2 logic output Y end and floating power supply
VS end；The grid of described field effect transistor M43 connects the logic output Y end of described nor gate NOR1, described
The source electrode of field effect transistor M43, drain electrode and substrate are all connected with the VB end of floating power supply；
Described nor gate NOR2 logic output Y end, described nor gate NOR1 logic input A end and
The outfan that common port is described state latching circuit of described resistance R25.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that described upper bridge
Output driving circuit include not gate N1, not gate N2, not gate N3, not gate N4, not gate N5, not gate N6,
Field effect transistor M20, field effect transistor M44, field effect transistor M48 and electric capacity C2；
Described not gate N1, described not gate N2 and described not gate N3 are series at the output of described state latching circuit
Between end and the grid of described field effect transistor M20；
Described not gate N4, described not gate N5 and described not gate N6 are series at the output of described state latching circuit
Between end and the grid of described field effect transistor M44；The drain electrode of described field effect transistor M20 and described field effect transistor
The drain electrode of M44 connects, and the source electrode of described field effect transistor M20 connects the VB end of floating power supply, described field effect
The source electrode of pipe M44 connects the VS end of floating power supply, and described electric capacity C2 is parallel to described field effect transistor M48
Between grid and source electrode；The grid of described field effect transistor M48 connects the drain electrode of described field effect transistor M20 with described
The common port of the drain electrode of field effect transistor M44, source electrode and the substrate of described field effect transistor M48 connect floating power supply
VS end, the drain electrode of described field effect transistor M48 meets power supply VH；
Wherein, described field effect transistor M20 is P-channel field-effect transistor (PEFT) pipe, field effect transistor M44 and described field effect
Pipe M48 is N-channel field effect transistor.
High-low voltage area signal transmission system the most according to claim 1, it is characterised in that under described
Bridge output driving circuit includes not gate N7, not gate N8, not gate N9, not gate N10, not gate N11, not gate
N12, field effect transistor M21, field effect transistor M47, field effect transistor M49 and electric capacity C3；
Described not gate N7, described not gate N8 and described not gate N9 are series at described second time delay and produce circuit
Between the grid of outfan and described field effect transistor M21；
Described not gate N10, described not gate N11 and described not gate N12 are series at described second time delay and produce electricity
Between outfan and the grid of described field effect transistor M47 on road；The drain electrode of described field effect transistor M21 is with described
The drain electrode of field effect transistor M47 connects, and the source electrode of described field effect transistor M21 connects the VCC end of power supply, described
The source ground of field effect transistor M47, described electric capacity C3 is parallel to grid and the source of described field effect transistor M49
Between pole；The grid of described field effect transistor M49 connects the drain electrode of described field effect transistor M21 and described field effect transistor
The common port of the drain electrode of M47, the source electrode of described field effect transistor M49 and Substrate ground, described field effect transistor
The drain electrode of M49 connects the VS end of floating power supply；
Wherein, described field effect transistor M21 is P-channel field-effect transistor (PEFT) pipe, field effect transistor M47 and described field effect
Pipe M49 is N-channel field effect transistor.
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| CN109102832B (en) * | 2018-09-12 | 2021-07-06 | 中国电子科技集团公司第五十八研究所 | Negative voltage transmission circuit |
| CN115395482B (en) * | 2022-10-27 | 2023-01-13 | 深圳芯能半导体技术有限公司 | Under-voltage locking circuit and half-bridge switch driving circuit |
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| CN101388548A (en) * | 2008-07-04 | 2009-03-18 | 江西省电力科学研究院 | Dead zone processing method and logic circuit for distribution network electric energy quality regulator |
| CN201656951U (en) * | 2009-03-24 | 2010-11-24 | 深圳市科陆变频器有限公司 | Insulated gate bipolar translator drive circuit |
| CN202059318U (en) * | 2011-04-26 | 2011-11-30 | 刘闯 | Isolated bridge type high-frequency MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) drive circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101388548A (en) * | 2008-07-04 | 2009-03-18 | 江西省电力科学研究院 | Dead zone processing method and logic circuit for distribution network electric energy quality regulator |
| CN201656951U (en) * | 2009-03-24 | 2010-11-24 | 深圳市科陆变频器有限公司 | Insulated gate bipolar translator drive circuit |
| CN202059318U (en) * | 2011-04-26 | 2011-11-30 | 刘闯 | Isolated bridge type high-frequency MOSFET (Metal-Oxide -Semiconductor Field Effect Transistor) drive circuit |
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