CN103441079A - Preparation method of wafer-level high-density wiring - Google Patents
Preparation method of wafer-level high-density wiring Download PDFInfo
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- CN103441079A CN103441079A CN2013104140213A CN201310414021A CN103441079A CN 103441079 A CN103441079 A CN 103441079A CN 2013104140213 A CN2013104140213 A CN 2013104140213A CN 201310414021 A CN201310414021 A CN 201310414021A CN 103441079 A CN103441079 A CN 103441079A
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Abstract
The invention relates to a preparation method of wafer-level high-density wiring, belonging to the technical field of semiconductor packaging. The preparation method comprises the following technological processes: providing a silicon wafer (100), selectively forming an electroplating seed layer I (210) on the surface of the silicon wafer (100), depositing wirings A (220) on the surface of the electroplating seed layer, and reserving intervals between the adjacent wirings A (220); forming dielectric layers (230) on the tops and the side walls of the wirings A (220) and the side wall of the electroplating seed layer I (210); and forming an electroplating seed layer II (310) on the surface of the silicon wafer (100) between the adjacent wirings A (220), and depositing wirings B (330) on the surface of the electroplating seed layer II (310). The preparation method has the advantages that the technology difficulty can be lowered, the bridging problem in a conventional rewiring technology is avoided, and meanwhile, as the wirings A are prepared firstly and then the wirings B are prepared, the wiring configuration with height difference can be formed; and the simple preparation method is simple and practical.
Description
Technical field
The present invention relates to a kind of wafer scale high-density wiring preparation method, belong to the semiconductor packaging field.
Background technology
Along with electronic product, constantly to light, thin, short, little future development, crystal wafer chip dimension encapsulation (WLCSP, Wafer Level Chip Scale Package) more and more receives an acclaim.In wafer-level packaging, adopt again wiring technique again to arrange at crystal column surface to the input/output interface of chip, to facilitate final mounting.Complicated along with the raising of integrated chip density and chip functions, chip area constantly dwindles, and input/output end port constantly increases, and this just makes the wiring density of wiring layer increasing again, and both distance between centers of tracks was more and more less.
Traditional wafer scale main flow process of Wiring technique again is as follows: at first at silicon wafer surface sputter plating seed layer, then form the photoresist opening figure by photoetching method on plating seed layer, finally by electric plating method, in the photoresist opening, deposit contour wiring layer.Along with the increase of wiring density, the photoresist between adjacent two wirings requires very narrow, and this narrow photoresist is not only easily washed away by plating solution when electroplating wiring, and the plating phenomenon easily occurs, thereby cause adjacent wiring bridging short circuit, cause product failure, affect product yield; And contour wiring general layout also makes actual use be restricted.
Summary of the invention
The object of the invention is to overcome the deficiency of above-mentioned technique, propose a kind ofly can to reduce technology difficulty, the bridging problem in Wiring technique, wiring general layout have the wafer scale high-density wiring preparation method of difference in height more effectively to avoid tradition.
the object of the present invention is achieved like this:
A kind of wafer scale high-density wiring preparation method, it comprises following technical process:
Silicon Wafer is provided, and the surface selectivity ground of described Silicon Wafer forms the plating seed layer I, and at the surface deposition wiring A of described plating seed layer I, setting space between adjacent described wiring A;
Form dielectric layer in the top of described wiring A and the sidewall of sidewall and plating seed layer I;
The surface of the Silicon Wafer between adjacent described wiring A forms the plating seed layer II, and in the surface deposition wiring B of described plating seed layer II.
Alternatively, described dielectric layer is formed at the surface of Silicon Wafer and the periphery of wiring A by the method for spraying or spin coating.
Alternatively, the described dielectric layer of the silicon wafer surface between adjacent wire A is removed by the method for photoetching or dry etching.
Alternatively, the surface of the Silicon Wafer between adjacent described wiring A also comprises step before forming the plating seed layer II: described plating seed layer II is formed at the surface of Silicon Wafer and the surface of dielectric layer by the method for sputter or evaporation.
Alternatively, attach photoresist layer in the surface spraying photoresist layer of plating seed layer II or in the surface of the plating seed layer II at wiring A top.
Alternatively, the photoresist layer between adjacent described wiring A is removed by the method for exposure imaging, and forms the photoresist layer opening.
Alternatively, the surface of the plating seed layer II of the photoresist layer opening part between adjacent described wiring A deposits wiring B by electric plating method.
Alternatively, the surface that is opened on the plating seed layer II by the photoresist layer between adjacent described wiring A deposit by electric plating method the B that connects up.
Alternatively, the plating seed layer II of the peripheral inactive area of described wiring A is removed by the method for wet etching or laser ablation.
Alternatively, the plating seed layer II of the peripheral inactive area of described wiring A comprises step before removing by the method for wet etching or laser ablation:
Remove remaining described photoresist layer.
the invention has the beneficial effects as follows:
1,the present invention has the wiring A of larger spacing by preparation, and covers dielectric layer in wiring A is peripheral, then prepares wiring B between adjacent wire A, can obtain highdensity wiring general layout, reduce technology difficulty, avoided the bridging problem in traditional Wiring technique more simultaneously, promoted product yield;
2,the present invention first prepares wiring A, prepares wiring B again, can form the wiring general layout with difference in height, convenient actual the use.
The accompanying drawing explanation
The flow chart that Fig. 1 is a kind of wafer scale high-density wiring of the present invention preparation method.
The schematic diagram of the embodiment mono-that Fig. 2～Figure 10 is a kind of wafer scale high-density wiring of the present invention preparation method.
The schematic diagram of the embodiment bis-that Figure 11～Figure 19 is a kind of wafer scale high-density wiring of the present invention preparation method.
Wherein:
Silicon Wafer 100
Plating seed layer I 210
Wiring A220
Plating seed layer II 310
Photoresist layer opening 321
Wiring B330.
Specific implementation method
Referring to a kind of wafer scale high-density wiring of Fig. 1 the present invention preparation method, its technological process is as follows:
Execution step S101: Silicon Wafer is provided, and the surface selectivity ground of described Silicon Wafer forms the plating seed layer I, and at the surface deposition of the described plating seed layer I A that connects up, setting space between adjacent described wiring A;
Execution step S102: in the top of described wiring A and the sidewall of sidewall and plating seed layer I, form dielectric layer;
Execution step S103: the surface of the Silicon Wafer between adjacent described wiring A forms the plating seed layer II, and in the surface deposition wiring B of described plating seed layer II.
A kind of wafer scale high-density wiring of the present invention preparation method, the technical process of embodiment one is as follows:
As shown in Figure 2, Silicon Wafer 100 is provided, and the method by sputter or evaporation forms plating seed layer I 210 on Silicon Wafer 100, plating seed layer I 210 can be single layer structure, it can be also sandwich construction, form again the wiring A220 on plating seed layer I 210 surfaces by photoetching and electric plating method, the arrangement mode of wiring A220 is determined according to actual needs, setting space between adjacent described wiring A220, this spacing is greater than the width of wiring B330, so that wiring B330 can have enough spaces to make, then remove the plating seed layer I 210 between adjacent wire A220 by the method for wet etching or laser ablation, retain the plating seed layer I 210 between wiring A220 and Silicon Wafer 100,
As shown in Figure 3, spray dielectric layer 230 at the surface of Silicon Wafer 100, top and the sidewall of wiring A220, also can form dielectric layer 230 in the surface of Silicon Wafer 100 and the periphery of wiring A220 by the method for spin coating, (not shown), dielectric layer 230 can be the photosensitive organic material, can be also the inorganic material such as silicon nitride or silicon dioxide;
As shown in Figure 4, remove the dielectric layer 230 on Silicon Wafer 100 surfaces between adjacent wire A220 by the method for photoetching or dry etching, retain wiring A220 top and the dielectric layer 230 of sidewall and the dielectric layer 230 of plating seed layer I 210 sidewalls;
As shown in Figure 5, in the surface of Silicon Wafer 100 surface and dielectric layer 230, by the method formation plating seed layer II 310 of sputter or evaporation, described plating seed layer II 310 can be single layer structure, can be also sandwich construction;
As shown in Figure 6, in the surface spraying photoresist layer 320 of plating seed layer II 310;
As shown in Figure 7, remove the photoresist layer 320 between adjacent wire A220 by the method for exposure imaging, and form photoresist layer opening 321, and the plating seed layer II 310 between adjacent wire A220 is exposed by photoresist layer opening 321;
As shown in Figure 8, the surface deposition of the plating seed layer II 310 at photoresist layer opening 321 places by electric plating method between adjacent wire A220 wiring B330, the height of wiring B330 is determined according to actual needs;
As shown in Figure 9, remove remaining photoresist layer 320;
As shown in figure 10, remove the plating seed layer II 310 of the peripheral inactive area of wiring A220 by the method for wet etching or laser ablation, retain the plating seed layer II 310 between wiring B330 and Silicon Wafer 100.
A kind of wafer scale high-density wiring of the present invention preparation method, the technical process of embodiment bis-is as follows:
As shown in figure 11, Silicon Wafer 100 is provided, and the method by sputter or evaporation forms plating seed layer I 210 on Silicon Wafer 100, plating seed layer I 210 can be single layer structure, it can be also sandwich construction, form again the wiring A220 on plating seed layer I 210 surfaces by photoetching and electric plating method, the arrangement mode of wiring A220 is determined according to actual needs, setting space between adjacent described wiring A220, this spacing is greater than the width of wiring B330, so that wiring B330 can have enough spaces to make, then remove the plating seed layer I 210 between adjacent wire A220 by the method for wet etching or laser ablation, retain the plating seed layer I 210 between wiring A220 and Silicon Wafer 100,
As shown in figure 12, spray dielectric layer 230 at the surface of Silicon Wafer 100, top and the sidewall of wiring A220, also can form dielectric layer 230 in the surface of Silicon Wafer 100 and the periphery of wiring A220 by the method for spin coating, (not shown), dielectric layer 230 can be the photosensitive organic material, can be also the inorganic material such as silicon nitride or silicon dioxide;
As shown in figure 13, remove the dielectric layer 230 on Silicon Wafer 100 surfaces between adjacent wire A220 by the method for photoetching or dry etching, retain wiring A220 top and the dielectric layer 230 of sidewall and the dielectric layer 230 of plating seed layer I 210 sidewalls;
As shown in figure 14, the method in the surface of the surface of Silicon Wafer 100 and dielectric layer 230 by sputter or evaporation forms plating seed layer II 310, and described plating seed layer II 310 can be single layer structure, can be also sandwich construction;
As shown in figure 15, attach the photoresist layer 320 of dry film mode in the surface of the plating seed layer II 310 at wiring A220 top;
As shown in figure 16, by the method for exposure imaging, remove the photoresist layer 320 between adjacent wire A220, form photoresist layer opening 321;
As shown in figure 17, by the photoresist layer opening 321 between adjacent wiring A220, in plating seed layer II 310, by electric plating method, deposit wiring B330, the height of wiring B330 is determined according to actual needs;
As shown in figure 18, remove remaining photoresist layer 320;
As shown in figure 19, remove the plating seed layer II 310 of the peripheral inactive area of wiring A220 by the method for wet etching or laser ablation, retain the plating seed layer II 310 between wiring B330 and Silicon Wafer 100.
In sum, the present invention is by first preparation wiring A220, adjacent wire A220 has larger spacing, be enough to hold wiring B330, and cover dielectric layer 230 in wiring A220 is peripheral, then prepare wiring B330 between adjacent wire A220, thereby obtain highdensity wiring general layout, whole process has been avoided the bridging problem in traditional Wiring technique again, has reduced technology difficulty, has promoted product yield simultaneously.Simultaneously, wiring B330 is later than wiring A220 and makes, and by the control of electroplating technology, the height of the B330 that can make according to actual needs to connect up is different from wiring A220, thereby forms the wiring general layout with difference in height, convenient actual the use.
Claims (10)
1. a wafer scale high-density wiring preparation method, it comprises following technical process:
Silicon Wafer (100) is provided, and the surface selectivity ground of described Silicon Wafer (100) forms plating seed layer I (210), and at the surface deposition wiring A(220 of described plating seed layer I (210)), adjacent described wiring A(220) between setting space;
In described wiring A(220) top and the sidewall of sidewall and plating seed layer I (210) form dielectric layer (230);
The surface of the Silicon Wafer (100) adjacent described wiring A(220) forms plating seed layer II (310), and in the surface deposition wiring B(330 of described plating seed layer II (310)).
2. a kind of wafer scale high-density wiring preparation method as claimed in claim 1, is characterized in that, described dielectric layer (230) is formed at surface and the wiring A(220 of Silicon Wafer (100) by spraying or the method for spin coating) periphery.
3. a kind of wafer scale high-density wiring preparation method as claimed in claim 2, is characterized in that adjacent wire A(220) between the described dielectric layer (230) on Silicon Wafer (100) surface by the method removal of photoetching or dry etching.
4. a kind of wafer scale high-density wiring preparation method as claimed in claim 3, it is characterized in that adjacent described wiring A(220) between the surface of Silicon Wafer (100) form plating seed layer II (310) and also comprise before step: described plating seed layer II (310) is formed at the surface of Silicon Wafer (100) and the surface of dielectric layer (230) by the method for sputter or evaporation.
5. a kind of wafer scale high-density wiring preparation method as claimed in claim 4, it is characterized in that, in the surface spraying photoresist layer (320) of plating seed layer II (310) or in wiring A(220) surface of the plating seed layer II (310) at top attaches photoresist layer (320).
6. a kind of wafer scale high-density wiring preparation method as claimed in claim 5, is characterized in that, adjacent described wiring A(220) between photoresist layer (320) by the method for exposure imaging, remove, and form photoresist layer opening (321).
7. a kind of wafer scale high-density wiring preparation method as claimed in claim 6, it is characterized in that, in adjacent described wiring A(220) between the surface of the plating seed layer II (310) located of photoresist layer opening (321) deposit by electric plating method the B(330 that connects up).
8. a kind of wafer scale high-density wiring preparation method as claimed in claim 6, it is characterized in that, by adjacent described wiring A(220) between photoresist layer opening (321) deposit by electric plating method the B(330 that connects up in the surface of plating seed layer II (310)).
9. a kind of wafer scale high-density wiring preparation method as claimed in claim 7 or 8, is characterized in that, described wiring A(220) the plating seed layer II (310) of peripheral inactive area removes by the method for wet etching or laser ablation.
10. a kind of wafer scale high-density wiring preparation method as claimed in claim 9, is characterized in that, described wiring A(220) the plating seed layer II (310) of peripheral inactive area comprises step before removing by the method for wet etching or laser ablation:
Remove remaining described photoresist layer (320).
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| CN201310414021.3A CN103441079B (en) | 2013-09-12 | 2013-09-12 | Wafer-level high-density wiring preparation method |
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| CN201310414021.3A CN103441079B (en) | 2013-09-12 | 2013-09-12 | Wafer-level high-density wiring preparation method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007235144A (en) * | 2007-03-09 | 2007-09-13 | Fujitsu Ltd | Method for forming pattern |
| CN101360849A (en) * | 2005-11-18 | 2009-02-04 | 莱里斯奥鲁斯技术公司 | Method for forming multi-layer structure |
| CN101431864A (en) * | 2007-11-06 | 2009-05-13 | 日本梅克特隆株式会社 | Method for manufacturing printed wiring board with raised pad |
| CN101981655A (en) * | 2008-06-30 | 2011-02-23 | 英特尔公司 | Methods for fabricating line/space routing between C4 pads |
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2013
- 2013-09-12 CN CN201310414021.3A patent/CN103441079B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101360849A (en) * | 2005-11-18 | 2009-02-04 | 莱里斯奥鲁斯技术公司 | Method for forming multi-layer structure |
| JP2007235144A (en) * | 2007-03-09 | 2007-09-13 | Fujitsu Ltd | Method for forming pattern |
| CN101431864A (en) * | 2007-11-06 | 2009-05-13 | 日本梅克特隆株式会社 | Method for manufacturing printed wiring board with raised pad |
| CN101981655A (en) * | 2008-06-30 | 2011-02-23 | 英特尔公司 | Methods for fabricating line/space routing between C4 pads |
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