CN102446805A - Method for reducing particle defects at edges of wafers - Google Patents
Method for reducing particle defects at edges of wafers Download PDFInfo
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- CN102446805A CN102446805A CN2010105070144A CN201010507014A CN102446805A CN 102446805 A CN102446805 A CN 102446805A CN 2010105070144 A CN2010105070144 A CN 2010105070144A CN 201010507014 A CN201010507014 A CN 201010507014A CN 102446805 A CN102446805 A CN 102446805A
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- photoresistance glue
- topcoating
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Abstract
The invention provides a method for reducing particle defects at edges of wafers; the method comprises the following steps of: sequentially coating hexamethyl disilazane (HMDS), a bottom anti-reflective layer, a first photoresist adhesive layer and a top coating on the surface of a semiconductor substrate, wherein the HMDS, the bottom anti-reflective layer, the first photoresist adhesive layer and the top coating are also adhered in the thickness direction of the edges of the wafers; carrying out immersed photoetching on the top coating and the first photoresist adhesive layer, and by using a pattern formed after immersed photoetching as a masking film, etching the semiconductor substrate to form a shallow trench isolation area; filling the shallow trench isolation area with oxide, and then depositing a grid oxidation layer material on the surface of the semiconductor substrate; coating a second photoresist adhesive layer on the surface of the grid oxidation layer material; and etching the second photoresist adhesive layer, and by using a pattern formed after photoetching as a masking film, carrying out wet process etching on the grid oxidation layer material to form the grid oxidation layer. By adopting the method, defects that oxide particles occur at the edges of the wafers can be effectively reduced.
Description
Technical field
The present invention relates to semiconductor device processing technology, particularly a kind of method that reduces the Waffer edge grain defect.
Background technology
In the FEOL that semiconductor device is made, comprise that shallow trench isolation leaves the formation of the formation of the making of (STI), gate oxide, polysilicon gate and the multiple working procedures such as formation of contact hole (CT).Along with development of semiconductor; The speed of service of semiconductor device is more and more faster; The integrated level of chip circuit is increasingly high, thereby makes the various features dimensional parameters of semiconductor device diminish gradually, for 65 nanometers or more high-precision technology generation; Distinguishable device size is more little good more during photoetching, i.e. the resolution of photoetching is high more good more.Wherein, for improving resolution, adopt the method for liquid immersion lithography of new generation, patterning photoresistance glue-line.The method of said liquid immersion lithography refers to water as medium, in water, carries out photoetching.For example, in the manufacturing process of, polysilicon gate and contact hole, all can use liquid immersion lithography at shallow trench isolation.Need explain that the making of gate oxide is not strict especially to dimensional requirement in the prior art, so still adopt common photoetching method in this process, promptly is the photoetching method of medium with the air.
The structural representation of Waffer edge was as shown in Figure 1 when prior art was carried out liquid immersion lithography.Be formed with bottom anti-reflection layer (BARC) 101, first photoresistance glue-line (PR) 102 and Topcoating (Topcoat) 103 on the Semiconductor substrate 100 successively.Wherein, Topcoating 103 covers the first photoresistance glue-line 102 fully, and drops on the bottom anti-reflection layer 101.As can be seen from the figure; The first photoresistance glue-line 102 all is to remove (EBR) through flange with bottom anti-reflection layer 101; That is to say bottom anti-reflection layer 101 and the first photoresistance glue-line 102 after coating; Adopt coordinative solvent to remove the part on its Waffer edge respectively, make to have certain width separately apart from wafer boundary.Bottom anti-reflection layer 101 is apart from 0.7 millimeter of wafer boundary behind the process EBR among this embodiment, and the first photoresistance glue-line 102 is apart from 2.3 millimeters of wafer boundaries.If bottom anti-reflection layer 101 is not carried out EBR, then after EBR when dry, the bottom anti-reflection layer on the Waffer edge will be peeled off the generation grain defect easily.Photoresistance glue is oily matter; Can not contact well with the aqueous medium of immersion lithography, if photoresistance glue directly contacts with aqueous medium, wafer moves in water during exposure; Be easy to take the various particles of Waffer edge to the wafer middle section; Wafer middle section position generally is furnished with each device layer, if be stained with particle at the key position of its device layer, is easy to cause the inefficacy of device.So the first photoresistance glue-line 102 needs Topcoating 103 and covers; Topcoating 103 is and the kin organic matter layer of bottom anti-reflection layer; Not only have good hydrophily, and both can contact well, also can contact well with bottom anti-reflection layer with the photoresistance glue-line.The first photoresistance glue-line 102 just need carry out EBR for being covered by Topcoating 103 fully after being coated with, among this embodiment the first photoresistance glue-line 102 is carried out after the EBR, and the first photoresistance glue-line 102 is apart from 2.3 millimeters of wafer boundaries.Equally, occur and bottom anti-reflection layer 101 similar grain defects at Waffer edge for preventing Topcoating 103, Topcoating 103 also need carry out EBR after coating, and Topcoating 103 is apart from 1.4 millimeters of wafer boundaries in the present embodiment.
After the coating according to above-mentioned each layer; Need carry out liquid immersion lithography to the Topcoating 103 and the first photoresistance glue-line 102; With the pattern behind the said liquid immersion lithography is that mask carries out after the etching of Semiconductor substrate 100; Form shallow channel isolation area, fill oxide 201 in the shallow channel isolation area of etching then.Wherein, The Topcoating 103 and the first photoresistance glue-line 102 can manifest bottom anti-reflection layer 101 then simultaneously by photoetching, and bottom anti-reflection layer 101 needs wet method to remove; Because this step is a prior art; For describing for simplicity,, this step directly is classified as in the photoetching process so omitted the description that bottom anti-reflection layer needs wet method to remove.Owing on surface, do not have the photoresistance glue-line apart from 2.3 millimeters of wafer boundaries; On surface, there is not bottom anti-reflection layer apart from 0.7 millimeter of wafer boundary; So during the etching shallow channel isolation area; Substrate to Waffer edge stops that degree is different; Therefore can rugged step be occurred by in various degree etching in the scope of 2.3 millimeters of Waffer edges, then in the shallow channel isolation area of etching during fill oxide, also can in the scope of 2.3 millimeters of Waffer edges, deposit oxide and rugged step 202 correspondingly occurs.As shown in Figure 2, Fig. 2 is prior art Waffer edge occur being uneven sketch map of step after the fill oxide in shallow channel isolation area.
Then, form gate oxide on Semiconductor substrate 100 surfaces, concrete steps are:
Deposition gate oxide material; Be coated with the second photoresistance glue-line at the gate oxide material surface; The second photoresistance glue-line to Waffer edge carries out EBR, in the present embodiment the second photoresistance glue-line of gate oxide material surface after EBR apart from 1 millimeter of wafer boundary; Carry out photoetching and be that mask carries out forming gate oxide 203 after the wet etching of gate oxide material through the second photoresistance glue-line after the EBR said with the pattern after the said photoetching.Because when the gate oxide material is carried out wet etching; There is not the protection of photoresistance glue-line on the surface that Waffer edge is 1 millimeter; And the oxide components of filling in the preceding with it groove of gate oxide material is identical, so in the position that does not have the protection of photoresistance glue, the sulfuric acid that wet etching adopted is understood the intact gate oxide material of etching very soon; Then the oxide with shoulder height is carried out etching, the depression that is produced is as shown in Figure 3.The more important thing is; Subsiding in this etching process along with shoulder height; The oxide of not removed by the sulfuric acid etching can produce the grain defect of oxide residue; Problems such as this grain defect will cause the polysilicon gate broken string in the process that follow-up polysilicon gate and CT form, perhaps CT is blocked.
Need to prove; Each road technology is all followed certain uniform rules when accomplishing; That is to say if the photoresistance glue-line has carried out EBR in the making that shallow trench isolation leaves; So general in the making of subsequent gate oxide layer the photoresistance glue-line also need carry out EBR, so when above-mentioned gate oxide forms, need carry out EBR to the second photoresistance glue-line.
Summary of the invention
In view of this, the technical problem of the present invention's solution is: how when forming gate oxide, to prevent that the oxide particle defective from appearring in Waffer edge.
For solving the problems of the technologies described above, technical scheme of the present invention specifically is achieved in that
The invention discloses a kind of method that reduces the Waffer edge grain defect, be applied in the leading portion manufacturing process of semiconductor device, this method comprises:
On semiconductor substrate surface, be coated with HMDS HMDS, bottom anti-reflection layer, first photoresistance glue-line and the Topcoating successively; Wherein, HMDS, bottom anti-reflection layer, the first photoresistance glue-line and Topcoating also are attached on the thickness direction of Waffer edge;
The Topcoating and the first photoresistance glue-line are carried out liquid immersion lithography, and be that mask carries out after the etching of Semiconductor substrate, form shallow channel isolation area with the first photoresistance glue-line pattern behind the said liquid immersion lithography;
In shallow channel isolation area, after the fill oxide, deposit the gate oxide material at semiconductor substrate surface;
Be coated with the second photoresistance glue-line at the gate oxide material surface;
The said second photoresistance glue-line is carried out photoetching, and be that mask carries out after the wet etching of gate oxide material, form gate oxide with the second photoresistance glue-line pattern after the said photoetching.
After the coating Topcoating, Topcoating and the first photoresistance glue-line to be carried out before the liquid immersion lithography, this method further comprises: the HMDS on the thickness direction of Waffer edge, bottom anti-reflection layer, the first photoresistance glue-line and Topcoating are cleaned.
Plasma water or propyleneglycoles ether acetate PGMEA or ethylene glycol monomethyl amine ether acetate EGMEA are adopted in said cleaning.
Visible by above-mentioned technical scheme; The present invention is in the process that the formation shallow trench isolation leaves; At first be coated with HMDS (HMDS) at semiconductor substrate surface during liquid immersion lithography with stickiness; Be coated with bottom anti-reflection layer, photoresistance glue-line and Topcoating then successively, and these coatings are owing to have the existence of the HMDS of stickiness, can thickness direction attached to Waffer edge on.The present invention does not carry out EBR to above-mentioned coating, so Waffer edge has had the protection of above-mentioned coating, rugged step can not occur.Next; When forming gate oxide; Photoresistance glue-line in gate oxide material surface coating need not carry out EBR yet, and Waffer edge is covered by the photoresistance glue-line fully, so the gate oxide material is carried out wet etching when forming gate oxide; Waffer edge just can not etched into by the sulfuric acid that wet etching adopted, and just the oxide particle defective can not occur yet.Therefore, follow-up in the process that polysilicon gate and CT form, just can there be grain defect, cause the polysilicon gate broken string, problem such as perhaps CT is blocked.
Description of drawings
The structural representation of Waffer edge when Fig. 1 carries out liquid immersion lithography for prior art.
Fig. 2 is prior art Waffer edge occur being uneven sketch map of step after the fill oxide in shallow channel isolation area.
Fig. 3 forms the gate oxide sketch map of the step place appearance depression of Waffer edge afterwards for prior art.
Fig. 4 reduces the schematic flow sheet of the method for Waffer edge grain defect for the present invention.
The structural representation of Waffer edge when Fig. 4 a carries out liquid immersion lithography for the present invention.
Fig. 4 b forms the gate oxide sketch map of Waffer edge afterwards for adopting method of the present invention.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
The present invention utilizes sketch map to describe in detail; When the embodiment of the invention was detailed, for the ease of explanation, the sketch map of expression structure can be disobeyed general ratio and done local the amplification; Should be with this as to qualification of the present invention; In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
For comparing with method of the present invention, comprise shallow trench isolation leave with the prior art of gate oxide forming process in summary, may further comprise the steps:
Step 11, carrying out EBR after the bottom anti-reflection layer in coating on the semiconductor substrate surface; Carrying out EBR behind the coating first photoresistance glue-line on the bottom anti-reflective laminar surface; Carrying out EBR behind the coating Topcoating on the first photoresistance glue-line surface;
Step 12, Topcoating and the first photoresistance glue-line are carried out liquid immersion lithography and be that mask carries out forming shallow channel isolation area after the etching of Semiconductor substrate with the pattern behind the said liquid immersion lithography;
Step 13, in shallow channel isolation area after the fill oxide, at semiconductor substrate surface deposition gate oxide material;
Step 14,, the gate oxide material surface carries out EBR after being coated with the second photoresistance glue-line;
Step 15, the said second photoresistance glue-line is carried out photoetching and is that mask carries out after the wet etching of gate oxide material with the pattern after the said photoetching, form gate oxide.
Core concept of the present invention is: in the process that the making shallow trench isolation leaves, adopt liquid immersion lithography, be coated with HMDS, bottom anti-reflection layer, photoresistance glue-line and Topcoating successively at semiconductor substrate surface.Crucial is, above-mentioned each layer need not carry out EBR, have the HMDS of viscosity can thickness direction attached to Waffer edge on, Topcoating just can contact with HMDS on the thickness direction of Waffer edge, inside bottom anti-reflection layer and photoresistance glue-line are wrapped in.Therefore the bottom anti-reflection layer and the photoresistance glue-line that are wrapped in the inside need not carry out EBR, and promptly Waffer edge can remain with bottom anti-reflection layer and photoresistance glue-line.Like this after liquid immersion lithography; Waffer edge has had the protection of each layer to cover; So when the etching semiconductor substrate forms shallow channel isolation area; Just there is not rugged step of the prior art in Waffer edge, in shallow channel isolation area, during fill oxide, rugged step can not occur then yet.Next; When forming gate oxide, the photoresistance glue-line that is coated with at the gate oxide material surface need not carry out EBR yet, and Waffer edge is covered by the photoresistance glue-line fully; So when the gate oxide material is carried out wet etching formation gate oxide; Waffer edge just can not etched into by the sulfuric acid that wet etching adopted, and just the oxide particle defective can not occur yet, thereby realizes the object of the invention.
It is as shown in Figure 4 that the present invention reduces the schematic flow sheet of method of Waffer edge grain defect, and it may further comprise the steps:
Wherein, On semiconductor substrate surface, be coated with HMDS401; Main purpose is that wafer surface is increased glutinous the processing, is specially and under reduced pressure adopts the HMDS steam to form the HMDS monolayer at semiconductor substrate surface, and this method is a prior art; Also can adopt other to form the method for HMDS401 coating, repeat no more at this.Because HMDS has stickiness, make also to be attached with HMDS on the thickness direction of Waffer edge, can not look like to flow as the liquid.Topcoating 404 just can contact with HMDS on the thickness direction of Waffer edge, and the first photoresistance glue-line 403 and bottom anti-reflection layer 402 are rolled in the inside.Like this; The first photoresistance glue-line 403 just can the prior art that kind not contract to wafer central authorities; Promptly need not carry out EBR, the bottom anti-reflection layer 402 and the first photoresistance glue-line 403 align at Waffer edge and get final product, and this is because have the existence of the HMDS of stickiness; The phenomenon that produces grain defect can not appear peeling off in sufficient to guarantee first photoresistance glue-line 403 and the adhesion of bottom anti-reflection layer 402 at Waffer edge.
Wherein, The Topcoating 404 and the first photoresistance glue-line 403 can manifest bottom anti-reflection layer 402 then simultaneously by photoetching, and bottom anti-reflection layer 402 needs wet method to remove; The HMDS401 that then manifests also needs wet method to remove; For describing for simplicity,, be classified as in the photoetching process simply so omitted the description that bottom anti-reflection layer and HMDS need wet method to remove.
Owing in the forming process that shallow trench isolation leaves, its each coating is not carried out EBR, in line with the unified principle of each road process rule, so in the forming process of gate oxide; The second photoresistance glue-line of coating need not carry out EBR yet, like this, and not only in the forming process that shallow trench isolation leaves, during the etching semiconductor substrate; Waffer edge has had the covering of each coating, can not sustain damage, and in the forming process of gate oxide; During etching gate oxide material, Waffer edge also has the covering of the second photoresistance glue-line, also can not sustain damage; That is to say that Waffer edge rugged step can not occurred by intact protection; During wet etching gate oxide material, there is not oxide in its gate oxide material underneath, so the described oxide particle defective of prior art just can not occur.Therefore, follow-up in the process that polysilicon gate and CT form, just can there be grain defect, cause the polysilicon gate broken string, problem such as perhaps CT is blocked.
Further; Though the HMDS stickiness is very strong; But also might on the thickness direction of Waffer edge, peel off coating; In order to avoid Waffer edge grain defect to occur better, the preferred embodiment of the present invention is for adding the step that the HMDS on the thickness direction of Waffer edge, bottom anti-reflection layer, the first photoresistance glue-line and Topcoating are cleaned between step 41 and the step 42.This step is fairly simple, generally adopts plasma water (DI water) or propyleneglycoles ether acetate (PGMEA) or ethylene glycol monomethyl amine ether acetate (EGMEA) to clean, with each coating removal on the wafer thickness direction.
Need to prove that EBR according to the invention also can replace with Waffer edge exposure (WEE) operation with it when the EBR operation of carrying out the photoresistance glue-line, after WEE adopted the Waffer edge exposure exactly, developer solution directly showed to fall.This repeats no more for prior art.In addition, the present invention mainly introduces the appearance of how when forming gate oxide, avoiding the oxide particle defective, for describe clear for the purpose of, about other FEOLs, for example the formation of trap etc. is all omitted, these all are prior art, repeat no more at this.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (3)
1. a method that reduces the Waffer edge grain defect is applied in the leading portion manufacturing process of semiconductor device, and this method comprises:
On semiconductor substrate surface, be coated with HMDS HMDS, bottom anti-reflection layer, first photoresistance glue-line and the Topcoating successively; Wherein, HMDS, bottom anti-reflection layer, the first photoresistance glue-line and Topcoating also are attached on the thickness direction of Waffer edge;
The Topcoating and the first photoresistance glue-line are carried out liquid immersion lithography, and be that mask carries out after the etching of Semiconductor substrate, form shallow channel isolation area with the first photoresistance glue-line pattern behind the said liquid immersion lithography;
In shallow channel isolation area, after the fill oxide, deposit the gate oxide material at semiconductor substrate surface;
Be coated with the second photoresistance glue-line at the gate oxide material surface;
The said second photoresistance glue-line is carried out photoetching, and be that mask carries out after the wet etching of gate oxide material, form gate oxide with the second photoresistance glue-line pattern after the said photoetching.
2. the method for claim 1; It is characterized in that; After the coating Topcoating; Topcoating and the first photoresistance glue-line are carried out before the liquid immersion lithography, and this method further comprises: the HMDS on the thickness direction of Waffer edge, bottom anti-reflection layer, the first photoresistance glue-line and Topcoating are cleaned.
3. method as claimed in claim 2 is characterized in that, plasma water or propyleneglycoles ether acetate PGMEA or ethylene glycol monomethyl amine ether acetate EGMEA are adopted in said cleaning.
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| CN2010105070144A CN102446805A (en) | 2010-10-14 | 2010-10-14 | Method for reducing particle defects at edges of wafers |
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| CN2010105070144A CN102446805A (en) | 2010-10-14 | 2010-10-14 | Method for reducing particle defects at edges of wafers |
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| CN102446805A true CN102446805A (en) | 2012-05-09 |
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| CN2010105070144A Pending CN102446805A (en) | 2010-10-14 | 2010-10-14 | Method for reducing particle defects at edges of wafers |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104037064A (en) * | 2014-06-19 | 2014-09-10 | 上海华力微电子有限公司 | Immersed-type photoetching process method |
| CN104916529A (en) * | 2014-03-14 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | Method of manufacturing trench for trench power MOSFET chip |
| WO2019184694A1 (en) * | 2018-03-29 | 2019-10-03 | 武汉华星光电技术有限公司 | Substrate edge processing method and mask |
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| JP2010056365A (en) * | 2008-08-29 | 2010-03-11 | Nikon Corp | Exposure method and method of manufacturing device |
| CN101819382A (en) * | 2009-02-26 | 2010-09-01 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing wafer defects in edge bead removal process and wafer structure |
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| CN1166798A (en) * | 1994-11-22 | 1997-12-03 | 配合液系统公司 | Non-aminic photoresist adhesion promoters for microelectronic applications |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104916529A (en) * | 2014-03-14 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | Method of manufacturing trench for trench power MOSFET chip |
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| WO2019184694A1 (en) * | 2018-03-29 | 2019-10-03 | 武汉华星光电技术有限公司 | Substrate edge processing method and mask |
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Application publication date: 20120509 |