CN100590531C - Two time graph exposure method utilizing developing filler material - Google Patents
Two time graph exposure method utilizing developing filler material Download PDFInfo
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- CN100590531C CN100590531C CN200710040715A CN200710040715A CN100590531C CN 100590531 C CN100590531 C CN 100590531C CN 200710040715 A CN200710040715 A CN 200710040715A CN 200710040715 A CN200710040715 A CN 200710040715A CN 100590531 C CN100590531 C CN 100590531C
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Abstract
The invention discloses a double-graphics exposure method which makes use of developable filling materials; after completing the first lithography and etching, and peeling off the remainder first anti-reflective layer and first photoresist, the method coats the developable filling material on the surface of a silicon wafer through a wet method so as to fill the gap between hard masks; then the filling material is removed from the surface of the hard masks by developing the filling material, so as to form a level interface; later, the second lithography, etching and other technologies are carried through so as to eliminate the instability of the second lithography and etching technology caused by the height changes of the surface morphology step in the traditional double-graphics exposuretechnology to improve the performance of the double-graphics exposure technology.
Description
Technical field
The present invention relates to a kind of manufacture method of SIC (semiconductor integrated circuit), but relate in particular to a kind of secondary image exposure method that on the integrated circuit substrate, utilizes developing material.
Background technology
Along with dwindling of chip size, traditional single optical patterning technology can not satisfy the demand of semiconductor technology evolves, for potentiality, the more tiny chip live width of realization of further excavating and utilize existing equipment, secondary image exposure technology (Double Patterning) is arisen at the historic moment.
But also there is more problem in present secondary image exposure technology, shown in Fig. 1 a to Fig. 1 d, in the prior art, uses the positive photoresist exposure imaging to realize that the typical process flow of secondary image exposure technology is as follows:
(1) (Hard Mask, HM) 102 (for example silicon dioxide, silicon nitride, metal silicide) of the hard mask of deposit one deck on the substrate 101 to be etched;
(2) first anti-reflecting layers (Bottom Anti-Reflection Coating, BARC) 103 the coating and first photoresist (Photo Resist, PR) 104 coating;
(3) carry out the photoetching first time, at this moment the cross-section structure of silicon chip as shown in Figure 1a;
(4) carry out the etching first time, at first etch into first antireflecting coating 103 of non-photoresist protection zone, utilize first photoresist 104 as the etching masking layer subsequently, finish hard mask 102 etchings, this etching stopping is in substrate to be etched 101 surfaces;
(5) peel off first anti-reflecting layer 103 and first photoresist 104, at this moment the cross-section structure of silicon chip is shown in Fig. 1 b;
The coating of (6) second anti-reflecting layers 105, the coating of second photoresist 106;
(7) carry out the photoetching second time, at this moment the cross-section structure of silicon chip is shown in Fig. 1 c;
(8) carry out the etching second time, at first etch away second antireflecting coating 105 that covers hard mask 102 and non-photoresist protection zone, utilize the hard mask 102 and second photoresist 106 subsequently, the substrate 101 that etching exposes jointly as the etching masking layer.
(9) peel off remaining second anti-reflecting layer 105 and second photoresist 106, clean then, at this moment the cross-section structure of silicon chip is shown in Fig. 1 d;
(10) peel off remaining hard mask 102.
In this technological process, there is following shortcoming: because the etching selection ratio of hard mask layer and backing material is not high, therefore its thickness is thicker, the coating thickness that causes second antireflecting coating differs greatly in graphics intensive zone and the loose zone of figure, and then can influence follow-up photoetching, etching technics, cause being difficult to carry out accurate, repeatable explained hereafter.
Summary of the invention
But the technical problem to be solved in the present invention provides a kind of secondary image exposure method of utilization developing filler material, can avoid producing the problem that coating thickness is regional in graphics intensive and the loose zone of figure differs greatly of antireflecting coating for the second time, thereby improve the stability of photoetching for the second time and etching technics, improve the performance of secondary image exposure technology.
For solving the problems of the technologies described above, but the invention provides a kind of secondary image exposure method of utilization developing filler material, comprise the steps:
(1) the hard mask 202 of deposit one deck on silicon chip substrate to be etched 201;
(2) in deposit apply one deck first anti-reflecting layer 203 on the silicon chip of hard mask 202, on the silicon chip that has applied first anti-reflecting layer 203, apply first photoresist 204 then;
(3) carry out the photoetching first time;
(4) carry out the etching first time, at first, etch away first anti-reflecting layer 203 that is positioned at non-first photoresist 204 protection zones; Then, utilize first photoresist 204 as the etching masking layer, finish the etching for hard mask 202, this etching stopping is in substrate 201 surfaces;
(5) peel off first photoresist 204 and remaining first anti-reflecting layer 203;
(6) packing material 205 that can develop with wet method is coated in silicon chip surface, fills the gap between the hard mask 202;
(7) develop through the silicon chip after packing material 205 coatings, remove the packing material 205 of hard mask 202 surfaces, realize the smooth performance of silicon chip surface;
(8) applying second anti-reflecting layer 206, apply second photoresist 207 again at the silicon chip surface that has applied second anti-reflecting layer (206) then through the silicon chip surface after developing;
(9) carry out the photoetching second time;
(10) carry out the etching second time, at first, etch away second anti-reflecting layer (206) and the packing material (205) that are positioned at non-second photoresist (207) protection zone; Then, utilize hard mask (202) and second photoresist (207), etch away the substrate (201) of exposure as the etching masking layer;
(11) peel off second photoresist 207 and remaining second anti-reflecting layer 206 and packing material 205, clean then;
(12) peel off remaining hard mask 202.
The present invention is owing to adopted technique scheme, has such beneficial effect, promptly by finishing photoetching for the first time, etching, and peeled off remaining first anti-reflecting layer, after first photoresist, adopt wet method can develop the fillibility coated materials at silicon chip surface, to fill the gap between the hard mask, remove described fillibility material on the hard mask surface by the mode that described packing material is developed then, thereby form smooth interface, and then carry out the photoetching second time, technologies such as etching, thereby eliminated the photoetching of introducing owing to the height change of surface topography step in the traditional secondary image exposure technical matters second time, the instability of etching technics, the performance that has improved the secondary image exposure technology; And process of the present invention does not have the specific (special) requirements to the alignment precision of figure when carrying out photoetching for the second time.
Description of drawings
The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:
Fig. 1 a to Fig. 1 d is the silicon chip section of structure that utilizes the existing techniques in realizing secondary image exposure;
Fig. 2 is the schematic flow sheet that but the utilization developing filler material is realized secondary image exposure according to the present invention;
Fig. 3 a to Fig. 3 f is the silicon chip section of structure that but the utilization developing filler material is realized secondary image exposure according to the present invention.
Embodiment
As shown in Figure 2, but realize the schematic flow sheet of secondary image exposure for utilization developing filler material of the present invention, its detailed process is as follows:
The hard mask 202 of deposit one deck on substrate 201 to be etched (Hard Mask, HM), deposition thickness is 100 nanometer to 10000 nanometers; Wherein, hard mask 202 can be or be made of following material: as silicon dioxide, silicon nitride, metal silicide.
In deposit apply one deck first anti-reflecting layer (BottomAnti-Reflection Coating) 203 on the silicon chip of hard mask 202, coating thickness is 10 nanometer to 10000 nanometers, baking temperature is that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.Described first anti-reflecting layer can adopt following material: amorphous silicon, silicon nitride, silicon oxynitride, monox, doped silicon oxide, siloxicon, nitride, silicon nitride, titanium, titanium dioxide etc.Then, on the silicon chip that has applied first anti-reflecting layer 203, apply first photoresist (Photo Resist, PR) 204, coating thickness is 10 nanometer to 10000 nanometers, baking temperature is that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.
Silicon chip is carried out the photoetching first time, thereby form the cross-section structure shown in Fig. 3 a.Subsequently; described silicon chip is carried out the etching first time, at first etch away first anti-reflecting layer 203 that is positioned at non-first photoresist 204 protection zones, utilize first photoresist 204 then as the etching masking layer; finish the etching for hard mask 202, this etching stopping is in substrate 201 surfaces.After the described first time, etching was finished, peel off first photoresist 204 and remaining first anti-reflecting layer 203, thereby form the silicon chip cross-section structure shown in Fig. 3 b.
The packing material 205 that can develop with wet method is coated in silicon chip surface, to fill the gap between the hard mask 202.In the present invention, described packing material 205 is by ketone, ethers, organic solvents such as alkanes, antireflection absorbing material, can constitute with the organic acid group resin of standard Tetramethylammonium hydroxide developer solution reaction and the organic group resin that contains oxygen, fluorine element, cross-linked resin constitutes, its molecular weight is between 1000 to 50000, and refractive index is between 1.0 to 3.0, and extinction coefficient is between 0.1 to 3.0.Can fill gap between the hard mask 202 effectively in order to ensure packing material 205, can carry out the coating of 1～3 packing material 205 according to actual conditions, whenever after finishing the coating of a packing material 205, all tackle to apply to show and detect, to check whether it satisfies the requirement of filling the gap between the hard mask 202, if backlog demand then can apply for the 2nd～3 time, till meeting the demands.In one embodiment, the coating dosage of each coated packing material 205 is 0.5ml to 5ml, and baking temperature is 60 ℃ to 250 ℃, and stoving time is 10 seconds to 120 seconds.The silicon chip cross-section structure of finishing after packing material applies can be referring to Fig. 3 c.
Develop through the silicon chip after packing material 205 coatings,, realize the smooth performance of silicon chip surface to remove the packing material 205 of hard mask 202 surfaces.In the developing process, the temperature of used developer solution is 10 ℃ to 30 ℃, and the development soak time is 10 seconds to 120 seconds, re-uses the deionized water rinsing silicon chip surface subsequently, and to remove developer solution, flush time is 10 to 120 seconds.In order to remove the packing material 205 of hard mask 202 surfaces clean, realize smooth silicon chip surface, can carry out 1～3 time according to actual conditions develops, whenever after finishing once development, all tackling the performance of developing and detecting,, then can carry out the 2nd～3 time and develop if finding that the surface of hard mask 202 is also residual has a packing material 205, packing material 205 until hard mask 202 surfaces is all removed, and silicon chip surface is comparatively smooth.In one embodiment, each developer solution consumption that develops is 1ml to 100ml, and temperature is 10 ℃ to 30 ℃, and the development soak time is 10 seconds to 120 seconds.Can be through the silicon chip cross-section structure after developing with reference to figure 3d.
Applying second anti-reflecting layer 206 through the silicon chip surface after developing, coating thickness is 10 nanometer to 10000 nanometers, and baking temperature is that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.Wherein, described second anti-reflecting layer 206 can adopt following material: amorphous silicon, silicon nitride, silicon oxynitride, monox, doped silicon oxide, siloxicon, nitride, silicon nitride, titanium, titanium dioxide etc.Then, apply second photoresist 207 again at the silicon chip surface that has applied second anti-reflecting layer 206, applied thickness is that 10 nanometer to 10000 nanometers, baking temperature are that 50 ℃ to 250 ℃, stoving time are 10 seconds to 1000 seconds.
Silicon chip is carried out the photoetching second time, form the cross-section structure shown in Fig. 3 e.Subsequently; described silicon chip is carried out the etching second time; at first etch away second anti-reflecting layer 206 and the packing material 205 that are positioned at non-second photoresist 207 protection zones, utilize the hard mask 202 and second photoresist 207 then, etch away the substrate 201 of exposure as the etching masking layer.After described second time, etching was finished, but peel off second photoresist 207 and remaining second anti-reflecting layer 206 and wet method developing filler material 205, and silicon chip is cleaned, the cross-section structure of formed silicon chip is shown in Fig. 3 f.Then, after remaining hard mask 202 peeled off, promptly finished whole secondary image exposure process, formed chip with less live width spacing.
In sum, but the method for the invention is by utilizing developing filler material, avoid producing the problem that coating thickness is regional in graphics intensive and the loose zone of figure differs greatly of antireflecting coating for the second time, therefore improved the stability of photoetching for the second time, etching technics in the secondary image exposure technology.
Claims (7)
1, but a kind of secondary image exposure method of utilization developing filler material is characterized in that, comprising:
(1) goes up the hard mask of deposit one deck (202) in silicon chip substrate to be etched (201);
(2) in deposit apply one deck first anti-reflecting layer (203) on the silicon chip of hard mask (202), on the silicon chip that has applied first anti-reflecting layer (203), apply first photoresist (204) then;
(3) carry out the photoetching first time;
(4) carry out the etching first time, at first, etch away first anti-reflecting layer (203) that is positioned at non-first photoresist (204) protection zone; Then, utilize first photoresist (204) as the etching masking layer, finish the etching for hard mask (202), this etching stopping is in substrate (201) surface;
(5) peel off first photoresist (204) and remaining first anti-reflecting layer (203);
(6) packing material that can develop with wet method (205) is coated in silicon chip surface, fills the gap between the hard mask (202);
(7) develop through the silicon chip after packing material (205) coating, remove the packing material (205) of hard mask (202) surface, realize the smooth performance of silicon chip surface;
(8) applying second anti-reflecting layer (206), apply second photoresist (207) again at the silicon chip surface that has applied second anti-reflecting layer (206) then through the silicon chip surface after developing;
(9) carry out the photoetching second time;
(10) carry out the etching second time, at first, etch away second anti-reflecting layer (206) and the packing material (205) that are positioned at non-second photoresist (207) protection zone; Then, utilize hard mask (202) and second photoresist (207), etch away the substrate (201) of exposure as the etching masking layer;
(11) peel off second photoresist (207) and remaining second anti-reflecting layer (206) and packing material (205), clean then;
(12) peel off remaining hard mask (202).
But 2, the secondary image exposure method of utilization developing filler material according to claim 1, it is characterized in that, when carrying out described step (6), should carry out the coating of 1～3 packing material (205) according to actual conditions, whenever finish the coating of a packing material (205) after, all tackle applying performance and detect, to check whether it satisfies the requirement of filling the gap between the hard mask (202), if backlog demand then can apply for the 2nd～3 time, till meeting the demands.
But 3, according to the secondary image exposure method of claim 1 or 4 described utilization developing filler materials, it is characterized in that, described packing material (205) is by ketone, ethers, organic solvents such as alkanes, antireflection absorbing material, can constitute with the organic acid group resin of standard Tetramethylammonium hydroxide developer solution reaction and the organic group resin or the cross-linked resin that contain oxygen, fluorine element, its molecular weight is between 1000 to 50000, refractive index is between 1.0 to 3.0, and extinction coefficient is between 0.1 to 3.0.
But 4, the secondary image exposure method of utilization developing filler material according to claim 2, it is characterized in that, the coating dosage of each coated packing material (205) is 0.5ml to 5ml, and baking temperature is 60 ℃ to 250 ℃, and stoving time is 10 seconds to 120 seconds.
But 5, the secondary image exposure method of utilization developing filler material according to claim 1 and 2, it is characterized in that, when carrying out described step (7), should carry out 1～3 time according to actual conditions develops, whenever after finishing once development, all tackling the performance of developing detects, if find that the surface of hard mask (202) is also residual packing material (205) arranged, then can carry out the 2nd～3 time develops, packing material (205) until hard mask (202) surface is all removed, and silicon chip surface is smooth.
6, but the secondary image exposure method of utilization developing filler material according to claim 5 is characterized in that, each developer solution consumption that develops is 1ml to 100ml, and temperature is 10 ℃ to 30 ℃, and the development soak time is 10 seconds to 120 seconds.
But 7, the secondary image exposure method of utilization developing filler material according to claim 6, it is characterized in that, after packing material (205) is developed, also need use the deionized water rinsing silicon chip surface, to remove developer solution, flush time is 10 to 120 seconds.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710040715A CN100590531C (en) | 2007-05-16 | 2007-05-16 | Two time graph exposure method utilizing developing filler material |
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| CN200710040715A CN100590531C (en) | 2007-05-16 | 2007-05-16 | Two time graph exposure method utilizing developing filler material |
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| CN101308331A CN101308331A (en) | 2008-11-19 |
| CN100590531C true CN100590531C (en) | 2010-02-17 |
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| CN102841514A (en) * | 2011-06-23 | 2012-12-26 | 上海华虹Nec电子有限公司 | Method for implementing exposure of high-step surface graph by wet developable filling material |
| CN102903611B (en) * | 2012-09-19 | 2018-06-22 | 上海集成电路研发中心有限公司 | A kind of Metal-dielectric-metcapacitor capacitor and its manufacturing method |
| CN103337566A (en) * | 2013-06-19 | 2013-10-02 | 上海大学 | Patterned substrate manufacturing method |
| US9709884B2 (en) * | 2014-11-26 | 2017-07-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | EUV mask and manufacturing method by using the same |
| CN107359118B (en) * | 2017-07-31 | 2019-11-29 | 电子科技大学 | A kind of production method of super junction power device Withstand voltage layer |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Free format text: CORRECT: ADDRESS; FROM: 201206 PUDONG NEW AREA, SHANGHAI TO: 201203 PUDONG NEW AREA, SHANGHAI |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |