CN103400821B - Surface-mounted inductor and wafer-level manufacturing method thereof - Google Patents
Surface-mounted inductor and wafer-level manufacturing method thereof Download PDFInfo
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- CN103400821B CN103400821B CN201310350808.8A CN201310350808A CN103400821B CN 103400821 B CN103400821 B CN 103400821B CN 201310350808 A CN201310350808 A CN 201310350808A CN 103400821 B CN103400821 B CN 103400821B
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- 239000010410 layer Substances 0.000 claims description 196
- 229920002120 photoresistant polymer Polymers 0.000 claims description 26
- 238000007747 plating Methods 0.000 claims description 26
- 238000001259 photo etching Methods 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 7
- 238000005452 bending Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
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- 230000006698 induction Effects 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
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- 239000011241 protective layer Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
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- 230000008021 deposition Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
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- 238000009434 installation Methods 0.000 description 2
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- 230000003064 anti-oxidating effect Effects 0.000 description 1
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Abstract
The invention relates to a surface-mounted inductor and a wafer-level manufacturing method thereof, belonging to the field of passive device manufacturing. The surface protection type inductor comprises a substrate (110), more than one metal wiring layer (200) forming an inductor structure of a central inductor coil area and electrodes (300) of two side electrode areas, wherein different metal wiring layers (200) are electrically connected through a dielectric layer through hole (401), two metal wiring layers I (210) and two metal wiring layers II (220) of the metal wiring layers (200) extend towards the electrode areas on two sides and are respectively connected with the electrodes (300) on two sides at equal heights, and a surface protection layer (500) covers the surface of the metal wiring layer (200) on the uppermost layer. According to the invention, the structure of the inductor, the electrode and the like is manufactured on the surface of the wafer through the wafer-level rewiring process, so that the obtained surface-mounted inductor device has higher inductor precision, thinner thickness and higher reliability, the defect of single-side tilting during mounting can be overcome, and high-density mounting is realized.
Description
Technical field
The present invention relates to a kind of surface mount inductance component and wafer scale manufacture method thereof, belong to passive device and manufacture field.
Background technology
Inductance is requisite components and parts in electronic installation, and along with the trend of the hand-hold electronic device miniaturizations such as electronic installation especially mobile phone, inductor size is also more and more less.At present, wireless telecommunications radio frequency inductive model mainly contains 0201 size and 0402 size (English system), and wherein, the packaging body length of 0201 size model is between 500 microns to 700 microns, width is between 250 microns to 350 microns, and height is between 250 microns to 350 microns; The packaging body length of 0402 size model is between 900 microns to 1100 microns, and width is between 400 microns to 600 microns, and height is between 450 microns to 550 microns.Traditional inductance is mainly made by multilayer LTCC technique (LTCC technique), and its profile as shown in Figure 1.In this induction structure, its two ends are enclosed with conductive electrode, install in the circuit board by surface mount process, and in the reflux course of assembling, scolding tin can be climbed on the sidewall of electrode under the driving of wetting power, shown in figure as left in Fig. 2.Shown in figure as right in Fig. 2, along with inductance component constantly reduces, himself weight is also more and more lighter, if the wetting power imbalance of inductance two electrode and scolding tin will cause inductance one end to tilt in surface mount process, cause assembly failure, greatly reduce assembling yield.In addition, because scolding tin can climb electrode sidewall, if during assembling two inductance from too close to be just easy to occur scolding tin crossover, therefore need the distance of two devices to pull open when designed lines plate, so just have lost board area, high density attachment can not be realized.
In LTCC technique, formed by the mode of printing-sintering in order to form the metallic circuit of inductance coil, due to typography capabilities limits, metallic circuit dimensional accuracy is not high, also the printing of narrow pitch circuit cannot be realized, therefore its precision of inductance adopting this technique to make is lower, and its precision of inductance being usually less than 4nH can only reach +/-0.3nH, cannot meet the demand of efficient radio frequency system.In addition, as shown in Figure 3, adopt the inductance of LTCC technique to be generally sandwich construction, circuit is distributed in the whole thickness range of inductance, is therefore difficult to realize Ultrathin packaging.
Summary of the invention
From the above, the object of the invention is to the deficiency overcoming above-mentioned traditional ceramics inductance component, a kind of inductance precision is higher, thickness is thinner, reliability is higher, can overcome the one-sided tilting defect of attachment, realize high density attachment surface mount inductance component and wafer scale manufacture method thereof are provided.
the object of the present invention is achieved like this:
A kind of surface mount inductance component, comprise substrate, more than one deck form the metal wiring layer of the induction structure in central inductance coil region and the electrode of both sides electrode zone, described electrode zone is arranged at the top layer of surface mount inductance component, the height of the described electrode of both sides is equal, dielectric layer and dielectric layer through hole are set between different described metal wiring layers and form dielectric layer opening figure, be electrically connected by described dielectric layer through hole between different metal wiring layers, wherein two-layer described metal wiring layer is respectively metal wiring layer I and metal wiring layer II, described metal wiring layer I and metal wiring layer II extend respectively to both sides electrode zone, and respectively with the Electrode connection of both sides, described metal wiring layer II is arranged at the top of metal wiring layer I, at the superiors' metal wiring layer surface coverage sealer, and sealer opening figure is set.
Further, arrange coat of metal in described sealer opening figure, described coat of metal is to the sidewall of downward-extension parcel electrode, and described coat of metal is multi-layer metal structure.
Further, the cross section of described sealer opening figure is rectangular, and arrange the coat of metal with Electrode connection in it, described coat of metal is multi-layer metal structure.
Further, in inductance coil region, described metal wiring layer in the shape of a spiral or strip.
Further, described metal wiring layer I and metal wiring layer II by after bending and electrode sustained height with Electrode connection.
Further, between described substrate and metal wiring layer, passivation layer is set.
Further, the reduced thickness 100 ~ 200 microns of described surface mount inductance component.
Further, at electrode zone, described electrode is the extension of metal wiring layer.
Further, described wafer scale manufacture method comprises following technical process:
Step one, provide wafer, deposit plating seed layer by sputtering or evaporation coating method at crystal column surface;
Step 2, on above-mentioned wafer, apply photoresist, then utilize the photoetching processes such as exposure, development to form photoresist opening figure successively;
Step 3, plating seed layer in above-mentioned photoresist opening figure are electroplated, the electrode forming metal wiring layer I and is connected with metal wiring layer I, and remove photoresist with degumming process, then with the plating seed layer of etching process removal inactive area;
Step 4, on above-mentioned wafer, apply dielectric layer, form dielectric layer opening figure by photoetching process, and form dielectric layer through hole above metal wiring layer I;
Step 5, again deposit plating seed layer at above-mentioned whole crystal column surface, plating seed layer applies photoresist, utilize photoetching process to form photoresist opening figure;
Step 6, plating seed layer in above-mentioned photoresist opening figure are electroplated, the electrode forming metal wiring layer II and be connected with metal wiring layer II, metal wiring layer II and metal wiring layer I are by dielectric layer through-hole interconnection, realize electrical communication, and remove photoresist with degumming process, then remove the plating seed layer of inactive area with etching process;
Step 7, on above-mentioned wafer coating surface protective layer, form sealer opening figure by photoetching process;
Step 8, in sealer opening figure, formed the coat of metal of material nickel and/or gold by the method for chemical plating;
Step 9, wafer is thinning, and cutting forms single surface mount inductance component.
Further, before step 7, repeat above step 4 to step 6, form all the other metal wiring layers except metal wiring layer I and metal wiring layer II.
the invention has the beneficial effects as follows:
During the connection of 1, surface mount inductance component of the present invention and circuit board, electrode zone is positioned at the top layer of inductance component, scolding tin used can not be climbed on the sidewall of inductance component, therefore the bad phenomenon that there will not be one end to tilt when carrying out surface mount, the distance between two devices can be reduced simultaneously, promote wiring board utilance, realize high density attachment;
2, the present invention adopts wafer scale Wiring technique again, and compared with existing product, the thickness of surface mount inductance component of the present invention all can be thinning 100 ~ 200 microns, forms ultra-thin surface mount inductance component;
3, metal wiring layer of the present invention, dielectric layer, sealer and passivation layer all adopt photoetching process to make, and improve the dimensional accuracy of metal wiring layer, thus promote inductance precision, can control to +/-0.1nH for its precision of inductance being less than 4nH.
Accompanying drawing explanation
Fig. 1 is the 3-D view of traditional ceramics inductor;
Fig. 2 is traditional inductor normal and contrast schematic diagram that single-ended tilting is bad when mounting wiring board;
Fig. 3 is the 3-D view of the internal structure of traditional inductor;
Fig. 4 is the schematic diagram of a kind of surface mount inductance component of the present invention;
Fig. 5 is the cutaway view (embodiment one) of the A-A of Fig. 4;
Fig. 6 is the cutaway view (embodiment two) of the A-A of Fig. 4;
Fig. 7 to Figure 17 is the schematic diagram of the wafer scale manufacture method of a kind of surface mount inductance component of the present invention.
Wherein:
Wafer 100
Substrate 110
Metal wiring layer 200
Metal wiring layer I 210
Metal wiring layer II 220
Electrode 300
Dielectric layer 400
Dielectric layer through hole 401
Dielectric layer opening figure 410
Sealer 500
Sealer opening figure 501
Coat of metal 600
Passivation layer 700
Photoresist G1, G2
Photoresist opening figure G11, G21.
Embodiment
See Fig. 4 to Fig. 6, a kind of surface mount inductance component of the present invention, its central authorities are inductance coil region, and the top layer of the both sides in inductance coil region is electrode zone.
This surface mount inductance component comprises the metal wiring layer 200 that more than substrate 110, one deck form induction structure and the electrode 300 be arranged in electrode zone, and described substrate 110 can be silicon, glass or pottery etc.Electrode 300 is in strip, and height residing in surface mount inductance component is equal, and during to make the connection of surface mount inductance component and circuit board, the bad phenomenon that one end tilts does not appear in surface mount device.Dielectric layer 400 and dielectric layer through hole 401 be set between different metal wiring layers 200 and form dielectric layer opening figure 410, being electrically connected by dielectric layer through hole 401 between different metal wiring layers 200.Metal wiring layer 200 and dielectric layer 400 be all adopt wafer scale again Wiring technique formed by wafer scale photoetching on the substrate 110 of High Resistivity Si, pottery or glass wafer.In central inductance coil region, metal wiring layer 200 in the shape of a spiral or strip, determine according to actual needs by the shape of different metal wiring layers 200.
The wherein two-layer of metal wiring layer 200 is respectively metal wiring layer I 210 and metal wiring layer II 220, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, metal wiring layer II 220 in the shape of a spiral, metal wiring layer I 210 is in strip, as shown in Figure 4, metal wiring layer I 210 and metal wiring layer II 220 also can all in the shape of a spiral or all in strips.
Metal wiring layer I 210 and metal wiring layer II 220 extend respectively to the electrode zone of both sides, and are connected with the electrode 300 of both sides respectively.Metal wiring layer I 210 and metal wiring layer II 220 all can be connected with electrode 300 with after electrode 300 sustained height by bending.Illustrate in figure, metal wiring layer I 210 is contour with electrode 300, and is all arranged at the below of metal wiring layer II 220.Metal wiring layer I 210 is directly connected with electrode 300, is connected after highly equal with electrode 300 after metal wiring layer II 220 downward bending with electrode 300.At the superiors' metal wiring layer 200 surface coverage sealer 500, and sealer opening figure 501 is set.
Embodiment one
See Fig. 4 and Fig. 5, a kind of surface mount inductance component of the present invention, metal wiring layer 200 is arranged at the surface of substrate 110, in Fig. 5, metal wiring layer 200 for only illustrate metal wiring layer I 210 and metal wiring layer II 220 two-layer, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, and the two is connected by dielectric layer through hole 401, realizes electrical communication.Metal wiring layer I 210 and metal wiring layer II 220 extend respectively to both sides electrode zone, and are connected with the electrode 300 of the equal altitudes of both sides respectively.Arrange coat of metal 600 in sealer opening figure 501, coat of metal 600 is to the sidewall of downward-extension parcel electrode 300, and its material is the inert metal such as nickel, gold, and coat of metal 600 also can be multi-layer metal structure.
Embodiment two
See Fig. 4 and Fig. 6, a kind of surface mount inductance component of the present invention, as follows with embodiment one difference, between substrate 110 and metal wiring layer 200, also passivation layer 700 can be set, to improve the reliability of inductance component.In Fig. 6, metal wiring layer 200 for only illustrate metal wiring layer I 210 and metal wiring layer II 220 two-layer, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, and the two is connected by dielectric layer through hole 401, realizes electrical communication.Metal wiring layer I 210 and metal wiring layer II 220 extend respectively to both sides electrode zone, and are connected with the electrode 300 of the equal altitudes of both sides respectively, and if desired, metal wiring layer I 210 and metal wiring layer II 220 can bendings.The cross section of sealer opening figure 501 is rectangular; the coat of metal 600 be connected with electrode 300 is set in it; its material is the inert metal such as nickel, gold; also can be multi-layer metal structure, to improve the heat resistanceheat resistant moisture resistance of inductance component and to improve the switching performance of surface mount inductance component and circuit board.The size of sealer opening figure 501 is not more than the size of electrode 300, and in order to make, attachment is convenient, electrode 300 mounts firmly with circuit board, and sealer opening figure 501 should be large as far as possible.
Dielectric layer 400 of the present invention, sealer 500 and passivation layer 700 all play the effects such as insulation, anti-oxidation, support; its material can be identical; also different materials can be adopted according to actual conditions; three does not have absolute border to distinguish in the inside of inductance component, any similar structure all falls within the protection range of this patent.
Surface mount inductance component of the present invention, adopts wafer scale Wiring technique again, final formation 0201 size model and 0402 size model.The thickness of above two kinds of surface mount inductance components all can be thinning 100 ~ 200 microns, forms ultra-thin surface mount inductance component.
The wafer scale manufacture method of a kind of surface mount inductance component of the present invention, for embodiment one structure, its wafer scale manufacture method comprises following process:
Step one, provide wafer 100, by methods such as sputtering or evaporations at wafer 100 surface deposition plating seed layer (not shown plating seed layer); As shown in Figure 7.
Step 2, on above-mentioned wafer 100, apply photoresist G1, then utilize the photoetching processes such as exposure, development to form photoresist opening figure G11 successively; As shown in Figure 8.
Step 3, plating seed layer in above-mentioned photoresist opening figure G11 are electroplated, the electrode 300 forming metal wiring layer I 210 and be connected with metal wiring layer I 210, and remove photoresist G1 with degumming process, then remove the plating seed layer of inactive area with etching process; As shown in Figure 9 and Figure 10.
Step 4, on above-mentioned wafer 100, apply dielectric layer 400, form dielectric layer opening figure 410 by photoetching process, and form dielectric layer through hole 401 above metal wiring layer I 210; As shown in figure 11.
Step 5, again deposit plating seed layer (not shown plating seed layer) on above-mentioned whole Zhang Jingyuan 100 surface, plating seed layer applies photoresist G2, utilize photoetching process to form photoresist opening figure G21; As shown in figure 12.
Step 6, plating seed layer in above-mentioned photoresist opening figure G21 are electroplated, the electrode 300 forming metal wiring layer II 220 and be connected with metal wiring layer II 220, metal wiring layer II 220 and metal wiring layer I 210 are interconnected by dielectric layer through hole 401, realize electrical communication, and remove photoresist G2 with degumming process, then remove the plating seed layer of inactive area with etching process; As shown in Figure 13 and Figure 14.
Step 7, on above-mentioned wafer 100 coating surface protective layer 500, form sealer opening figure 501 by photoetching process; As shown in figure 15.
Step 8, in sealer opening figure 501, formed the coat of metal 600 of material nickel and/or gold by the method for chemical plating; As shown in figure 16.
Step 9, by thinning for wafer 100, and cutting formed single surface mount inductance component; As shown in figure 17.
If make two-layer above induction structure, the making of all the other metal wiring layers 200 except metal wiring layer I 210 and metal wiring layer II 220 needs to repeat above step 4 to step 6.
Wherein, metal wiring layer 200, dielectric layer 400, sealer 500 and passivation layer 700 adopt photoetching process to make; improve the dimensional accuracy of metal wiring layer 200, thus improve inductance precision, can +/-0.1nH be controlled to for its precision of inductance being less than 4nH.
The wafer scale manufacture method of a kind of surface mount inductance component of the present invention, not only can form 0201 size model and 0402 size model, also may be used for the surface mount inductance component making other size model, and its existing thickness thinning, improve its existing inductance precision.
At electrode zone, described electrode 300 of the present invention also can be the extension of metal wiring layer 200, the identical function of the connection of this metal wiring layer 200 electrodes 300 and circuit board.In an embodiment, for make follow-up be connected with circuit board time, attachment operation smooth, rise an electrode 300 highly need equal with the metal wiring layer 200 of the connection said function of circuit board, its implementation is as follows:
One, metal wiring layer II 220 can both direction extend to the left and right, has made electrode 300 highly identical with the metal wiring layer II 220 of the connection said function of circuit board, has made follow-up attachment operation smooth;
Two, the metal wiring layer I 210 be connected with circuit board and/or metal wiring layer II 220 can be connected with circuit board after bending to sustained height again.
Claims (9)
1. a surface mount inductance component, it is characterized in that: comprise substrate (110), be formed at the metal wiring layer (200) of the induction structure in central inductance coil region and the electrode (300) of both sides electrode zone, described electrode zone is arranged at the top layer of surface mount inductance component, the height of the described electrode (300) of both sides is equal, dielectric layer (400) and dielectric layer through hole (401) are set between different described metal wiring layers (200) and form dielectric layer opening figure (410), be electrically connected by described dielectric layer through hole (401) between different metal wiring layers (200), described metal wiring layer (200) comprises metal wiring layer I (210) and metal wiring layer II (220), described metal wiring layer I (210) and metal wiring layer II (220) extend respectively to both sides electrode zone, and be connected with the electrode (300) of both sides respectively, described metal wiring layer II (220) is arranged at the top of metal wiring layer I (210), at the superiors' metal wiring layer (200) surface coverage sealer (500), and sealer opening figure (501) is set.
2. a kind of surface mount inductance component according to claim 1; it is characterized in that: in described sealer opening figure (501), coat of metal (600) is set; described coat of metal (600) is to the sidewall of downward-extension parcel electrode (300), and described coat of metal (600) is multi-layer metal structure.
3. a kind of surface mount inductance component according to claim 1; it is characterized in that: the cross section of described sealer opening figure (501) is rectangular; arrange the coat of metal (600) be connected with electrode (300) in it, described coat of metal (600) is multi-layer metal structure.
4. a kind of surface mount inductance component according to claim 1, is characterized in that: in inductance coil region, and described metal wiring layer (200) in the shape of a spiral or strip.
5. a kind of surface mount inductance component according to claim 1, is characterized in that: described metal wiring layer I (210) is connected with electrode (300) with after electrode (300) sustained height by bending with metal wiring layer II (220).
6. a kind of surface mount inductance component according to claim 1, is characterized in that: arrange passivation layer (700) between described substrate (110) and metal wiring layer (200).
7. a kind of surface mount inductance component according to claim 1, is characterized in that: at electrode zone, the extension that described electrode (300) is metal wiring layer (200).
8. a wafer scale manufacture method for a kind of surface mount inductance component as claimed in claim 2, is characterized in that: described wafer scale manufacture method comprises following technical process:
Step one, provide wafer (100), by sputtering or evaporation coating method at wafer (100) surface deposition plating seed layer;
Step 2, on above-mentioned wafer (100), apply photoresist (G1), then utilize the photoetching processes such as exposure, development to form photoresist opening figure (G11) successively;
Step 3, plating seed layer in above-mentioned photoresist opening figure (G11) are electroplated, the electrode (300) forming metal wiring layer I (210) and be connected with metal wiring layer I (210), and remove photoresist (G1) with degumming process, then remove the plating seed layer of inactive area with etching process;
Step 4, on above-mentioned wafer (100), apply dielectric layer (400), form dielectric layer opening figure (410) by photoetching process, and form dielectric layer through hole (401) in metal wiring layer I (210) top;
Step 5, again deposit plating seed layer on above-mentioned wafer (100) surface, plating seed layer applies photoresist (G2), utilize photoetching process to form photoresist opening figure (G21);
Step 6, plating seed layer in above-mentioned photoresist opening figure (G21) are electroplated, the electrode (300) forming metal wiring layer II (220) and be connected with metal wiring layer II (220), metal wiring layer II (220) and metal wiring layer I (210) are interconnected by dielectric layer through hole (401), realize electrical communication, and remove photoresist (G2) with degumming process, then remove the plating seed layer of inactive area with etching process;
Step 7, at the upper coating surface protective layer (500) of above-mentioned wafer (100), form sealer opening figure (501) by photoetching process;
Step 8, in sealer opening figure (501), formed the coat of metal (600) of material nickel and/or gold by the method for chemical plating;
Step 9, by thinning for wafer (100), and cutting formed single surface mount inductance component.
9. the wafer scale manufacture method of a kind of surface mount inductance component according to claim 8, it is characterized in that: before step 7, repeat above step 4 to step 6, form all the other metal wiring layers (200) except metal wiring layer I (210) and metal wiring layer II (220).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1431709A (en) * | 2001-12-14 | 2003-07-23 | 富士通株式会社 | Electronic device |
| CN101030576A (en) * | 2006-03-03 | 2007-09-05 | 精工爱普生株式会社 | Electronic substrate, semiconductor device, and electronic device |
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| JP5767495B2 (en) * | 2011-03-29 | 2015-08-19 | パナソニック株式会社 | Variable inductor and semiconductor device using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431709A (en) * | 2001-12-14 | 2003-07-23 | 富士通株式会社 | Electronic device |
| CN101030576A (en) * | 2006-03-03 | 2007-09-05 | 精工爱普生株式会社 | Electronic substrate, semiconductor device, and electronic device |
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