CN103400821A - Surface-mounted inductor and wafer-level manufacturing method thereof - Google Patents
Surface-mounted inductor and wafer-level manufacturing method thereof Download PDFInfo
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- CN103400821A CN103400821A CN2013103508088A CN201310350808A CN103400821A CN 103400821 A CN103400821 A CN 103400821A CN 2013103508088 A CN2013103508088 A CN 2013103508088A CN 201310350808 A CN201310350808 A CN 201310350808A CN 103400821 A CN103400821 A CN 103400821A
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Abstract
The invention relates to a surface-mounted inductor and a wafer-level manufacturing method thereof and belongs to the field of manufacturing of passive devices. The surface-mounted inductor comprises a substrate (110), more than one metal wiring layer (200) which form an inductance structure in a central inductance coil area, and electrodes (300) in electrode areas on two sides; the metal wiring layers (200) are electrically connected through dielectric layer through holes (401); a metal wiring layer I (210) and a metal wiring layer II (220) of the metal wiring layers (200) extend to the electrode areas on the two sides and are connected with the electrodes (300) which have the same height on the two sides; a surface protecting layer (500) covers the surface of the metal wiring layer (200) in the upper most layer. According to the invention, inductors, electrodes and other structures are manufactured on the surface of a wafer through a wafer-level re-wiring technology, so that the obtained surface-mounted inductor is higher in inductance precision, smaller in thickness, and higher in reliability, and can overcome the defect of upwarp of a single side in surface-mounting, and realize high-density surface-mount.
Description
Technical field
The present invention relates to a kind of surface mount inductance component and wafer scale manufacture method thereof, belong to passive device and make field.
Background technology
Inductance is requisite components and parts in electronic installation, and along with the trend of the hand-hold electronic device miniaturizations such as electronic installation especially mobile phone, inductor size is also more and more less.At present, wireless telecommunications mainly contain 0201 size and 0402 size (English system) with the radio frequency inductive model, and wherein, the packaging body length of 0201 size model is between 500 microns to 700 microns, width is between 250 microns to 350 microns, and height is between 250 microns to 350 microns; The packaging body length of 0402 size model is between 900 microns to 1100 microns, and width is between 400 microns to 600 microns, and height is between 450 microns to 550 microns.Traditional inductance is mainly to be made by multilayer LTCC technique (LTCC technique), and its profile as shown in Figure 1.Its two ends are enclosed with conductive electrode in this induction structure, by surface mount process, install in the circuit board, and in the reflux course of assembling, scolding tin can climbed to the sidewall of electrode, as shown in figure as left in Fig. 2 under the driving of wetting power.As shown in figure as right in Fig. 2, along with inductance component constantly dwindles, himself weight is also more and more lighter, if the wetting power imbalance of inductance two electrodes and scolding tin will cause inductance one end perk in the surface mount process, cause assembly failure, greatly reduce the assembling yield.In addition, because scolding tin can be climbed electrode sidewall, if during assembling two inductance from too close to just be easy to occur the scolding tin crossover, therefore the distance of two devices need to be pulled open when the designed lines plate, so just lost board area, can not realize that high density mounts.
In LTCC technique, that mode by printing-sintering forms in order to the metallic circuit that forms inductance coil, due to the typography capabilities limits, the metallic circuit dimensional accuracy is not high, also can't realize the printing of narrow pitch circuit, therefore its precision of inductance that adopts this technique to make is lower, and its precision of inductance less than 4nH can only reach +/-0.3nH usually, can't meet the demand of efficient radio frequency system.In addition, as shown in Figure 3, adopt the inductance of LTCC technique to be generally sandwich construction, circuit is distributed in the whole thickness range of inductance, therefore is difficult to realize Ultrathin packaging.
Summary of the invention
From the above, the object of the invention is to overcome the deficiency of above-mentioned traditional ceramics inductance component, provide that a kind of inductance precision is higher, thickness is thinner, reliability is higher, can overcome and mount one-sided perk defect, realize surface mount inductance component and wafer scale manufacture method thereof that high density mounts.
The object of the present invention is achieved like this:
a kind of surface mount inductance component, comprise substrate, the metal wiring layer of the induction structure in the above formation of one deck central inductance coil zone and the electrode of both sides electrode zone, described electrode zone is arranged at the top layer of surface mount inductance component, the height of the described electrode of both sides equates, dielectric layer and dielectric layer through hole are set between different described metal wiring layers and form the dielectric layer opening figure, be electrically connected by described dielectric layer through hole between different metal wiring layers, wherein two-layer described metal wiring layer is respectively metal wiring layer I and metal wiring layer II, described metal wiring layer I and metal wiring layer II are extended to the both sides electrode zone respectively, and be connected with the electrode of both sides respectively, described metal wiring layer II is arranged at the top of metal wiring layer I, at the superiors' metal wiring layer surface coverage sealer, and the sealer opening figure is set.
Further, in described sealer opening figure, coat of metal is set, described coat of metal is to the sidewall of downward-extension parcel electrode, and described coat of metal is multi-layer metal structure.
Further, the cross section of described sealer opening figure is rectangular, and the coat of metal that is connected with electrode is set in it, and described coat of metal is multi-layer metal structure.
Further, in inductance coil zone, described metal wiring layer in the shape of a spiral or strip.
Further, described metal wiring layer I and metal wiring layer II are connected with electrode by after bending and electrode sustained height.
Further, between described substrate and metal wiring layer, passivation layer is set.
Further, 100～200 microns of the reduced thickness of described surface mount inductance component.
Further, at electrode zone, described electrode is the extension of metal wiring layer.
Further, described wafer scale manufacture method comprises following technical process:
Step 1, provide wafer, by sputter or evaporation coating method, at crystal column surface, deposit plating seed layer;
Step 2, apply photoresist on above-mentioned wafer, then utilize the photoetching processes formation photoresist opening figure such as exposure, development successively;
Step 3, the enterprising electroplating of plating seed layer in above-mentioned photoresist opening figure, form metal wiring layer I and the electrode that is connected with the metal wiring layer I, and with degumming process, remove photoresist, then remove the plating seed layer of inactive area with etching process;
Step 4, apply dielectric layer on above-mentioned wafer, by photoetching process, form the dielectric layer opening figure, and form the dielectric layer through hole above the metal wiring layer I;
Step 5, at above-mentioned whole crystal column surface, again deposit plating seed layer, apply photoresist on plating seed layer, utilize photoetching process to form the photoresist opening figure;
Step 6, the enterprising electroplating of plating seed layer in above-mentioned photoresist opening figure, form metal wiring layer II and the electrode that is connected with the metal wiring layer II, metal wiring layer II and metal wiring layer I are by the dielectric layer through-hole interconnection, realize electrical communication, and with degumming process, remove photoresist, then remove the plating seed layer of inactive area with etching process;
Step 7, on above-mentioned wafer the coating surface protective layer, form the sealer opening figure by photoetching process;
Step 8, the method by chemical plating form material nickel and/or golden coat of metal in the sealer opening figure;
Step 9, with the wafer attenuate, and cutting forms single surface mount inductance component.
Further, before step 7, repeat above step 4 to step 6, form all the other metal wiring layers except metal wiring layer I and metal wiring layer II.
The invention has the beneficial effects as follows:
1, during being connected of surface mount inductance component of the present invention and circuit board, electrode zone is positioned at the top layer of inductance component, scolding tin used can not climbed on the sidewall of inductance component, therefore not there will be the bad phenomenon of an end perk when carrying out surface mount, simultaneously can reduce two distances between device, promote the wiring board utilance, realize that high density mounts;
2, the present invention adopts wafer scale Wiring technique again, compare with existing product, but equal 100～200 microns of the attenuates of the thickness of surface mount inductance component of the present invention forms ultra-thin surface mount inductance component;
3, metal wiring layer of the present invention, dielectric layer, sealer and passivation layer all adopt photoetching process to make, and have improved the dimensional accuracy of metal wiring layer, thereby promote the inductance precision, for its precision of the inductance less than 4nH, can control to +/-0.1nH.
Description of drawings
Fig. 1 is the 3-D view of traditional ceramics inductor;
Fig. 2 is traditional inductor normal and contrast schematic diagram that single-ended perk is bad while mounting wiring board;
Fig. 3 is the 3-D view of the internal structure of traditional inductor;
Fig. 4 is the schematic diagram of a kind of surface mount inductance component of the present invention;
Fig. 5 is the cutaway view (embodiment one) of the A-A of Fig. 4;
Fig. 6 is the cutaway view (embodiment two) of the A-A of Fig. 4;
Fig. 7 to Figure 17 is the schematic diagram of the wafer scale manufacture method of a kind of surface mount inductance component of the present invention.
Wherein:
Wafer 100
Metal wiring layer 200
Metal wiring layer I 210
Metal wiring layer II 220
Electrode 300
Dielectric layer through hole 401
Dielectric layer opening figure 410
Sealer opening figure 501
Coat of metal 600
Photoresist G1, G2
Photoresist opening figure G11, G21.
Embodiment
Referring to Fig. 4 to Fig. 6, a kind of surface mount inductance component of the present invention, its central authorities are the inductance coil zone, the top layer of the both sides in inductance coil zone is electrode zone.
This surface mount inductance component comprises substrate 110, one deck is above forms the metal wiring layer 200 of induction structure and is arranged at the interior electrode 300 of electrode zone, and described substrate 110 can be silicon, glass or pottery etc.Electrode 300 is strip, and residing height equates in the surface mount inductance component, so that during being connected of surface mount inductance component and circuit board, the bad phenomenon of an end perk does not appear in surface mount device.Dielectric layer 400 and dielectric layer through hole 401 be set between different metal wiring layers 200 and form dielectric layer opening figure 410, being electrically connected by dielectric layer through hole 401 between different metal wiring layers 200.Metal wiring layer 200 and dielectric layer 400 be all adopt wafer scale again Wiring technique form by the wafer scale photoetching on the substrate 110 of High Resistivity Si, pottery or glass wafer.In central inductance coil zone, metal wiring layer 200 in the shape of a spiral or strip, determine according to actual needs by the shape of different metal wiring layers 200.
Wherein two-layer metal wiring layer I 210 and the metal wiring layer II 220 of being respectively of metal wiring layer 200, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, metal wiring layer II 220 in the shape of a spiral, metal wiring layer I 210 is strip, as shown in Figure 4, metal wiring layer I 210 and metal wiring layer II 220 also can all be strip in the shape of a spiral or all.
Metal wiring layer I 210 and metal wiring layer II 220 are extended to the electrode zone of both sides respectively, and are connected with the electrode 300 of both sides respectively.Metal wiring layer I 210 is connected with the metal wiring layer II all and can be connected with electrode 300 by after bending and electrode 300 sustained heights.Illustrate in figure, metal wiring layer I 210 is contour with electrode 300, and all is arranged at the below of metal wiring layer II 220.Metal wiring layer I 210 directly is connected with electrode 300, is connected with electrode 300 after metal wiring layer II 220 downward bendings with after electrode 300 highly equates.At the superiors' metal wiring layer 200 surface coverage sealers 500, and sealer opening figure 501 is set.
Embodiment one
Referring to Fig. 4 and Fig. 5, a kind of surface mount inductance component of the present invention, metal wiring layer 200 is arranged at the surface of substrate 110, in Fig. 5, metal wiring layer 200 is only to illustrate metal wiring layer I 210 and metal wiring layer II 220 two-layer as example, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, both by dielectric layer through hole 401, connects, and realizes electrical communication.Metal wiring layer I 210 and metal wiring layer II 220 are extended to the both sides electrode zone respectively, and are connected with the electrode 300 of the equal altitudes of both sides respectively.The interior coat of metal 600 that arranges of sealer opening figure 501, coat of metal 600 is to the sidewall of downward-extension parcel electrode 300, and its material is the inert metals such as nickel, gold, and coat of metal 600 also can be multi-layer metal structure.
Embodiment two
Referring to Fig. 4 and Fig. 6, a kind of surface mount inductance component of the present invention, as follows with embodiment one difference, also passivation layer 700 can be set between substrate 110 and metal wiring layer 200, to improve the reliability of inductance component.In Fig. 6, metal wiring layer 200 is only to illustrate metal wiring layer I 210 and metal wiring layer II 220 two-layer as example, and metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, both by dielectric layer through hole 401, connects, and realizes electrical communication.Metal wiring layer I 210 and metal wiring layer II 220 are extended to the both sides electrode zone respectively, and are connected with the electrode 300 of the equal altitudes of both sides respectively, and in case of necessity, metal wiring layer I 210 and metal wiring layer II 220 can bendings.The cross section of sealer opening figure 501 is rectangular; the coat of metal 600 that is connected with electrode 300 is set in it; its material is the inert metals such as nickel, gold; also can be multi-layer metal structure, with the heat resistanceheat resistant moisture resistance that improves inductance component and the switching performance that improves surface mount inductance component and circuit board.The size of sealer opening figure 501 is not more than the size of electrode 300, mounts conveniently for making, electrode 300 mounts firmly with circuit board, and sealer opening figure 501 should be large as far as possible.
Surface mount inductance component of the present invention, adopt wafer scale Wiring technique again, finally forms 0201 size model and 0402 size model.The thickness of above two kinds of surface mount inductance components all can attenuate 100～200 microns, forms ultra-thin surface mount inductance component.
The wafer scale manufacture method of a kind of surface mount inductance component of the present invention, take embodiment one structure as example, its wafer scale manufacture method comprises following process:
Step 1, provide wafer 100, by methods such as sputter or evaporations at wafer 100 surface deposition plating seed layers (not shown plating seed layer); As shown in Figure 7.
Step 2, apply photoresist G1 on above-mentioned wafer 100, then utilize the photoetching processes formation photoresist opening figure G11 such as exposure, development successively; As shown in Figure 8.
Step 3, the enterprising electroplating of plating seed layer in above-mentioned photoresist opening figure G11, form metal wiring layer I 210 and the electrode 300 that is connected with metal wiring layer I 210, and with degumming process, remove photoresist G1, then remove the plating seed layer of inactive area with etching process; As shown in Figure 9 and Figure 10.
Step 4, apply dielectric layer 400 on above-mentioned wafer 100, by photoetching process, form dielectric layer opening figure 410, and above metal wiring layer I 210 formation dielectric layer through hole 401; As shown in figure 11.
Step 5, on above-mentioned whole Zhang Jingyuan 100 surfaces, again deposit plating seed layer (not shown plating seed layer), apply photoresist G2 on plating seed layer, utilize photoetching process to form photoresist opening figure G21; As shown in figure 12.
Step 6, the enterprising electroplating of plating seed layer in above-mentioned photoresist opening figure G21, form metal wiring layer II 220 and the electrode 300 that is connected with metal wiring layer II 220, metal wiring layer II 220 interconnects by dielectric layer through hole 401 with metal wiring layer I 210, realize electrical communication, and with degumming process, remove photoresist G2, then remove the plating seed layer of inactive area with etching process; As shown in Figure 13 and Figure 14.
Step 7, on above-mentioned wafer 100 coating surface protective layer 500, form sealer opening figure 501 by photoetching process; As shown in figure 15.
Step 8, the method by chemical plating are at the coat of metal 600 of sealer opening figure 501 interior formation material nickel and/or gold; As shown in figure 16.
Step 9, with wafer 100 attenuates, and cutting forms single surface mount inductance component; As shown in figure 17.
If make two-layer above induction structure, the making of all the other metal wiring layers 200 except metal wiring layer I 210 and metal wiring layer II 220 need to repeat above step 4 to step 6.
Wherein, metal wiring layer 200, dielectric layer 400, sealer 500 and passivation layer 700 adopt photoetching process to make; improve the dimensional accuracy of metal wiring layer 200, thereby promoted the inductance precision, for its precision of the inductance less than 4nH, can control to +/-0.1nH.
The wafer scale manufacture method of a kind of surface mount inductance component of the present invention, not only can form 0201 size model and 0402 size model, also can be used for make the surface mount inductance component of other size model, and its existing thickness of attenuate, improve its existing inductance precision.
At electrode zone, described electrode 300 of the present invention can be also the extension of metal wiring layer 200, the identical function that is connected of 200 electrodes 300 of this metal wiring layer and circuit board.In an embodiment, follow-up while with circuit board, being connected for making, mount operation smooth, highly needs are equal to play the metal wiring layer that is connected said function 200 of electrode 300 and circuit board, and its implementation is as follows:
One, metal wiring layer II 220 to the left and right both direction extend, made electrode 300 highly identical with the metal wiring layer II 220 of the connection said function of circuit board, make that follow-up to mount operation smooth;
Two, the metal wiring layer I 210 that is connected with circuit board and/or metal wiring layer II 220 can be connected with circuit board in bending again to sustained height.
Claims (10)
1. surface mount inductance component, it is characterized in that: comprise substrate (110), the metal wiring layer (200) of the induction structure in the above formation of one deck central inductance coil zone and the electrode (300) of both sides electrode zone, described electrode zone is arranged at the top layer of surface mount inductance component, the height of the described electrode (300) of both sides equates, dielectric layer (400) and dielectric layer through hole (401) are set between different described metal wiring layers (200) and form dielectric layer opening figure (410), be electrically connected by described dielectric layer through hole (401) between different metal wiring layer (200), wherein two-layer described metal wiring layer (200) is respectively metal wiring layer I (210) and metal wiring layer II (220), described metal wiring layer I (210) and metal wiring layer II (220) are extended to the both sides electrode zone respectively, and be connected with the electrode (300) of both sides respectively, described metal wiring layer II (220) is arranged at the top of metal wiring layer I (210), at the superiors' metal wiring layer (200) surface coverage sealer (500), and sealer opening figure (501) is set.
2. a kind of surface mount inductance component according to claim 1; it is characterized in that: coat of metal (600) is set in described sealer opening figure (501); described coat of metal (600) is to the sidewall of downward-extension parcel electrode (300), and described coat of metal (600) is multi-layer metal structure.
3. a kind of surface mount inductance component according to claim 1; it is characterized in that: the cross section of described sealer opening figure (501) is rectangular; the coat of metal (600) that is connected with electrode (300) is set in it, and described coat of metal (600) is multi-layer metal structure.
4. a kind of surface mount inductance component according to claim 1 is characterized in that: in the inductance coil zone, described metal wiring layer (200) in the shape of a spiral or strip.
5. a kind of surface mount inductance component according to claim 1, it is characterized in that: described metal wiring layer I (210) is connected 220 with the metal wiring layer II) be connected with electrode (300) by after bending and electrode (300) sustained height.
6. a kind of surface mount inductance component according to claim 1, is characterized in that: between described substrate (110) and metal wiring layer (200), passivation layer (700) is set.
7. a kind of surface mount inductance component according to claim 1, is characterized in that: 100～200 microns of the reduced thickness of described surface mount inductance component.
8. a kind of surface mount inductance component according to claim 1, it is characterized in that: at electrode zone, described electrode (300) is the extension of metal wiring layer (200).
9. the wafer scale manufacture method of an a kind of surface mount inductance component as claimed in claim 2, it is characterized in that: described wafer scale manufacture method comprises following technical process:
Step 1, provide wafer (100), by sputter or evaporation coating method at wafer (100) surface deposition plating seed layer;
Step 2, apply photoresist (G1) above-mentioned wafer (100) is upper, then utilize the photoetching processes formation photoresist opening figure (G11) such as exposure, development successively;
Step 3, the enterprising electroplating of plating seed layer in above-mentioned photoresist opening figure (G11), form metal wiring layer I (210) and the electrode (300) that is connected with metal wiring layer I (210), and with degumming process, remove photoresist (G1), then remove the plating seed layer of inactive area with etching process;
Step 4, at the upper dielectric layer (400) that applies of above-mentioned wafer (100), forms dielectric layer opening figure (410) by photoetching process, and at metal wiring layer I (210) top formation dielectric layer through hole (401);
Step 5, on above-mentioned whole Zhang Jingyuan (100) surface, again deposit plating seed layer, apply photoresist (G2) on plating seed layer, utilize photoetching process to form photoresist opening figure (G21);
Step 6, the enterprising electroplating of plating seed layer in above-mentioned photoresist opening figure (G21), form metal wiring layer II (220) and the electrode (300) that is connected with metal wiring layer II (220), metal wiring layer II (220) interconnects by dielectric layer through hole (401) with metal wiring layer I (210), realize electrical communication, and with degumming process, remove photoresist (G2), then remove the plating seed layer of inactive area with etching process;
Step 7, at the upper coating surface protective layer (500) of above-mentioned wafer (100), form sealer opening figure (501) by photoetching process;
Step 8, the method by chemical plating form material nickel and/or golden coat of metal (600) sealer opening figure (501) in;
Step 9, with wafer (100) attenuate, and cutting forms single surface mount inductance component.
10. the wafer scale manufacture method of a kind of surface mount inductance component according to claim 9, it is characterized in that: before step 7, repeat above step 4 to step 6, form all the other metal wiring layers (200) except metal wiring layer I (210) and metal wiring layer II (220).
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431709A (en) * | 2001-12-14 | 2003-07-23 | 富士通株式会社 | Electronic device |
| CN101030576A (en) * | 2006-03-03 | 2007-09-05 | 精工爱普生株式会社 | Electronic substrate, semiconductor device, and electronic device |
| US20130140672A1 (en) * | 2011-03-29 | 2013-06-06 | Panasonic Corporation | Variable inductor and semiconductor device using same |
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- 2013-08-13 CN CN201310350808.8A patent/CN103400821B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1431709A (en) * | 2001-12-14 | 2003-07-23 | 富士通株式会社 | Electronic device |
| CN101030576A (en) * | 2006-03-03 | 2007-09-05 | 精工爱普生株式会社 | Electronic substrate, semiconductor device, and electronic device |
| US20130140672A1 (en) * | 2011-03-29 | 2013-06-06 | Panasonic Corporation | Variable inductor and semiconductor device using same |
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