CN203423170U - Surface-mounted inductive device adopting wafer-level production technology - Google Patents
Surface-mounted inductive device adopting wafer-level production technology Download PDFInfo
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- CN203423170U CN203423170U CN201320492281.8U CN201320492281U CN203423170U CN 203423170 U CN203423170 U CN 203423170U CN 201320492281 U CN201320492281 U CN 201320492281U CN 203423170 U CN203423170 U CN 203423170U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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Abstract
The utility model relates to a surface-mounted inductive device adopting a wafer-level production technology, belonging to the field of passive device production. The device comprises a substrate (110), more than one metal wiring layers (200) forming an inductive structure of a central inductive coil area, and electrodes (300) of electrode areas on two sides. Different metal wiring layers (200) are electrically connected by dielectric layer through holes (401). A metal wiring layer I (210) and a metal wiring layer II (220) in the metal wiring layers (200) extend towards the electrode areas on two sides, and connected with the electrodes (300) at the same altitude on two sides, respectively. The surface of the topmost metal wiring layer (200) is covered by a surface protection layer (500), and is provided with a surface protection layer opening (501). The surface protection layer opening (501) has a rectangular cross section, and internally provided with an electrode terminal (600). The surface-mounted inductive device provided by the utility model has improvement in induction precision, reduction in thickness and increase in reliability, and overcomes the defect of single-side upwarp of surface mounting, thereby achieving high-density mounting.
Description
Technical field
The utility model relates to a kind of surface mount inductance component that adopts wafer level manufacture craft, belongs to passive device and manufactures field.
background technology
Inductance is requisite components and parts in electronic installation, and along with the trend of the hand-hold electronic device miniaturizations such as electronic installation especially mobile phone, inductor size is also more and more less.At present, wireless telecommunications mainly contain 0201 size and 0402 size (English system) by radio frequency inductive model, and wherein, the packaging body length of 0201 size model is between 500 microns to 700 microns, width is between 250 microns to 350 microns, and height is between 250 microns to 350 microns; The packaging body length of 0402 size model is between 900 microns to 1100 microns, and width is between 400 microns to 600 microns, and height is between 450 microns to 550 microns.Traditional inductance is to be mainly made by multilayer LTCC technique (LTCC technique), and its profile as shown in Figure 1.In this induction structure, its two ends are enclosed with conductive electrode, by surface mount process, install in the circuit board, and in the reflux course of assembling, scolding tin can be climbed to the sidewall of electrode, as shown in figure as left in Fig. 2 under the driving of wetting power.As shown in figure as right in Fig. 2, along with inductance component constantly dwindles, himself weight is also more and more lighter, if the wetting power imbalance of inductance two electrodes and scolding tin will cause the perk of inductance one end in surface mount process, cause assembly failure, greatly reduce assembling yield.In addition, because scolding tin can be climbed electrode sidewall, if during assembling two inductance from too close to be just easy to occur scolding tin crossover, therefore when designed lines plate, the distance of two devices need to be pulled open, so just lost board area, can not realize high density and mount.
In LTCC technique, in order to form the metallic circuit of inductance coil, be that mode by printing-sintering forms, due to typography capabilities limits, metallic circuit dimensional accuracy is not high, also cannot realize the printing of narrow pitch circuit, therefore its precision of inductance that adopts this technique to make is lower, and its precision of inductance that is conventionally less than 4nH can only reach +/-0.3nH, cannot meet the demand of efficient radio frequency system.In addition, as shown in Figure 3, adopt the inductance of LTCC technique to be generally sandwich construction, circuit is distributed in the whole thickness range of inductance, is therefore difficult to realize Ultrathin packaging.
Summary of the invention
From the above, the purpose of this utility model is to overcome the deficiency of above-mentioned traditional ceramics inductance component, provides that a kind of inductance precision is higher, thickness is thinner, reliability is higher, can overcome the surface mount inductance component that mounts one-sided perk defect, realizes the employing wafer level manufacture craft that high density mounts.
the purpose of this utility model is achieved in that
A surface mount inductance component for wafer level manufacture craft, its central authorities are inductance coil region, the top layer of both sides is electrode zone,
A kind of surface mount inductance component that adopts wafer level manufacture craft, comprise substrate, the above metal wiring layer of induction structure and the electrode of both sides electrode zone that forms central inductance coil region of one deck, the height of the described electrode of both sides equates, dielectric layer and dielectric layer through hole are set between different described metal wiring layers and form dielectric layer opening figure, between different metal wiring layers, by described dielectric layer through hole, be electrically connected, wherein two-layer described metal wiring layer is respectively metal wiring layer I and metal wiring layer II, described metal wiring layer I and metal wiring layer II are extended to both sides electrode zone respectively, and be connected with the electrode of both sides respectively, described metal wiring layer II is arranged at the top of metal wiring layer I, at the superiors' metal wiring layer surface coverage sealer, and sealer opening is set, the cross section of described sealer opening is rectangular, the electrode terminal being connected with electrode is set in it, the height of described electrode terminal equates, and be not less than the height of metal wiring layer and sealer thereof.
Further, the size of described sealer opening is not more than the size of electrode.
Further, at electrode zone, the extension that described electrode is metal wiring layer.
Further, between described substrate and metal wiring layer, passivation layer is set.
Further, in inductance coil region, described metal wiring layer in the shape of a spiral or strip.
Further, described metal wiring layer I is connected with electrode with after electrode sustained height by bending with metal wiring layer II.
Further, described electrode terminal comprises the scolding tin cap on projection and projection top or comprises projection and the projection protective layer that is coated on lug surface.
Further, the above size in the projection of described electrode terminal middle part is greater than the size of sealer opening.
Further, the height of described electrode terminal is no more than 20 microns.
Further, reduced thickness to 100～200 micron of described surface mount inductance component.
Above metal wiring layer and passivation layer be all adopt wafer level again Wiring technique on the substrate of High Resistivity Si, pottery or glass wafer, by techniques such as wafer level photoetching, plating, form, after completing above-mentioned wiring and passivation technology, again wafer attenuate is cut, form single surface mount inductance component.
the beneficial effects of the utility model are:
1, during being connected of surface mount inductance component of the present utility model and circuit board, electrode zone is positioned at the top layer of inductance component, scolding tin used can not climbed on the sidewall of inductance component, therefore when carrying out surface mount, there will not be the bad phenomenon of one end perk, can reduce two distances between device simultaneously, promote wiring board utilance, realize high density and mount;
2, the present invention adopts the wafer scale technique such as Wiring technique, plating again, compares with existing product, and the thickness of surface mount inductance component of the present invention all can be thinned to 100～200 microns, forms ultra-thin surface mount inductance component;
3, metal wiring layer adopts photoetching process to make, and precision is high, thereby promotes inductance precision, for its precision of inductance that is less than 4nH, can control to +/-0.1nH.
Accompanying drawing explanation
Fig. 1 is the 3-D view of traditional ceramics inductor;
Fig. 2 is traditional inductor normal and contrast schematic diagram that single-ended perk is bad while mounting wiring board;
Fig. 3 is the 3-D view of the internal structure of traditional inductor;
Fig. 4 is a kind of schematic diagram that adopts the surface mount inductance component of wafer level manufacture craft of the utility model;
Fig. 5 is the cutaway view (embodiment mono-) of the A-A of Fig. 4;
Fig. 6 is the cutaway view (embodiment bis-) of the A-A of Fig. 4;
Wherein:
Metal wiring layer 200
Metal wiring layer I 210
Metal wiring layer II 220
Electrode 300
Dielectric layer through hole 401
Dielectric layer opening figure 410
Sealer opening 501
Electrode terminal 600
Projection protective layer 603
Embodiment
Referring to Fig. 4 to Fig. 7, a kind of surface mount inductance component that adopts wafer level manufacture craft of the utility model, its central authorities are inductance coil region, the top layer of the both sides in inductance coil region is electrode zone.This surface mount inductance component comprises that substrate 110, one deck form the metal wiring layer 200 of induction structure and the electrode 300 of both sides electrode zone in central inductance coil region above, and described substrate 110 can be silicon, glass or pottery etc.
Wherein two-layer metal wiring layer I 210 and the metal wiring layer II 220 of being respectively of metal wiring layer 200, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, metal wiring layer II 220 in the shape of a spiral, metal wiring layer I 210 is strip, as shown in Figure 4, metal wiring layer I 210 and metal wiring layer II 220 also can all be strip in the shape of a spiral or all.
Metal wiring layer I 210 is connected with the electrode 300 of both sides equal altitudes respectively with metal wiring layer II 220, and metal wiring layer I 210 all can be connected with electrode 300 with after electrode 300 sustained heights by bending with metal wiring layer II 220.In Fig. 5, illustrate, metal wiring layer I 210 is contour with electrode 300, and is all arranged at the below of metal wiring layer II 220.Metal wiring layer I 210 is directly connected with electrode 300, after highly equating, is connected with electrode 300 after metal wiring layer II 220 downward bendings with electrode 300.At the superiors' metal wiring layer 200 surface coverage sealers 500; and sealer opening 501 is set; the cross section of described sealer opening 501 is rectangular; the electrode terminal 600 being connected with electrode 300 is set in it; the size of sealer opening 501 is not more than the size of electrode 300; for making to mount convenience, electrode 300 and circuit board, mount firmly, sealer opening 501 should be large as far as possible.The height of described electrode terminal 600 equates, and is not less than the height of metal wiring layer 200 and sealer 500 thereof.
Embodiment mono-
Referring to Fig. 4 and Fig. 5, a kind of surface mount inductance component that adopts wafer level manufacture craft of the utility model, metal wiring layer 200 is arranged at the surface of substrate 110, in Fig. 5, metal wiring layer 200 take only illustrate metal wiring layer I 210 and metal wiring layer II 220 two-layer be example, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, and the two connects by dielectric layer through hole 401, realizes electrical communication.Metal wiring layer I 210 and metal wiring layer II 220 are extended to both sides electrode zone respectively, and are connected with the electrode 300 of the equal altitudes of both sides respectively.If desired, metal wiring layer I 210 can be connected with electrode 300 after bending with metal wiring layer II 220.The electrode terminal 600 of sealer opening 501 interior settings comprises the scolding tin cap 602 on projection 601 and projection 601 tops.The cross section of described projection 601 can be strip, and can be the multi-layer metal structure of the compositions such as copper, nickel, and can be multi-layer metal structure.The projection 601 above sizes in middle part of described electrode terminal 600 are greater than the size of sealer opening 501, to improve the heat resistanceheat resistant moisture resistance of inductance component.The height of described electrode terminal 600 is no more than 20 microns, to realize ultra-thin surface mount inductance component.
Embodiment bis-
Referring to Fig. 4 and Fig. 6, a kind of surface mount inductance component that adopts wafer level manufacture craft of the utility model, as follows with embodiment mono-difference, between substrate 110 and metal wiring layer 200, also passivation layer 700 can be set, to improve the reliability of inductance component.In Fig. 6, metal wiring layer 200 take only illustrate metal wiring layer I 210 and metal wiring layer II 220 two-layer be example, metal wiring layer II 220 is arranged at the top of metal wiring layer I 210, the two connects by dielectric layer through hole 401, realizes electrical communication.Metal wiring layer I 210 and metal wiring layer II 220 are extended to both sides electrode zone respectively, and are connected with the electrode 300 of the equal altitudes of both sides respectively.The electrode terminal 600 of sealer opening 501 interior settings comprises projection 601 and is coated on the projection protective layer 603 on projection 601 surfaces.The cross section of described projection 601 can be strip, and can be the multi-layer metal structure of the compositions such as copper, nickel, and can be multi-layer metal structure.The described projection 601 above sizes in middle part are greater than sealer opening 501, to improve the heat resistanceheat resistant moisture resistance of inductance component.The height of described electrode terminal 600 is not less than the height of metal wiring layer 200 and sealer 500 thereof and is no more than 20 microns.
At electrode zone, electrode 300 of the present utility model can be also the extension of metal wiring layer 200, the identical function being connected of 200 electrodes 300 of this metal wiring layer and circuit board.
In an embodiment, follow-up while being connected with circuit board for making, mount operation smooth, highly needs are equal to play the metal wiring layer that is connected said function 200 of electrode 300 and circuit board, and its implementation is as follows:
One, metal wiring layer II 220 to the left and right both direction extend, made electrode 300 highly identical with the metal wiring layer II 220 of the connection said function of circuit board, make that follow-up to mount operation smooth;
Two, the metal wiring layer I 210 being connected with circuit board and/or metal wiring layer II 220 can be connected with circuit board to sustained height in bending again.
Surface mount inductance component of the present utility model, adopts the wafer scale manufacture craft that connects up again, finally forms 0201 size model and 0402 size model.Compare with existing product, the thickness of above two kinds of surface mount inductance components all can be thinned to 100～200 microns, forms ultra-thin surface mount inductance component.
Metal wiring layer 200 of the present utility model and dielectric layer 400, sealer 500, passivation layer 700 be all adopt wafer level again Wiring technique on the substrate 110 of High Resistivity Si, pottery or glass wafer, by techniques such as wafer level photoetching, plating, form; improved the dimensional accuracy of metal wiring layer 200; thereby promoted inductance precision; for its precision of inductance that is less than 4nH, can control to +/-0.1nH; after completing above-mentioned wiring and passivation technology, again wafer attenuate is cut, form the surface mount inductance component of single.
Claims (10)
1. adopt a surface mount inductance component for wafer level manufacture craft, its central authorities are inductance coil region, and the top layer of both sides is electrode zone,
It is characterized in that: comprise substrate (110), the above metal wiring layer (200) of induction structure and the electrode (300) of both sides electrode zone that forms central inductance coil region of one deck, the height of the described electrode (300) of both sides equates, dielectric layer (400) and dielectric layer through hole (401) are set between different described metal wiring layers (200) and form dielectric layer opening figure (410), between different metal wiring layer (200), by described dielectric layer through hole (401), be electrically connected, wherein two-layer described metal wiring layer (200) is respectively metal wiring layer I (210) and metal wiring layer II (220), described metal wiring layer I (210) and metal wiring layer II (220) are extended to both sides electrode zone respectively, and be connected with the electrode (300) of both sides respectively, described metal wiring layer II (220) is arranged at the top of metal wiring layer I (210), at the superiors' metal wiring layer (200) surface coverage sealer (500), and sealer opening (501) is set, the cross section of described sealer opening (501) is rectangular, the electrode terminal (600) being connected with electrode (300) is set in it, the height of described electrode terminal (600) equates, and be not less than the height of metal wiring layer (200) and sealer (500) thereof.
2. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 1, is characterized in that: the size of described sealer opening (501) is not more than the size of electrode (300).
3. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 1 and 2, is characterized in that: at electrode zone, described electrode (300) is the extension of metal wiring layer (200).
4. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 1, is characterized in that: between described substrate (110) and metal wiring layer (200), passivation layer (700) is set.
5. according to a kind of surface mount inductance component that adopts wafer level manufacture craft described in claim 1 or 4, it is characterized in that: in inductance coil region, described metal wiring layer (200) in the shape of a spiral or strip.
6. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 1, is characterized in that: described metal wiring layer I (210) is connected with electrode (300) with after electrode (300) sustained height by bending with metal wiring layer II (220).
7. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 1, is characterized in that: described electrode terminal (600) comprises the scolding tin cap (602) on projection (601) and projection (601) top or comprises projection (601) and be coated on the surperficial projection protective layer (603) of projection (601).
8. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 7, is characterized in that: the above size in projection (601) middle part of described electrode terminal (600) is greater than the size of sealer opening (501).
9. according to a kind of surface mount inductance component that adopts wafer level manufacture craft described in claim 7 or 8, it is characterized in that: the height of described electrode terminal (600) is no more than 20 microns.
10. a kind of surface mount inductance component that adopts wafer level manufacture craft according to claim 1, is characterized in that: reduced thickness to 100～200 micron of described surface mount inductance component.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320492281.8U CN203423170U (en) | 2013-08-13 | 2013-08-13 | Surface-mounted inductive device adopting wafer-level production technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320492281.8U CN203423170U (en) | 2013-08-13 | 2013-08-13 | Surface-mounted inductive device adopting wafer-level production technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203423170U true CN203423170U (en) | 2014-02-05 |
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ID=50022261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320492281.8U Expired - Lifetime CN203423170U (en) | 2013-08-13 | 2013-08-13 | Surface-mounted inductive device adopting wafer-level production technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203423170U (en) |
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2013
- 2013-08-13 CN CN201320492281.8U patent/CN203423170U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140205 |