CN103400776A - Packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and process method thereof - Google Patents
Packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and process method thereof Download PDFInfo
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- CN103400776A CN103400776A CN2013103409171A CN201310340917A CN103400776A CN 103400776 A CN103400776 A CN 103400776A CN 2013103409171 A CN2013103409171 A CN 2013103409171A CN 201310340917 A CN201310340917 A CN 201310340917A CN 103400776 A CN103400776 A CN 103400776A
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- photoresistance film
- metal substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Electroplating Methods And Accessories (AREA)
Abstract
The invention relates to a packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and a process method thereof. The structure comprises a pad and pins, wherein a first chip is arranged on the front surface of the pad; second chips are flipped on the back surfaces of the pad and the pins through bottom filling adhesives; the front surfaces of the first chip and the pins are connected through metal wires; conductive columns are arranged on the front surfaces of the pins; molding compounds are encapsulated in the peripheral area of the pad, the areas between the pad and the pins and between each two pins, the upper areas of the pad and the pins, the lower areas of the pad and the pins, and the external areas of the first chip, the second chips, the metal wires and the conductive columns; and anti-oxidation layers are plated on the surfaces, exposed from the molding compounds, of the pins and the conductive columns. By virtue of the packaging-prior-to-etching type three-dimensional system-level chip-flipped packaging structure and the process method thereof, the problem of limitation of the functionality and application performance of a metal lead frame caused by difficulty in embedding of an object into a conventional metal lead frame can be solved.
Description
Technical field
After the present invention relates to a kind of first erosion, inside back cover maintains irrespective of size flip chip encapsulation structure and process.Belong to the semiconductor packaging field.
Background technology
Tradition four sides without pin die-attach area encapsulating structure as shown in Figure 79, its main manufacture craft is that sheet metal carries out chemical etching, thereby metal plating is made the Ji Dao of carries chips, the die-attach area of inside and outside pin getting, then carries out one-sided load, routing on this basis, the packaging technology such as seals.
And traditional organic multilayer circuit base plate encapsulating structure is as shown in Figure 80, its main technique is by amassing into mode that material the amasss formation multilayer circuit board that superposes on the basis of glass mat core material, pass through the mode perforate of laser drill between line layer, then plate hole and complete electric connection.And then carry out one-sided load, routing on the basis of multilayer circuit board, the packaging technology such as seal.
Above-mentioned tradition four sides all has the following disadvantages without pin die-attach area encapsulating structure and organic multilayer circuit base plate encapsulating structure:
1, this type of die-attach area and multilayer wiring board all can only carry out one-sided chip package, and the utilance of die-attach area or multilayer wiring board is lower, thereby limit the functional integration of whole encapsulation.
2, this type of die-attach area and multilayer wiring board itself do not imbedded any object, so traditional metal lead frame and organic multilayer wiring board do not possess the function integrated result, thereby correspondingly limited the functional integration of whole packaging body yet.
3, the material cost of organic multilayer substrate and technique cost of manufacture are higher.
4, the live width line-spacing of traditional metal lead frame is considerably large, more than at least all wanting 100 μ m, so can't accomplish highdensity demand.
5, the live width line-spacing of traditional organic multilayer circuit is made ability according to present etching, can only reach 25 μ m live widths and 25 μ m line-spacings, and is a bit wide a little.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of erosion chip formal dress three-dimensional system level packaging structure and process of first being honored as a queen is provided, and it can solve that traditional metal lead frame or multilayer wiring board itself can't be imbedded chip and passive component and the problem and the traditional organic substrate that limit whole encapsulation function integrated level needs wider Yu narrower line and the distance between centers of tracks of fine rule.
The object of the present invention is achieved like this: after a kind of first erosion, inside back cover maintains the process of irrespective of size flip-chip encapsulation, and described method comprises the steps:
In the metal substrate front of completing the little copper layer of preplating and the back side stick respectively the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 4, the metal substrate back side
Utilize exposure imaging equipment that step 3 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Electroplate the metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 4;
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 5;
Part photoresistance film is removed at step 7, the metal substrate back side
Utilize exposure imaging equipment that step 6 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Electroplate the high-conductive metal line layer in the zone of metal substrate back side removal part photoresistance film in step 7, form corresponding Ji Dao and pin;
Remove the photoresistance film of metallic substrate surfaces;
Utilize epoxide resin material to carry out the plastic packaging protection on the metallic circuit layer surface at the metal substrate back side;
Carrying out epoxy resin surface after completing the epoxy resin plastic packaging grinds;
Metal substrate front and back at completing steps 11 sticks the photoresistance film that can carry out exposure imaging;
Utilize exposure imaging equipment that step 12 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the positive follow-up needs of metal substrate, carry out etched regional graphics;
Metal substrate front in step 13 is completed the zone of exposure imaging and carry out chemical etching;
Step 15, the operation of subsides photoresistance film
Metal substrate front and back at completing steps 14 sticks the photoresistance film that can carry out exposure imaging;
Utilize exposure imaging equipment that step 15 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate;
Electroplate the metal pillar in the zone of the positive removal of metal substrate part photoresistance film in step 10 six;
Remove the photoresistance film of metallic substrate surfaces;
At basic island front surface coated conduction or the non-conductive bonding material that step 8 forms;
Implant the first chip on the conduction of step 10 nine or non-conductive bonding material;
Carry out the operation of bonding metal wire between the first chip front side and pin front;
The positive plastic packaging material that adopts of metal substrate in step 2 11 is carried out plastic packaging;
Carrying out epoxy resin surface after the epoxy resin plastic packaging of completing steps 22 grinds;
The exposed metal of metallic substrate surfaces after completing steps 23 is electroplated anti-oxidant metal layer or is criticized and covers antioxidant (OSP).
The Ji Dao of step 2 14 and the pin back side is filled up between Metal Ball and Metal Ball by underfill and chip and Ji Dao, pin between space upside-down mounting the second chip.
Adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 2 15.
after a kind of first erosion, inside back cover maintains the irrespective of size flip chip encapsulation structure, it comprises Ji Dao and pin, the first chip just is being equipped with by conduction or non-conductive material in front at described Ji Dao, there is the second chip at the back side at described Ji Dao and pin by the underfill upside-down mounting, be connected with metal wire between the front of described the first chip and the front of pin, be provided with conductive posts in described pin front, the zone of periphery, described basic island, zone between Ji Dao and pin, zone between pin and pin, the zone on Ji Dao and pin top, zone and the first chip and second chip of Ji Dao and pin bottom, metal wire and conductive posts all are encapsulated with plastic packaging material outward, described plastic packaging material flushes with the top of conductive posts, the surface of exposing plastic packaging material in described conductive posts is coated with anti oxidation layer or coating antioxidant.
By conduction bonding material cross-over connection passive device, described passive device is connected across between the pin back side and the pin back side, between the pin back side and the Ji Dao back side, between the pin back side and the static release ring back side and between the static release ring back side and the Ji Dao back side between described pin and pin, between pin and basic island, between pin and static release ring and between static release ring and basic island.
Described Ji Dao and the pin back side fill up between Metal Ball and Metal Ball by underfill and chip and Ji Dao, chip between the space upside-down mounting a plurality of the second chips are arranged
Be provided with the 3rd chip at described the second chip back by conduction or non-conductive bonding material, be connected by metal wire between described the 3rd chip front side and the pin back side.
By the Metal Ball upside-down mounting, the 3rd chip is arranged at the described pin back side, described Metal Ball and the 3rd chip are in the inside of plastic packaging material.
By the Metal Ball upside-down mounting, passive device is arranged at the described pin back side, described Metal Ball and passive device are in the inside of plastic packaging material.
After a kind of first erosion, inside back cover maintains the process of irrespective of size flip-chip encapsulation, and described method comprises the steps:
In the metal substrate front of completing the little copper layer of preplating and the back side stick respectively the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 4, the metal substrate back side
Utilize exposure imaging equipment that step 3 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Electroplate the first metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 4;
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 5;
Part photoresistance film is removed at step 7, the metal substrate back side
Utilize exposure imaging equipment that step 6 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Electroplate the second metallic circuit layer conduct in order to connect the conductive posts of the first metallic circuit layer and the 3rd metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 7;
Remove the photoresistance film of metallic substrate surfaces;
At the non-conductive glued membrane of metal substrate back side pressing one deck;
Carry out surface grinding after completing non-conductive glued membrane pressing;
To the preliminary treatment of metallizing of non-conductive glued membrane surface;
The metal substrate front and back sticks the photoresistance film that can carry out exposure imaging in step 12;
Part photoresistance film is removed at step 14, the metal substrate back side
Utilize exposure imaging equipment that step 13 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the follow-up needs in the metal substrate back side, carry out etched regional graphics;
Step 15, etching operation
Carry out the etching operation in the zone that step 14 is completed after the photoresistance film is windowed;
The photoresistance film is removed at step 10 six, the metal substrate back side
Remove the photoresistance film at the metal substrate back side, the metallic region figure that is plated to expose follow-up needs;
Carry out the plating work of the 3rd metallic circuit layer at the metal substrate back side of step 10 six;
Stick the photoresistance film that can carry out exposure imaging at the metal substrate back side of step 10 seven;
Part photoresistance film is removed at step 10 nine, the metal substrate back side
Utilize exposure imaging equipment that step 10 eight is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Electroplate the 4th metallic circuit layer as belong to the conductive posts of line layer in order to connect the 3rd metallic circuit layer and five metals in the zone of metal substrate back side removal part photoresistance film in step 10 nine;
Remove the photoresistance film of metallic substrate surfaces;
At the non-conductive glued membrane of metal substrate back side pressing one deck;
Carry out surface grinding after completing non-conductive glued membrane pressing;
To the preliminary treatment of metallizing of non-conductive glued membrane surface;
The metal substrate front and back sticks the photoresistance film that can carry out exposure imaging in step 2 14;
Part photoresistance film is removed at step 2 16, the metal substrate back side
Utilize exposure imaging equipment that step 2 15 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the follow-up needs in the metal substrate back side, carry out etched regional graphics; Step 2 17, etching operation
Carry out the etching operation in the zone that step 2 16 is completed after the photoresistance film is windowed;
The photoresistance film is removed at step 2 18, the metal substrate back side
Remove the photoresistance film at the metal substrate back side;
Carry out five metals at the metal substrate back side of step 2 18 and belong to the plating work of line layer, five metals belongs to line layer and electroplates after completing namely form corresponding Ji Dao and pin on metal substrate;
The photoresistance film that can carry out exposure imaging is sticked in the metal substrate front in step 2 19;
Utilize exposure imaging equipment that step 3 ten is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the positive follow-up needs of metal substrate, carry out etched regional graphics;
Metal substrate front in step 3 11 is completed the zone of exposure imaging and carry out chemical etching, chemical etching is until the metallic circuit layer;
Complete the metal substrate front of chemical etching and stick the photoresistance film that can carry out exposure imaging in step 3 12;
Utilize exposure imaging equipment that step 3 13 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate;
Electroplate the metal pillar in the zone of the positive removal of metal substrate part photoresistance film in step 3 14;
Remove the photoresistance film of metallic substrate surfaces;
At the basic island of completing steps 36 front surface coated conduction or non-conductive bonding material;
Implant the first chip on the conduction of step 3 17 or non-conductive bonding material;
Carry out the operation of bonding metal wire between chip front side and pin front;
The positive epoxy resin (being commonly called as plastic packaging material) that adopts of metal substrate in step 3 19 is carried out plastic packaging;
Carrying out epoxy resin surface after the epoxy resin plastic packaging of completing steps 40 grinds;
The exposed metal of metallic substrate surfaces after completing steps 41 is electroplated anti-oxidant metal layer or is criticized and covers antioxidant (OSP).
The Ji Dao of step 4 12 and the pin back side is filled up between Metal Ball and Metal Ball by underfill and chip and Ji Dao, chip between space carry out upside-down mounting the second chip.
Adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 4 13.
But described step 6, to step 10 seven repetitive operations, forms more multi-layered metallic circuit layer.
Compared with prior art, the present invention has following beneficial effect:
1, metal current lead frame or organic multilayer circuit base plate all can't be imbedded object, thereby have limited the functional integration of whole encapsulation.And three-dimensional systematic metallic circuit substrate of the present invention, three-dimensional systematic metallic circuit substrate can be imbedded object in manufacturing process again in the interlayer in the middle of substrate, thereby realize loading chip or other assemblies in the both sides of three-dimensional systematic metallic circuit substrate substrate, thereby promoted the functional integration of whole encapsulation;
2, the interlayer in three-dimensional systematic metallic circuit substrate can be because heat conduction or heat radiation need in manufacturing process be imbedded heat conduction or heat radiation object in the position of needs or zone, thereby improves the radiating effect of whole encapsulating structure;
3, the interlayer in three-dimensional systematic metallic circuit substrate can be because of the needs of system and function in manufacturing process be imbedded active member or assembly or passive assembly in the position of needs or zone, thereby has improved the utilance of substrate;
4, can't see the inner interlayer of substrate fully from the outward appearance of three-dimensional systematic metallic circuit substrate package finished product has imbedded because of system or the object of function needs, especially the imbedding X-ray and all can't inspect of the chip of silicon material, fully reach confidentiality and the protectiveness of system and function;
5, the systemic-function integrated of three-dimensional systematic metallic circuit substrate package is many, thereby the component module of said function shared space on PCB is just fewer, thereby has also just reduced cost.
6, the interlayer of three-dimensional systematic metallic circuit substrate can be imbedded high-power component in manufacturing process, with control chip, is contained in respectively the substrate both sides, thereby can avoid the high-power component heat radiation and the signal transmission of interference control chip.
7, three-dimensional systematic metallic circuit substrate adopts plating mode to make circuit, and the live width line-spacing can reach below 15 μ m.
8, three-dimensional systematic metallic circuit substrate adopts plating, etching and plastic package process to make, and technique is simple, and cost is than low 30% left and right of organic substrate.
Description of drawings
Fig. 1 ~ Figure 27 is that the present invention first loses rear inside back cover and maintains each operation schematic diagram of irrespective of size flip-chip packaging process.
Figure 28 is that the present invention first loses rear inside back cover and maintains the schematic diagram of irrespective of size flip chip encapsulation structure embodiment 1.
Figure 29 is that the present invention first loses rear inside back cover and maintains the schematic diagram of irrespective of size flip chip encapsulation structure embodiment 2.
Figure 30 is that the present invention first loses rear inside back cover and maintains the schematic diagram of irrespective of size flip chip encapsulation structure embodiment 3.
Figure 31 is that the present invention first loses rear inside back cover and maintains the schematic diagram of irrespective of size flip chip encapsulation structure embodiment 4.
Figure 32 is that the present invention first loses rear inside back cover and maintains the schematic diagram of irrespective of size flip chip encapsulation structure embodiment 5.
Figure 33 ~ Figure 77 is that the present invention first loses rear inside back cover and maintains the process chart of irrespective of size flip chip encapsulation structure embodiment 6.
Figure 78 is that the present invention first loses rear inside back cover and maintains the schematic diagram of irrespective of size flip chip encapsulation structure embodiment 6.
Figure 79 is the schematic diagram of tradition four sides without pin die-attach area encapsulating structure.
Figure 80 is the schematic diagram of traditional organic multilayer circuit base plate encapsulating structure.
Wherein:
Conduction or non-conductive bonding material 3
The first chip 4
The second chip 6
Anti oxidation layer or batch cover antioxidant 10
The 3rd chip 12
Embodiment
The present invention a kind of first the erosion after inside back cover maintain the irrespective of size flip chip encapsulation structure and process as follows:
referring to Figure 28, for first losing rear inside back cover, the present invention maintains the structural representation of irrespective of size flip chip encapsulation structure embodiment 1, it comprises basic island 1 and pin 2, the first chip 4 just is being equipped with by conduction or non-conductive bonding material 3 in the front on described basic island 1, there is the second chip 6 at the back side at basic island 1 and pin 2 by underfill 5 upside-down mountings, be connected with metal wire 7 between the front of the front of described the first chip 4 and pin 2, be provided with conductive posts 8 in described pin 2 fronts, the zone of 1 periphery, described basic island, zone between base island 1 and pin 2, zone between pin 2 and pin 2, the zone on base island 1 and pin 2 tops, zone and first chip 4 of base island 1 and pin 2 bottoms, the second chip 6, the outer plastic packaging material 9 that all is encapsulated with of metal wire 7 and conductive posts 8, described plastic packaging material 9 flushes with the top of conductive posts 8, be coated with anti oxidation layer on the surface that described conductive posts 7 is exposed plastic packaging material 9 or criticize and cover antioxidant (OSP) 10.
Its process is as follows:
Referring to Fig. 1, get the suitable metal substrate of a slice thickness, the purpose that this sheet material uses is just made with follow-up encapsulation and is supported the transitional material that the line layer structure is used as circuit, the material of this sheet material is mainly take metal material as main, and the metallics of the material of metal material can be the zinc-plated Cai ﹑ of Tong Cai ﹑ Tie Cai ﹑ Bu rust Gang Cai ﹑ aluminium maybe can reach conducting function or non-all-metal material etc.
Referring to Fig. 2, at the little copper layer of metallic substrate surfaces preplating, little copper layer thickness is at 2 ~ 10 microns, needing also according to function can attenuate or thicken, be mainly to make while for follow-up circuit, making line layer and the metal substrate can fluid-tight engagement, the mode of plating can adopt chemical deposition or metallide.
Referring to Fig. 3, in the metal substrate front of completing the little copper layer of preplating and the back side stick respectively the photoresistance film that can carry out exposure imaging, to protect follow-up electroplated metal layer process operation, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 4, the metal substrate back side
, referring to Fig. 4, utilize exposure imaging equipment that step 3 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side.
referring to Fig. 5, electroplate the metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 4, the metallic circuit layer material can be copper, aluminium, nickel, silver, gold, copper silver, the nickel gold, (common 5 ~ 20 microns of NiPdAus, can select different plating materials according to different application, the thickness of electroplating according to the different qualities conversion) material such as, certainly other metallics that can conduct electricity can use, do not limit to copper, aluminium, nickel, silver, gold, copper silver, the nickel gold, the metal materials such as NiPdAu, plating mode can be chemical deposition or metallide mode.
Referring to Fig. 6, the photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 5, and the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 7, the metal substrate back side
, referring to Fig. 7, utilize exposure imaging equipment that step 6 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side.
Referring to Fig. 8, electroplate the high-conductive metal line layer in the zone of metal substrate back side removal part photoresistance film in step 7, form corresponding Ji Dao and pin, the material of high-conductive metal line layer can be copper, aluminium, nickel, silver, gold, the materials such as copper is silver-colored, nickel is golden, NiPdAu, certainly other metallics that can conduct electricity can use, do not limit to copper, aluminium, nickel, silver, gold, the metal materials such as copper is silver-colored, nickel is golden, NiPdAu, plating mode can make chemical deposition or metallide mode.
Referring to Fig. 9, remove the photoresistance film of metallic substrate surfaces, the method for removing the photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove the photoresistance film.
Referring to Figure 10; metallic circuit layer and high-conductive metal line layer surface at the metal substrate back side utilize epoxide resin material to carry out the plastic packaging protection; epoxide resin material can be selected filler to be arranged or do not have Packed kind according to product performance, and the plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method, pad pasting mode or the mode of brush coating.
Referring to Figure 11, to carry out epoxy resin surface and grind after completing the epoxy resin plastic packaging, purpose is the thickness that high-conductive metal line layer that outer pin function is used exposes plastic-sealed body surface and control ring epoxy resins.
Referring to Figure 12, stick the photoresistance film that can carry out exposure imaging at the metal substrate front and back of completing steps 11, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Referring to Figure 13, utilize exposure imaging equipment that step 12 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, carry out etched regional graphics to expose the positive follow-up needs of metal substrate.
Referring to Figure 14, metal substrate front in step 13 to be completed the zone of exposure imaging and carry out chemical etching, chemical etching is until the metallic circuit layer, and etching solution can adopt copper chloride or iron chloride or the liquid medicine that can carry out chemical etching.
Step 15, the operation of subsides photoresistance film
Referring to Figure 15, stick the photoresistance film that can carry out exposure imaging at the metal substrate front and back of completing steps 14, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
, referring to Figure 16, utilize exposure imaging equipment that step 15 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate.
Referring to Figure 17, electroplate the metal pillar in the zone of the positive removal of metal substrate part photoresistance film in step 10 six, the material of metal pillar can be copper, aluminium, nickel, silver, gold, the materials such as copper is silver-colored, nickel is golden, NiPdAu, certainly other metallics that can conduct electricity can use, do not limit to copper, aluminium, nickel, silver, gold, the metal materials such as copper is silver-colored, nickel is golden, NiPdAu, plating mode can be chemical deposition or metallide mode.
Referring to Figure 18, remove the photoresistance film of metallic substrate surfaces, the method for removing the photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove the photoresistance film.
Referring to Figure 19, at the basic island of step 10 eight front surface coated conduction or non-conductive bonding material, purpose be for after follow-up implanted chip with the engaging of Ji Dao.
, referring to Figure 20, implant the first chip on the conduction of step 10 nine or non-conductive bonding material.
Referring to Figure 21, carry out the operation of bonding metal wire between the first chip front side and pin front, the material of described metal wire adopts gold, silver, copper, aluminium or the material of alloy, shape wiry can be thread can be also banded.
Referring to Figure 22, the positive plastic packaging material that adopts of metal substrate in step 2 11 is carried out plastic packaging, the plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method or use the pad pasting mode, and described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Referring to Figure 23, to carry out epoxy resin surface and grind after the epoxy resin plastic packaging of completing steps 22, purpose is to make the metal pillar expose the thickness of plastic-sealed body surface and control ring epoxy resins.
Referring to Figure 24, the exposed metal of the metallic substrate surfaces after completing steps 23 is electroplated anti-oxidant metal layer, prevents burning, as gold, golden, the NiPdAu of nickel, tin or coating antioxidant (OSP).
Referring to Figure 25, the Ji Dao of step 2 14 and the pin back side is filled up between Metal Ball and Metal Ball by underfill and chip and Ji Dao, basic island between space after upside-down mounting the second chip, after the mode of upside-down mounting can be coated in underfill on Ji Dao and pin in upside-down mounting again the second chip or underfill is coated in the second chip front side, upside-down mounting is in Ji Dao and the pin back side.
Referring to Figure 26, adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 2 15, the plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method or use the pad pasting mode, and described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Referring to Figure 27, step 2 16 is completed the semi-finished product of sealing carry out cutting operation, make and originally in array aggregate mode, integrate and to contain more than cuttings of plastic-sealed body module of chip independent, after making first erosion, inside back cover maintains the irrespective of size flip chip encapsulation structure, can adopt conventional diamond blade and conventional cutting equipment to get final product.
referring to Figure 29, for first losing rear inside back cover, the present invention maintains the structural representation of irrespective of size flip chip encapsulation structure embodiment 2, embodiment 2 is with the difference of embodiment 1: described conductive posts 8 has multi-turn, pass through conduction bonding material cross-over connection passive device 11 between described pin 2 and pin 2, be provided with static release ring 14 between described basic island 1 and pin 2, described passive device 11 can be connected across between pin 2 back sides and pin 2 fronts, or be connected across between pin 2 back sides and static release ring 14 back sides, or be connected across between 1 back side, basic island and static release ring 14 back sides.
Referring to Figure 30, maintain the structural representation of irrespective of size flip chip encapsulation structure embodiment 3 for the present invention first loses rear inside back cover, embodiment 3 is with the difference of embodiment 1: there are a plurality of the second chips 6 at the back side at described basic island 1 and pin 2 by underfill 5 upside-down mountings.
Referring to Figure 31, for first losing rear inside back cover, the present invention maintains the structural representation of irrespective of size flip chip encapsulation structure embodiment 4, embodiment 4 is with the difference of embodiment 1: be provided with the 3rd chip 12 at described second chip 6 back sides by conduction or non-conductive bonding material 3, be connected by metal wire 7 between described the 3rd chip 12 fronts and pin 2.
Referring to Figure 32, for first losing rear inside back cover, the present invention maintains the structural representation of irrespective of size flip chip encapsulation structure embodiment 5, embodiment 5 is with the difference of embodiment 1: at described pin 2 back sides, be provided with Metal Ball 13, upside-down mounting has the 3rd chip 12 on described Metal Ball 13, and described Metal Ball 13 and the 3rd chip 12 are in the inside of plastic packaging material 9.
Referring to Figure 78, for first losing rear inside back cover, the present invention maintains the structural representation of irrespective of size flip chip encapsulation structure embodiment 7, embodiment 7 is with the difference of embodiment 1: described basic island 1 or pin 2 comprise the multiple layer metal line layer, be connected by conductive posts between adjacent two layers metallic circuit layer, the front and back on described basic island 1 is provided with the first chip 4 and the second chip 5 by conduction or non-conductive bonding material 3 respectively, at described pin 2 back sides, is provided with conductive posts 7.
Its process is as follows:
Referring to Figure 33, get the suitable metal substrate of a slice thickness, the purpose that this sheet material uses is just made with follow-up encapsulation and is supported the transitional material that the line layer structure is used as circuit, the material of this sheet material is mainly take metal material as main, and the metallics of the material of metal material can be the zinc-plated Cai ﹑ of Tong Cai ﹑ Tie Cai ﹑ Bu rust Gang Cai ﹑ aluminium maybe can reach conducting function or nonmetallic substance etc.
Referring to Figure 34, at the little copper layer of metallic substrate surfaces preplating, little copper layer thickness is at 2 ~ 10 microns, needing also according to function can attenuate or thicken, be mainly to make while for follow-up circuit, making line layer and the metal substrate can fluid-tight engagement, the mode of plating can adopt chemical deposition or metallide.
Referring to Figure 35, in the metal substrate front of completing the little copper layer of preplating and the back side stick respectively the photoresistance film that can carry out exposure imaging, to protect follow-up electroplated metal layer process operation, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 4, the metal substrate back side
, referring to Figure 36, utilize exposure imaging equipment that step 3 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side.
referring to Figure 37, electroplate the first metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 4, the first metallic circuit layer material can be copper, aluminium, nickel, silver, gold, copper silver, the nickel gold, (common 5 ~ 20 microns of NiPdAus, can select different plating materials according to different application, the thickness of electroplating according to the different qualities conversion) material such as, certainly other metallics that can conduct electricity can use, do not limit to copper, aluminium, nickel, silver, gold, copper silver, the nickel gold, the metal materials such as NiPdAu, plating mode can be chemical deposition or metallide mode.
Referring to Figure 38, the photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 5, and the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 7, the metal substrate back side
, referring to Figure 39, utilize exposure imaging equipment that step 6 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side.
Referring to Figure 40, electroplate the second metallic circuit layer conduct in order to connect the conductive posts of the first metallic circuit layer and the 3rd metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 7, the material of metallic circuit layer can adopt copper, nickel gold, NiPdAu, silver, gold or tin metal, and plating mode can make chemical deposition or metallide mode.
Referring to Figure 41, remove the photoresistance film of metallic substrate surfaces, purpose is to carry out non-conductive glued membrane operation for follow-up, the method for removing the photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove the photoresistance film.
referring to Figure 42, the non-conductive glued membrane of (zone that line layer is arranged) pressing one deck at the metal substrate back side, purpose is to insulate for the first metallic circuit layer and the 3rd metallic circuit layer, the mode of the non-conductive glued membrane of pressing can adopt conventional roll unit, or carry out pressing under the environment of vacuum, to prevent that the pressing process from producing the residual of air, non-conductive glued membrane is mainly thermosetting epoxy resin, and epoxy resin can not have filler or Packed non-conductive glued membrane according to the product performance employing, the color of epoxy resin can be according to the product performance processing of dyeing.
Referring to Figure 43, carry out surface grinding after completing non-conductive glued membrane pressing, purpose is to expose the second metallic circuit layer, keeps the evenness of non-conductive glued membrane and the second metallic circuit layer and the thickness of controlling non-conductive glued membrane.
Referring to Figure 44, to the preliminary treatment of metallizing of non-conductive glued membrane surface, make its surface attachment last layer metallization macromolecular material, purpose is the catalyst conversion that as subsequent metal material, can plate, and the adhesion metal macromolecular material can adopt spraying, plasma concussion, surface coarsening etc. to go to dry again and get final product;
Referring to Figure 45, the metal substrate front and back sticks the photoresistance film that can carry out exposure imaging in step 12, and to protect the electroplating technology operation of the 3rd follow-up metallic circuit layer, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 14, the metal substrate back side
Referring to Figure 46, utilize exposure imaging equipment that step 13 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, carry out etched regional graphics to expose the follow-up needs in the metal substrate back side.
Step 15, etching operation
Referring to Figure 47, carry out the etching operation in the zone that step 14 is completed after the photoresistance film is windowed, its objective is that the metallic region corrosion beyond the metallic circuit that will keep is clean, carrying out etching method can be copper chloride or iron chloride or the technology mode that can carry out the liquid medicine of chemical etching.
The photoresistance film is removed at step 10 six, the metal substrate back side
, referring to Figure 48, remove the photoresistance film at the metal substrate back side, the metallic region figure that is plated to expose follow-up needs.
Referring to Figure 49, carry out the plating work of the 3rd metallic circuit layer at the metal substrate back side of step 10 six, the material of the 3rd metallic circuit layer can be copper, nickel gold, NiPdAu, silver, gold or tin metal, and plating mode can be that chemical deposition adds metallide or all uses the chemical deposition mode to plate out the thickness of needs.
Referring to Figure 50, stick the photoresistance film that can carry out exposure imaging at the metal substrate back side of step 10 seven, purpose is the making for follow-up metallic circuit layer, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 10 nine, the metal substrate back side
, referring to Figure 51, utilize exposure imaging equipment that step 10 eight is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side.
Referring to Figure 52, electroplate the 4th metallic circuit layer as belong to the conductive posts of line layer in order to connect the 3rd metallic circuit layer and five metals in the zone of metal substrate back side removal part photoresistance film in step 10 nine, the material of metallic circuit layer can adopt copper, nickel gold, NiPdAu, silver, gold or tin metal, and plating mode can make chemical deposition or metallide mode.
Referring to Figure 53, remove the photoresistance film of metallic substrate surfaces, purpose is to carry out non-conductive glued membrane operation for follow-up, the method for removing the photoresistance film can adopt chemical medicinal liquid to soften and adopt the mode of high pressure water washing to remove the photoresistance film.
referring to Figure 54, the non-conductive glued membrane of (zone that line layer is arranged) pressing one deck at the metal substrate back side, purpose is to insulate for the 3rd metallic circuit layer and five metals belong to line layer, the mode of the non-conductive glued membrane of pressing can adopt conventional roll unit, or carry out pressing under the environment of vacuum, to prevent that the pressing process from producing the residual of air, non-conductive glued membrane is mainly thermosetting epoxy resin, and epoxy resin can not have filler or Packed non-conductive glued membrane according to the product performance employing, the color of epoxy resin can be according to the product performance processing of dyeing.
Referring to Figure 55, carry out surface grinding after completing non-conductive glued membrane pressing, purpose is to expose the 4th metallic circuit layer, keeps the evenness of non-conductive glued membrane and the 4th metallic circuit layer and the thickness of controlling non-conductive glued membrane.
Referring to Figure 56, to the preliminary treatment of metallizing of non-conductive glued membrane surface, make its surface attachment last layer metallization macromolecular material, purpose is the catalyst conversion that as subsequent metal material, can plate, and the adhesion metal macromolecular material can adopt spraying, plasma concussion, surface coarsening etc. to go to dry again and get final product;
Referring to Figure 57, the metal substrate front and back sticks the photoresistance film that can carry out exposure imaging in step 2 14, to protect follow-up five metals, belongs to the electroplating technology operation of line layer, and the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Part photoresistance film is removed at step 2 16, the metal substrate back side
Referring to Figure 58, utilize exposure imaging equipment that step 2 15 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, carry out etched regional graphics to expose the follow-up needs in the metal substrate back side.
Referring to Figure 59, carry out the etching operation in the zone that step 2 16 is completed after the photoresistance film is windowed, its objective is that the metallic region corrosion beyond the metallic circuit that will keep is clean, carrying out etching method can be copper chloride or iron chloride or the technology mode that can carry out the liquid medicine of chemical etching.
The photoresistance film is removed at step 2 18, the metal substrate back side
, referring to Figure 60, remove the photoresistance film at the metal substrate back side, the metallic region figure that is plated to expose follow-up needs.
Referring to Figure 61, carry out five metals at the metal substrate back side of step 2 18 and belong to the plating work of line layer, five metals belongs to line layer and electroplates after completing namely form corresponding Ji Dao and pin on metal substrate, the material that five metals belongs to line layer can be copper, nickel gold, NiPdAu, silver, gold or tin metal, and plating mode can be that chemical deposition adds metallide or all uses the chemical deposition mode to plate out the thickness of needs.
Referring to Figure 62, the photoresistance film that can carry out exposure imaging is sticked in the metal substrate front in step 2 19, and the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
Referring to Figure 63, utilize exposure imaging equipment that step 3 ten is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, carry out etched regional graphics to expose the positive follow-up needs of metal substrate.
Referring to Figure 64, metal substrate front in step 3 11 to be completed the zone of exposure imaging and carry out chemical etching, chemical etching is until the metallic circuit layer, and etching solution can adopt copper chloride or iron chloride or the liquid medicine that can carry out chemical etching.
Referring to Figure 65, to complete the metal substrate front of chemical etching and stick the photoresistance film that can carry out exposure imaging in step 3 12, the photoresistance film can be that dry type photoresistance film can be also wet type photoresistance film.
, referring to Figure 66, utilize exposure imaging equipment that step 3 13 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate.
Referring to Figure 67, electroplate the metal pillar in the zone of the positive removal of metal substrate part photoresistance film in step 3 14, the material of metal pillar can be copper, aluminium, nickel, silver, gold, the materials such as copper is silver-colored, nickel is golden, NiPdAu, certainly other metallics that can conduct electricity can use, do not limit to copper, aluminium, nickel, silver, gold, the metal materials such as copper is silver-colored, nickel is golden, NiPdAu, plating mode can make chemical deposition or metallide mode.
Referring to Figure 68, remove the photoresistance film of metallic substrate surfaces, can adopt chemical medicinal liquid to soften and adopt the mode that high pressure water jets is removed to remove the photoresistance film.
Referring to Figure 69, at basic island front surface coated conduction or the nonconducting bonding material that step 2 19 forms, purpose be for after follow-up implanted chip with the engaging of Ji Dao.
Referring to Figure 70, positive first chip of implanting on the basic island of step 3 17.
Referring to Figure 71, carry out the operation of bonding metal wire between the first chip front side and pin front, the material of described metal wire adopts gold, silver, copper, aluminium or the material of alloy, shape wiry can be thread can be also banded.
Referring to Figure 72, the positive plastic packaging material that adopts of metal substrate in step 3 19 is carried out plastic packaging, the plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method, with pad pasting mode or the mode of brush coating, described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Referring to Figure 73, to carry out epoxy resin surface and grind after the epoxy resin plastic packaging of completing steps 40, purpose is to make the metal pillar expose the thickness of plastic-sealed body surface and control ring epoxy resins.
Referring to Figure 74, the exposed metal of the metallic substrate surfaces after completing steps 41 is electroplated anti-oxidant metal layer, prevents burning, as gold, golden, the NiPdAu of nickel, tin or coating antioxidant (OSP).
Referring to Figure 75, the Ji Dao of step 4 12 and the pin back side is filled up between Metal Ball and Metal Ball by underfill and chip and Ji Dao, basic island between space after upside-down mounting the second chip, after the mode of upside-down mounting can be coated in underfill on Ji Dao and pin in upside-down mounting again the second chip or underfill is coated in the second chip front side, upside-down mounting is positive in Ji Dao and pin.
Referring to Figure 76, adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 4 13, the plastic packaging mode can adopt mould encapsulating mode, spraying equipment spraying method or use the pad pasting mode, and described plastic packaging material can adopt packing material or without the epoxy resin of packing material.
Referring to Figure 77, step 4 14 is completed the semi-finished product of sealing carry out cutting operation, make and originally in array aggregate mode, integrate and to contain more than cuttings of plastic-sealed body module of chip independent, after making first erosion, inside back cover maintains the irrespective of size flip chip encapsulation structure, can adopt conventional diamond blade and conventional cutting equipment to get final product.
Claims (12)
1. the rear inside back cover of first erosion maintains the process that the irrespective of size flip-chip encapsulates, and described method comprises the steps:
Step 1, get metal substrate
Step 2, the little copper layer of metallic substrate surfaces preplating
Step 3, the operation of subsides photoresistance film
In the metal substrate front of completing the little copper layer of preplating and the back side stick respectively the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 4, the metal substrate back side
Utilize exposure imaging equipment that step 3 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Step 5, plated metal line layer
Electroplate the metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 4;
Step 6, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 5;
Part photoresistance film is removed at step 7, the metal substrate back side
Utilize exposure imaging equipment that step 6 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Step 8, plating high-conductive metal line layer
Electroplate the high-conductive metal line layer in the zone of metal substrate back side removal part photoresistance film in step 7, form corresponding Ji Dao and pin;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, epoxy resin plastic packaging
Utilize epoxide resin material to carry out the plastic packaging protection on the metallic circuit layer surface at the metal substrate back side;
Step 11, epoxy resin surface grind
Carrying out epoxy resin surface after completing the epoxy resin plastic packaging grinds;
Step 12, the operation of subsides photoresistance film
Metal substrate front and back at completing steps 11 sticks the photoresistance film that can carry out exposure imaging;
Step 13, the positive part photoresistance film of removing of metal substrate
Utilize exposure imaging equipment that step 12 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the positive follow-up needs of metal substrate, carry out etched regional graphics;
Step 14, chemical etching
Metal substrate front in step 13 is completed the zone of exposure imaging and carry out chemical etching;
Step 15, the operation of subsides photoresistance film
Metal substrate front and back at completing steps 14 sticks the photoresistance film that can carry out exposure imaging;
Step 10 six, the positive part photoresistance film of removing of metal substrate
Utilize exposure imaging equipment that step 15 is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate;
Step 10 seven, plated metal pillar
Electroplate the metal pillar in the zone of the positive removal of metal substrate part photoresistance film in step 10 six;
Step 10 eight, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10 nine, coating bonding material
At the basic island of step 10 eight front surface coated conduction or non-conductive bonding material;
Step 2 ten, load
Implant the first chip on the conduction of step 10 nine or non-conductive material;
Step 2 11, metal wire bonding
Carry out the operation of bonding metal wire between the first chip front side and pin front;
Step 2 12, seal
The positive plastic packaging material that adopts of metal substrate in step 2 11 is carried out plastic packaging;
Step 2 13, epoxy resin surface grind
Carrying out epoxy resin surface after the epoxy resin plastic packaging of completing steps 22 grinds;
Step 2 14, plating anti-oxidant metal layer or coating antioxidant
The exposed metal of metallic substrate surfaces after completing steps 23 is electroplated anti-oxidant metal layer or coating antioxidant;
Step 2 15, load
Ji Dao and pin back side upside-down mounting the second chip in step 2 14;
Step 2 16, seal
Adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 2 15;
Step 2 17, cutting finished product
Step 2 16 is completed the semi-finished product of sealing carry out cutting operation, make the rear inside back cover of first erosion and maintain the irrespective of size flip chip encapsulation structure.
2. after a first erosion of being made by claim 1, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that it comprises Ji Dao (1) and pin (2), in the front of described Ji Dao (1) conduction or non-conductive material (3), the first chip (4) just is being housed, by underfill (5) upside-down mounting, the second chip (6) is arranged at described Ji Dao (1) and pin (2) back side, described the first chip (4) positive with pin (2) front between be connected with metal wire (7), be provided with conductive posts (8) in described pin (2) front, the zone that described Ji Dao (1) is peripheral, zone between Ji Dao (1) and pin (2), zone between pin (2) and pin (2), the zone on Ji Dao (1) and pin (2) top, zone and first chip (4) of Ji Dao (1) and pin (2) bottom, the second chip (6), the outer plastic packaging material (9) that all is encapsulated with of metal wire (7) and conductive posts (8), described plastic packaging material (9) flushes with the top of conductive posts (8), the surface of exposing plastic packaging material (9) in described conductive posts (8) is coated with anti oxidation layer or coating antioxidant (10).
3. after a kind of first erosion that provides according to claim 2, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that between described pin (2) and pin (2) by conduction bonding material cross-over connection passive device (11).
4. after the according to claim 2 or 3 a kind of first erosions that provide, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that by underfill (5) upside-down mounting, a plurality of the second chips (6) being arranged at described Ji Dao (1) and pin (2) back side.
5. after the according to claim 2 or 3 a kind of first erosions that provide, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that at described the second chip (6) back side being provided with the 3rd chip (12) by conduction or non-conductive bonding material (3), described the 3rd chip (12) positive with pin (2) back side between be connected by metal wire (7).
6. after a kind of first erosion that provides according to claim 4, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that at described the second chip (6) back side being provided with the 3rd chip (12) by conduction or non-conductive bonding material (3), described the 3rd chip (12) positive with pin (2) back side between be connected by metal wire (7).
7. after the according to claim 2 or 3 a kind of first erosions that provide, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that by Metal Ball (13) upside-down mounting, the 3rd chip (12) being arranged at described pin (2) back side, described Metal Ball (13) and the 3rd chip (12) are in the inside of plastic packaging material (9).
8. after a kind of first erosion that provides according to claim 4, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that by Metal Ball (13) upside-down mounting, the 3rd chip (12) being arranged at described pin (2) back side, described Metal Ball (13) and the 3rd chip (12) are in the inside of plastic packaging material (9).
9. after the according to claim 2 or 3 a kind of first erosions that provide, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that by Metal Ball (13) upside-down mounting, passive device (11) being arranged at described pin (2) back side, described Metal Ball (13) and passive device (11) are in the inside of plastic packaging material (9).
10. after a kind of first erosion that provides according to claim 4, inside back cover maintains the irrespective of size flip chip encapsulation structure, it is characterized in that by Metal Ball (13) upside-down mounting, passive device (11) being arranged at described pin (2) back side, described Metal Ball (13) and passive device (11) are in the inside of plastic packaging material (9).
11. after a first erosion, inside back cover maintains the process that the irrespective of size flip-chip encapsulates, and it is characterized in that described method comprises the steps:
Step 1, get metal substrate
Step 2, the little copper layer of metallic substrate surfaces preplating
Step 3, the operation of subsides photoresistance film
In the metal substrate front of completing the little copper layer of preplating and the back side stick respectively the photoresistance film that can carry out exposure imaging;
Part photoresistance film is removed at step 4, the metal substrate back side
Utilize exposure imaging equipment that step 3 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Step 5, plating the first metallic circuit layer
Electroplate the first metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 4;
Step 6, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 5;
Part photoresistance film is removed at step 7, the metal substrate back side
Utilize exposure imaging equipment that step 6 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Step 8, plating the second metallic circuit layer
Electroplate the second metallic circuit layer conduct in order to connect the conductive posts of the first metallic circuit layer and the 3rd metallic circuit layer in the zone of metal substrate back side removal part photoresistance film in step 7;
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 10, the non-conductive glued membrane operation of pressing
At the non-conductive glued membrane of metal substrate back side pressing one deck;
Step 11, the non-conductive glued membrane of grinding surface
Carry out surface grinding after completing non-conductive glued membrane pressing;
Step 12, the preliminary treatment of non-conductive glued membrane surface metalation
To the preliminary treatment of metallizing of non-conductive glued membrane surface;
Step 13, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side and the back side in step 12;
Part photoresistance film is removed at step 14, the metal substrate back side
Utilize exposure imaging equipment that step 13 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the follow-up needs in the metal substrate back side, carry out etched regional graphics;
Step 15, etching operation
Carry out the etching operation in the zone that step 14 is completed after the photoresistance film is windowed;
The photoresistance film is removed at step 10 six, the metal substrate back side
Remove the photoresistance film at the metal substrate back side, the metallic region figure that is plated to expose follow-up needs;
Step 10 seven, plating the 3rd metallic circuit layer
Carry out the plating work of the 3rd metallic circuit layer at the metal substrate back side of step 10 six;
Step 10 eight, the operation of subsides photoresistance film
Stick the photoresistance film that can carry out exposure imaging at the metal substrate back side of step 10 seven;
Part photoresistance film is removed at step 10 nine, the metal substrate back side
Utilize exposure imaging equipment that step 10 eight is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the follow-up needs in the metal substrate back side;
Step 2 ten, plating the 4th metallic circuit layer
Electroplate the 4th metallic circuit layer as belong to the conductive posts of line layer in order to connect the 3rd metallic circuit layer and five metals in the zone of metal substrate back side removal part photoresistance film in step 10 nine;
Step 2 11, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 2 12, the non-conductive glued membrane operation of pressing
At the non-conductive glued membrane of metal substrate back side pressing one deck;
Step 2 13, the non-conductive glued membrane of grinding surface
Carry out surface grinding after completing non-conductive glued membrane pressing;
Step 2 14, the preliminary treatment of non-conductive glued membrane surface metalation
To the preliminary treatment of metallizing of non-conductive glued membrane surface;
Step 2 15, the operation of subsides photoresistance film
The metal substrate front and back sticks the photoresistance film that can carry out exposure imaging in step 2 14;
Part photoresistance film is removed at step 2 16, the metal substrate back side
Utilize exposure imaging equipment that step 2 15 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the follow-up needs in the metal substrate back side, carry out etched regional graphics;
Step 2 17, etching operation
Carry out the etching operation in the zone that step 2 16 is completed after the photoresistance film is windowed;
The photoresistance film is removed at step 2 18, the metal substrate back side
Remove the photoresistance film at the metal substrate back side;
Step 2 19, plating five metals belong to line layer
Carry out five metals at the metal substrate back side of step 2 18 and belong to the plating work of line layer, five metals belongs to line layer and electroplates after completing namely form corresponding Ji Dao and pin on metal substrate;
Step 3 ten, the operation of subsides photoresistance film
The photoresistance film that can carry out exposure imaging is sticked at the metal substrate back side in step 2 19;
Step 3 11, the positive part photoresistance film of removing of metal substrate
Utilize exposure imaging equipment that step 3 ten is completed the metal substrate front of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, to expose the positive follow-up needs of metal substrate, carry out etched regional graphics;
Step 3 12, chemical etching
Metal substrate front in step 3 11 is completed the zone of exposure imaging and carry out chemical etching, chemical etching is until the metallic circuit layer;
Step 3 13, the operation of subsides photoresistance film
Complete the metal substrate front of chemical etching and stick the photoresistance film that can carry out exposure imaging in step 3 12;
Step 3 14, the positive part photoresistance film of removing of metal substrate
Utilize exposure imaging equipment that step 3 13 is completed the metal substrate back side of pasting the operation of photoresistance film and carry out graph exposure, develop and remove part figure photoresistance film, the regional graphics of electroplating to expose the positive follow-up needs of metal substrate;
Step 3 15, plated metal pillar
Electroplate the metal pillar in the zone of the positive removal of metal substrate part photoresistance film in step 3 14;
Step 3 16, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces;
Step 3 17, coating bonding material
Basic island front surface coated conduction or nonconducting bonding material after completing steps 36;
Step 3 18, load
Implant the first chip on the conduction of step 3 17 or non-conductive material;
Step 3 19, metal wire bonding
Carry out the operation of bonding metal wire between the first chip front side and pin front;
Step 4 ten, seal
The positive plastic packaging material that adopts of metal substrate in step 3 19 is carried out plastic packaging;
Step 4 11, epoxy resin surface grind
Carrying out epoxy resin surface after the epoxy resin plastic packaging of completing steps 40 grinds;
Step 4 12, plating anti-oxidant metal layer or coating antioxidant
The exposed metal of metallic substrate surfaces after completing steps 41 is electroplated anti-oxidant metal layer or coating antioxidant;
Step 4 13, load
Ji Dao and pin back side upside-down mounting the second chip in step 4 12;
Step 4 14, seal
Adopt plastic packaging material to carry out plastic packaging at the metal substrate back side in step 4 13;
Step 4 15, cutting finished product
Step 4 14 is completed the semi-finished product of sealing carry out cutting operation, make the rear inside back cover of first erosion and maintain the irrespective of size flip chip encapsulation structure.
12. after a kind of first erosion according to claim 11, inside back cover maintains the process of irrespective of size flip-chip encapsulation, but it is characterized in that described step 6, to step 10 seven repetitive operations, forms more multi-layered metallic circuit layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015017959A1 (en) * | 2013-08-06 | 2015-02-12 | Jiangsu Changjiang Electronics Technology Co., Ltd | First-packaged and later-etched three-dimensional flip-chip system-in-package structure and processing method therefor |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000328264A (en) * | 1999-05-13 | 2000-11-28 | Toppan Printing Co Ltd | Production of etching parts |
| US20050006737A1 (en) * | 2002-04-29 | 2005-01-13 | Shafidul Islam | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN1691314A (en) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技（深圳）有限公司 | Flip ball grid array packaging base plate and making technique thereof |
| KR100723529B1 (en) * | 2006-05-10 | 2007-05-30 | 삼성전자주식회사 | Circuit board including solder ball land having hole and semiconductor package having the board |
| CN102723284A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Method for manufacturing front-mounted three-dimensional line on single side of chip by using first etching and later packaging and packaging structure of three-dimensional line |
| CN102723293A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip inversion single-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
-
2013
- 2013-08-06 CN CN201310340917.1A patent/CN103400776B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000328264A (en) * | 1999-05-13 | 2000-11-28 | Toppan Printing Co Ltd | Production of etching parts |
| US20050006737A1 (en) * | 2002-04-29 | 2005-01-13 | Shafidul Islam | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
| CN1691314A (en) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技（深圳）有限公司 | Flip ball grid array packaging base plate and making technique thereof |
| KR100723529B1 (en) * | 2006-05-10 | 2007-05-30 | 삼성전자주식회사 | Circuit board including solder ball land having hole and semiconductor package having the board |
| CN102723284A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Method for manufacturing front-mounted three-dimensional line on single side of chip by using first etching and later packaging and packaging structure of three-dimensional line |
| CN102723293A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip inversion single-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015017959A1 (en) * | 2013-08-06 | 2015-02-12 | Jiangsu Changjiang Electronics Technology Co., Ltd | First-packaged and later-etched three-dimensional flip-chip system-in-package structure and processing method therefor |
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