CN103377956A - 封装结构与基材的接合方法 - Google Patents

封装结构与基材的接合方法 Download PDF

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CN103377956A
CN103377956A CN201310129982XA CN201310129982A CN103377956A CN 103377956 A CN103377956 A CN 103377956A CN 201310129982X A CN201310129982X A CN 201310129982XA CN 201310129982 A CN201310129982 A CN 201310129982A CN 103377956 A CN103377956 A CN 103377956A
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base material
layer
silver layer
encapsulating structure
silver
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CN103377956B (zh
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殷宏林
谢哲伟
林立元
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Asia Pacific Microsystems Inc
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Asia Pacific Microsystems Inc
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Abstract

本发明提供一种基材的接合方法，包含:首先提供一第一基材和一第二基材，其中一第一银层覆盖第一基材的表面，一第二银层覆盖第二基材的表面以及一金属层覆盖第二银层，其中金属层包含一第一钖层，接着进行一接合制程，将第一基材与第二基材对准，使得金属层和第一银层接触，并且施加负载并加热至一预定温度以生成Ag3Sn金属间化合物，最后降温并移除负载，完成接合制程。本发明的有益效果是改良接合晶圆的质量，使技术能实际应用于产品量产之上。

Description

封装结构与基材的接合方法
技术领域
本发明是关于一种晶圆对晶圆接合的方法，尤其是利用Ag3Sn金属间化合物来接合晶圆。
背景技术
有别于以往半导体芯片利用后段封胶灌模及导线架或陶瓷基板等方式进行封装，近年来许多微芯片采用晶圆级封装(Wafer level package)，其利用一封盖(cap)芯片来保护芯片上对外界环境敏感的电路或脆弱的结构，如含悬浮可动组件的微机电传感器芯片等。许多微机电传感器芯片如加速度计(accelerometer)或压力计（pressure sensor)等通常会与一具凹槽(recess)结构的玻璃或硅芯片进行晶圆接合(wafer bonding)，以保护感测结构或薄膜，亦可提供如气密(hermetic seal)、硅穿孔导线(TSV)等功能。
常用的晶圆接合技术包含熔融接合(fusion bonding)、阳极接合(anodicbonding)及介质接合如共晶接合(eutectic bonding)或高分子接合等。由于熔融接合及阳极接合仅分别适用于硅-硅或二氧化硅及硅-含钠玻璃的接合，且对于晶圆表面的平整度要求较高，限制了其应用范围，因此利用兼容的介质来进行晶圆接合成为较常采用的方法。其中玻璃熔料（glass frit)已被大量使用在消费性电子芯片上，但由于其需利用网印(screen printing)的方式来将接合环(bond ring)图案化，使得其接合环(bonding ring)宽度大于100-2OOμm，对于逐渐微缩芯片尺寸的需求将构成严峻的挑战。而高分子材料(如BCB或光阻等)可利用黄光微影的方式精确定义接合环，因此宽度可大幅缩小，但由于高分子材料在高温时会有释放气体(out-gassing)的现象且其接合强度较弱，将影响产品的可靠度(reliability)。
而通过特定金属于较低温时接触互熔产生共晶的方式，将金属层预先成形定义于微机电晶圆及封盖晶圆上，当施加负载使两晶圆接触并升温至共晶温度之上维持一段时间后，即可将两片晶圆接合。在此通常选择半导体中常见或制程兼容的金属，如美国专利第7943411号教导利用铝-锗共晶的方式将封盖晶圆接合于微机电组件晶圆之上，由于铅-锗的共晶温度为419°C，因此欲形成一稳定的接合则其制程温度一般需提高至430至450°C，此高温可能会对部分膜层界面造成影响且所产生的热应力(thermal stress)亦会造成感测薄膜变形或失效。美国专利第5668033号则是揭露利用金-硅共晶来接合加速度传感器芯片上的封盖，由于Au-Si的共晶温度为363°C，因此可略微降低制程所需的温度(约390-410°C)，其缺点为金的成本较高且须克服硅表面生成自然氧化层(native oxide)的问题。因此需要开发另一与半导体制程兼容的金属共晶接合技术，来进行微机电组件的封盖制程，同时需具有较低的共晶接合温度及成本。美国专利第6229190号中提及可利用银-钖共晶的方式，在压力感测组件晶圆及封盖晶圆上分别成长银或钖后，对压力感测组件进行封盖接合。由于银-钖远低于铝-锗及金-硅的共晶温度仅约221°C，可大幅避免上述所提的热应力等问题，其成本亦远低于金，因此成为极具潜力的技术之一。然而此接合技术所遭遇的棘手问题在于钖本身为一熔点低(约230°C)且强度较低的脆性材料，因此经由银-钖共晶接合后所产若仍含高比例的纯钖，不仅会降低接合界面强度，且当后续制程温度高于钖的熔点230°C时(如通过回焊炉温度约为250°C)将对封装结构造成破坏。
发明内容
有鉴于此，本发明提出一特殊的封装方式，以改良接合晶圆的质量，使技术能实际应用于产品量产之上。
根据本发明的一较佳实施例，本发明提供一种封装结构，包含:一第一基材和一第二基材以及多个金属堆栈层设置于第一基材和第二基材之间，其中各个金属堆栈层包含至少一第一银层、一第二银层和一合金层位在第一银层和第二银层之间，其中合金层包含Ag3Sn金属间化合物(intermetalliccompound)和锡基体(Sn matrix)。
根据本发明的另一较佳实施例，木发明提供一种基材的接合方法，包含:首先提供一第一基材和一第二基材，其中一第一银层覆盖第一基材的表面，一第二银层覆盖第二基材的表面以及一金属层覆盖第二银层，其中金属层包含一第一钖层，接着进行一接合制程，将第一基材与第二基材对准，使得金属层和第一银层接触，并且施加负载并加热至一预定温度以生成Ag3Sn金属间化合物，最后降温并移除负载，完成接合制程。
为让本发明的上述目的、特征和优点更能明显易懂，下文将以实施例并配合所附图示，作详细说明如下。
附图说明
图1至图3为根据本发明的第一较佳实施例所绘示的基材的接合方法。
图4绘示的是合金层的放大示意图。
图5至图6为根据本发明的第二较佳实施例所绘示的基材的接合方法。
图7绘示的是本发明的第1组的基材结构配置。
图8是根据本发明的第五较佳实施例所绘示的封装结构。
图9是根据本发明的第六较佳实施例所绘示的封装结构。
图10是根据本发明的第七较佳实施例所绘示的封装结构。
图11是根据本发明的第八较佳实施例所绘示的封装结构。
具体实施方式
图1至图3为根据本发明的第一较佳实施例所绘示的基材的接合方法。请参阅图1，百先提供一第一基材10和一第二基材20，第一基材10和第二基材20可以为任何适用于电子装置封装的材料形成，例如硅、砷化镓、蓝宝石、金属、陶瓷、及玻璃或其他半导体材料。第一基材10具有一第一表面12，第二基材20也有一第二表面22，第一表面12和第二表面22皆为为装置面，先在第一基材10的第一表面12上依序形成一附着层14、一阻绝层16和一第一银层18，另外在第二基材20的第二表面22上依序形成一附着层14、一阻絶层16、一第二银层24和一金属层26，其中前述的金属层26包含一第一钖层28。附着层14包含铬或钛而阻絶层16包含镍或铂，另外，第一银层18、第二银层24和金属层26可以利用电子束蒸镀、溅镀或是电镀来形成。如图2所示，进行微影和蚀刻制程或是举离（lift-off)等方式，分别图案化第一基材10上的附着层14、阻絶层16和第一银层18，以及第二基材20上的附着层14、阻絶层16、第二银层24和金属层26，在图案化之后，剩余的附着层14、阻絶层16、第一银层18、第二银层24和金属层26，将在后续步骤形成接合环。
然后进行一预清洗步骤，可使用湿式蚀刻的方式，例如含氢氟酸(HF）系水溶液来清洗第一银层18和金属层26的表面，或是利用干式蚀刻的方式，例如氩离子电浆蚀刻等方式进行附着层14、阻絶层16、第一银层18、第二银层24和金属层26的预清洗。如图3所示，进行一接合制程，将第一基材10和第二基材20对准接合，详细来说，接合是指将第一基材10上的第一银层18对准第二基材20上的金属层26并且使第一银层18和金属层26接触，之后再施加一均匀负载(loading)于第一基材10和第二基材20，并且使第一基材10和第二基材20以及其上的银层18、24和金属层26升温至一预定温度，在预定温度维持一预定时间，前述的预定温度需超过银和钖的共晶温度，根据本发明的较佳实施例，预定温度为250至350度之间，而预定时间约为30分钟，然后降温及移除负载即完成接合制程。请参同时参阅图3和图4，图4绘示了Ag3Sn金属间化合物和锡基体混合的示意图。在接合制程中，部分的第一银层18、部分的第二银层24会和第一钖层28会反应形成Ag3Sn金属间化合物32，未和银结合的第一钖层28会聚集成为锡基体34，前述的Ag3Sn金属间化合物32和锡基体34定义为一合金层30。由于可通过第一银层18及第二银层24同时与第一锡层28产生共晶反应，因此共晶合金层中Ag3Sn金属间化合物32会均匀分布于锡基体34中，除提升接合强度外，由于此金属堆栈层50为一对称结构，因此可进一步降低接合所产生的梯度应力(gradient stress)。
另外，为强化共晶反应及接合强度，可选择性地将接合完成的基材10、20进行接合后退火(Post-bond annealing)，例如将接合的基材10、20在炉管或烤箱内进行退火，以确保大量的钖充分共晶成为Ag3Sn，退火温度较佳介于350至450度之间，由于可批次大量进行接合晶圆后的退火制程，相较以单次进行长时间的接合制程，利用接合后退火处理来改善接合强度更符合量产的需求。
图5至图6为根据本发明的第二较佳实施例所绘示的基材的接合方法，第二较佳实施例为第一较佳实施例的变化型，其和第一实施例的差异点在于形成在第二基材20上的金属层26的组成，如图5所示，第二基材20上的金属层26可以由银金属层和钖金属层交替堆栈而组成，举例而言，在第一较佳实施例中的第一钖层28形成之后，依序另形成一第三银层36和一第二钖层38，当然，本发明的金属层26可依据产品需求，交替形成适当的银金属层和钖金属层，之后再进行微影和蚀刻制程或是举离制程。后续的接合制程和退火制程步骤，都和第一实施例中描述的相同，在此不再赘述。请同时参阅图4和图6，在接合制程中，部分的第一银层18、部分的第二银层24和部分的第三银层36会分别和第一钖层28和第二钖层38反应形成Ag3Sn金属间化合物32，未和银结合的第一钖层28和第二钖层38会被打散成为锡基体34，前述的Ag3Sn金属间化合物32和锡基体34定义为一合金层30。本实施例中，合金层30有二层，而在二层合金层30中间夹着第三银层36。
依据本发明第一较佳实施例和第二较佳实施例的精神，发明人调整金属层26的组成以及退火时间，将基材接合方式分成五组，然后将其切割成多个相同尺寸的晶粒，最后再对分别利用这五种制程方式所接合的封装晶粒进行强度测试，包括剪力测试和高压水渗透测试。各组的制程条件分述如下:
第1组
请参阅图7，第1组的第一基材10上和配置就如第一实施例中所述，第二基材20上的金属层26也和第一实施例中相同，只有含有第一钖层28，和第一实施例不同的是第1组中的第二基材20上没有第二银层24，而且第1组的第一基材10和第二基材20在接合后未进行退火步骤。
第2组
请复参阅图7，第2组的第一银层18和金属层26的配置就如第1组中所述，不同的是第2组的退火步骤时间为1小时。
第3组
请参阅图2，第3组的第一基材10和第二基材20上的第一银层18、第二银层24和金属层26的配置就如第一实施例中所述，不同的是第3组的退火步骤的进行时间为1小时。
第4组
请复参阅图2，第4组的第一银层18、第二银层24和金属层26的配置就如第一实施例中所述，不同的是第4组的退火步骤时间为1.5小时。
第5组
请参阅图5，第5组的第一基材10和第二基材20上的第一银层18、第二银层24和金属层26的配置就如第二实施例中所述，不同的是第5组的退火步骤的进行时间为1小时。
表一为第1组至第5组的实验数据表，测试利用本发明接合技术所完成的封装结构的剪力和高压水渗透数据。
表一显示针对五组基材接合方式分别做剪力测试和高压水渗透测试的实验结果
Figure BDA00003052365400061
如表一所示，比较第1组和第2组可发现第1组由于未经接合后退火处理，因此其强度较差，因此在接合制程之后两片晶圆随即分离，而第2组经接合后退火处理后仍具一定强度，显见接合后退火制程确能促使Ag3Sn金属间化合物的生成，因而增加接合强度。另比较第2、3及5组可知，第2组的第二晶圆20上未含银层，所以在相同的接合及退火时间下Ag3Sn金属间化合物32的生成仍较第3和第5组不完全，因此其强度较弱，且以高压水渗透的方式测试第2组的密封性，在223晶粒中仅10个晶粒通过测试;反观第3及第5组在接合制程之前，第二晶圆20上有第二银层24和金属层26，其中金属层26包含第一锡层28或第一锡层28、第三银层36及第二锡层38的堆迭结构，因此在合金层30中，其Ag3Sn金属间化合物32的生成的比例较高，剩余的锡基体34比例较低，所以接合强度较强，且密封性亦较佳。因此得以验证，在接合制程中，利用银层和钖层堆栈结构的确可得到较佳的接合强度及密封性。另比较第3及第4组可发现，由于第4组的退火时间较长，使其合金层30中Ag3Sn金属间化合物32的比例较第3组高，因此其强度亦较为提升。
第3图绘示的是根据本发明的第三较佳实施例所绘示的封装结构。第三较佳实施例系利用本发明的基材接合方法所形成，如第3图所示，本发明的封装结构包含一第一基材10、一第二基材20和以及多个金属堆栈层50设置于第一基材10和第二基材20之间，其中各个金属堆栈层50包含至少一第一银层18、一第二银层24和一合金层30位在第一银层18和第二银层24之间，请同时参阅第4图，值得注意的是合金层30包含Ag3Sn金属间化合物32和锡基体34，其中Ag3Sn金属间化合物32较佳为是均匀混合在锡基体34中。
再者，前述的第一基材10和第二基材20可以为任何适用于电子装置封装的材料形成，例如硅晶圆、砷化镓、蓝宝石、金属、陶瓷、及玻璃或其他半导休材料。在本发明中基材的材料以晶圆为例，通常，晶圆中可以包含单晶硅、覆硅绝缘层、硅一锗基材或是前述的组合。另外，前述的第一银层18系与第一基材10的第一表面22接触，第二银层24系与第二基材20的第二表面22接触，一附着层16，例如铬或钛，系位在各个金属堆栈层50和第一基材10之间以及各个金属堆栈层50和第二基材20之间，再者附着层14和各个金属堆栈层50之间具有一阻绝层16，阻绝层16包含镍和铂。
第6图绘示的是根据本发明的第四较佳实施例所绘示的封装结构。请参阅第6图，第四实施例和第三实施例的差别在于第四实施例的金属堆栈层50中，除了第一银层18和第二银层24之外，还另包含二层合金层30和一层第三银层36，第三银层36夹在合金层30之间。
第8图是根据本发明的第五较佳实施例所绘示的封装结构。本发明的接合方式适用于接合各个不同的晶圆，如第8图所示，第一基材10可以为一封盖晶圆或是一微机电晶圆，而第二基材20可以为一封盖晶圆或是一微机电晶圆，但第一基材10和第二基20材为不同种类的晶圆，举例而言，第一基材10可以为一封盖晶圆，其上设有至少一个凹槽52，第二基材20可以为一微机电晶圆，其上设有至少一微机电组件54，而第三实施例或第四实施例中的金属堆栈层50，可设置于第一基材10和第二基材20之间。同样地，金属堆栈层50至少包含合金层30、第一银层18和第二银层24，另外，附着层14和阻绝层16则可以选择性设置。
第9图是根据本发明的第六较佳实施例所绘示的封装结构。第六较佳实施例为第五较佳实施例的变化型，其中第一基材10可以为一封盖晶圆，其上设有至少一个凹槽52，第二基材20可以为一微机电晶圆，其上设有至少一微机电组件54，而第三实施例或第四实施例中的金属堆栈层50，可设置于第一基材10和第二基材20之间，同样地，金属堆栈层50至少包含合金层30、第一银层18和第二银层24，另外，附着层14和阻绝层16则可以选择性设置。
此外，第一基材10和第二基材20之间另设有至少一焊垫56，焊垫56通过导电层55和微机电组件54电链接，再者，焊垫56亦含有包含Ag3Sn金属间化合物，另外，第一基材10上具有至少一穿孔58，穿孔58对应于前述焊垫56，在穿孔58内设有一金属层60，与焊垫56电性相连可将微机电组件54的电子讯号做输出。
第10图是根据本发明的第七较佳实施例所绘示的封装结构，其和第六实施例的差异点在于其微机电组件54的电子讯号输出并非通过金属层60而是直接利用打线61的方式直接将讯号线拉线链接至另一电子电路装置上(图中未标示）。
第11图是根据本发明的第八较佳实施例所绘示的封装结构。如第11图所示，第一基材10可以为一微机电晶圆，其上设有至少一微机电组件54，而第二基材20可以为CMOS晶圆，其上设有至少一电子电路组件62，而第三实施例或第四实施例中的金属堆栈层50，可设置于第一基材10和第二基材20之间用来密封接合微机电组件54，并且作为第一基材10和第二基材20的机械及电性接点，同样地，金属堆栈层50至少包含合金层30、第一银层18和第二银层24，另外，附着层14和阻绝层16则可以选择性设置。
此外，第一基材和第二基材之间设有至少一焊垫56，焊垫56亦含有包含Ag3Sn金属间化合物，焊垫56与微机电组件54以及电子电路组件62电链接，因此，微机电组件54的电子讯号可通过焊垫56传递至CMOS晶圆上的电子线路，再经由金属内联线输出。
本发明揭露一种封装结构及基材接合的方法，在一晶圆上形成银层，并在另一晶圆上交替形成银和钖的堆栈层。进行晶圆接合时，由于Ag3Sn金属间化合物的可由钖与上下两层银接触的界面开始生成，因此可缩短相互扩散所需的时间，在较短的时间内使银和钖形成Ag3Sn共晶。另外，在接合制程完成后，加入一接合后退火步骤，使纯钖大量转化Ag3Sn金属间化合物並均匀分布于锡层中，进一步提升接合的强度及密封等特性。
上述实施例仅是为了方便说明而举例，虽遭所属技术领域的技术人员任意进行修改，均不会脱离如权利要求书中所欲保护的范围。

Claims (18)

1.一种封装结构，其特征在于，包含:
一第一基材;
一第二基材;以及
多个金属堆栈层设置于该第一基材和该第二基材之间，其中各该金属堆栈层包含至少一第一银层、一第二银层和一合金层位在该第一银层和该第二银层之间，其中该合金层包含Ag3Sn金属间化合物和锡基体。
2.如权利要求1所述的封装结构，其特征在于，该第一银层接触该第一基材的表面，该第二银层接触该第二基材的表面。
3.如权利要求1所述的封装结构，其特征在于，该Ag3Sn金属间化合物和锡基体为均匀混合。
4.如权利要求1所述的封装结构，其特征在于，该第一基材及该第二基材可为硅、砷化镓、蓝宝石、金属、陶瓷、及玻璃或其他半导体材料。
5.如权利要求1所述的封装结构，其特征在于，另包含一附着层位在各该金属堆栈层和该第一基材之间以及各该金属堆栈层和该第二基材之间，该附着层包含铬或钛。
6.如权利要求5所述的封装结构，其特征在于，该附着层和各该金属堆栈层之间具有一阻绝层，该阻绝层包含镍或铂。
7.如权利要求1所述的封装结构，其特征在于，另包含至少一微机电组件设置于该第一基材上，且另包含一焊垫与该微机电组件电性相连。
8.如权利要求7所述的封装结构，其特征在于，该焊垫包含Ag3Sn金属间化合物。
9.如权利要求8所述的封装结构，其特征在于，另包含至少一电子电路组件设置于该第二基材上。
10.如权利要求9所述的封装结构，其特征在于，该焊垫为该微机电组件与该电子电路组件间的机械及电性接点。
11.如权利要求7所述的封装结构，其特征在于，另包含多个凹槽设置于该第二基材上。
12.如权利要求11所述的封装结构，其特征在于，该第二基材上包含至少一贯穿孔，该贯穿孔对应与该微机电组件电性相连之该焊垫，可利用一位在该贯穿孔内的金属层或打线的方式，来传导该焊垫的电子讯号。
13.一种基材的接合方法，其特征在于，包含:
提供一第一基材和一第二基材，其中一第一银层覆盖该第一基材的表面，一第二银层覆盖该第二基材的表面以及一金属层覆盖该第二银层，其中该金属层包含一第一钖层;
进行一接合制程，将该第一基材与该第二基材对准，使得该金属层和该第一银层接触，并且施加负载并加热至一预定温度以生成Ag3Sn金属间化合物;以及
降温并移除负载，完成接合制程。
14.如权利要求13所述的基材的接合方法，其特征在于，另包含在接合制程之后，进行一退火步骤，该退火步骤的温度范围为350-450度。
15.如权利要求13所述的基材的接合方法，其特征在于，该预定温度范围为250-350度。
16.如权利要求14所述的基材的接合方法，其特征在于，另包含形成一附着层位在该第一银层和该第一基材之间以及该第二银层和该第二基材之间，其中该附着层包含铬或钛。
17.如权利要求16所述的基材的接合方法，其特征在于，另包含形成一阻绝层位在该附着层和该第一银层之间以及该附着层和该第二银层之间，该阻绝层包含镍或铂。
18.如权利要求13所述的基材的接合方法，其特征在于，另包含在接合制程之前形成一第三银层于该第一钖层上，再形成一第二锡层于该第三银层上。
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