CN103377883B - 具有密度梯度平滑的mos阵列边缘的布局 - Google Patents

具有密度梯度平滑的mos阵列边缘的布局 Download PDF

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Publication number
CN103377883B
CN103377883B CN201310153862.3A CN201310153862A CN103377883B CN 103377883 B CN103377883 B CN 103377883B CN 201310153862 A CN201310153862 A CN 201310153862A CN 103377883 B CN103377883 B CN 103377883B
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China
Prior art keywords
density
unit
component density
array
component
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CN201310153862.3A
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English (en)
Chinese (zh)
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CN103377883A (zh
Inventor
彭永州
周文升
黄睿政
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US13/744,532 external-priority patent/US8759163B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN103377883A publication Critical patent/CN103377883A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CN201310153862.3A 2012-04-30 2013-04-27 具有密度梯度平滑的mos阵列边缘的布局 Active CN103377883B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261640073P 2012-04-30 2012-04-30
US61/640,073 2012-04-30
US13/744,532 US8759163B2 (en) 2012-04-30 2013-01-18 Layout of a MOS array edge with density gradient smoothing
US13/744,532 2013-01-18

Publications (2)

Publication Number Publication Date
CN103377883A CN103377883A (zh) 2013-10-30
CN103377883B true CN103377883B (zh) 2016-04-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310153862.3A Active CN103377883B (zh) 2012-04-30 2013-04-27 具有密度梯度平滑的mos阵列边缘的布局

Country Status (2)

Country Link
CN (1) CN103377883B (de)
DE (1) DE102013103968B4 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114937557B (zh) * 2022-05-26 2024-06-11 北京奕斯伟计算技术股份有限公司 电容阵列模组

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097913A (zh) * 2006-06-29 2008-01-02 联发科技股份有限公司 电容阵列、电容与电容阵列布局方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4646485B2 (ja) 2002-06-25 2011-03-09 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP4620942B2 (ja) 2003-08-21 2011-01-26 川崎マイクロエレクトロニクス株式会社 半導体集積回路のレイアウト方法、そのレイアウト構造、およびフォトマスク
US7335966B2 (en) * 2004-02-26 2008-02-26 Triad Semiconductor, Inc. Configurable integrated circuit capacitor array using via mask layers
US7849436B2 (en) 2006-08-11 2010-12-07 Dongbu Hitek Co., Ltd. Method of forming dummy pattern
US7866035B2 (en) * 2006-08-25 2011-01-11 Coolearth Solar Water-cooled photovoltaic receiver and assembly method
US8372742B2 (en) 2010-02-25 2013-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method, system, and apparatus for adjusting local and global pattern density of an integrated circuit design

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101097913A (zh) * 2006-06-29 2008-01-02 联发科技股份有限公司 电容阵列、电容与电容阵列布局方法

Also Published As

Publication number Publication date
DE102013103968B4 (de) 2023-05-04
CN103377883A (zh) 2013-10-30
DE102013103968A1 (de) 2013-10-31

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