CN103368394A - Efficient step-down DC-DC (Direct Current-Direct Current) converter - Google Patents
Efficient step-down DC-DC (Direct Current-Direct Current) converter Download PDFInfo
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Abstract
The invention discloses an efficient step-down DC-DC (Direct Current-Direct Current) converter. The converter comprises a power circuit and a control circuit, wherein a power part comprises a power switch tube, a synchronous rectifier tube, and a filter feedback circuit; and the control circuit comprises a current detection circuit, a gate width control circuit, a logic control and grid driving circuit, a pulse width modulating circuit, a dead zone predicating circuit and a dead zone circuit. By adopting the DC-DC converter provided by the invention, an unstable DC voltage can be lowered and efficiently converted to a stable DC voltage. When the DC-DC converter works in a light load condition, the gate width control circuit changes the sizes of the power switch tube and the synchronous rectifier tube so as to reduce the driving loss in the power circuit and improve the light-load conversion efficiency. The dead zone predicating circuit detects the residual dead zone time in real time, records the detected dead zone time, and then controls the dead zone time interval by which the dead zone circuit is added into a switch signal so as o minimize the dead zone time, reduce the conduction loss caused by the residual dead zone time, and improve the conversion efficiency of the system.
Description
Technical field
The invention belongs to the electronic circuit technology field, relate to analog integrated circuit.Be particularly related to a kind of efficient voltage reducing type DC-DC converter, mainly adopt grid width control technology and dead band Prediction and Control Technology to improve the conversion efficiency of system.
Background technology
The inner required voltage of supply power voltage in the electronic product and electronic product is inconsistent to be extremely common.A lot of portable sets adopt powered battery, and the output voltage of battery changes along with the length of service time of battery, so supply power voltage is not a constant voltage usually.The chip of electronic product inside then needs a stable supply power voltage, power management chip just becomes the indispensable part of electronic product, and whether the quality of power management chip directly has influence on the technical performance index of electronic equipment and and work safe and reliable.
Buck type Switching Power Supply is the class in the DC-DC converter, and its basic function is: will input unsettled direct voltage step-down and be converted to more stable output dc voltage.When being heavy duty, its major advantage can arrive very high conversion efficiency.
There is parasitic capacitance in power switch pipe in the side circuit, so handoff procedure in power tube conducting and shutoff, voltage and current on the power tube is not desirable instantaneous saltus step, but the process of a rising or decline is arranged, and this is because the parasitic capacitance of switching tube discharges and recharges and causes.Parasitic capacitance has been introduced the driving loss during the course.This loss is directly proportional with parasitic capacitance value size and switching frequency size.For the maximum current that may occur in the load power circuit, usually select the very large metal-oxide-semiconductor of breadth length ratio W/L as power switch pipe, this is just so that larger with the wide parasitic capacitance with growing up to direct ratio of metal-oxide-semiconductor.Under the underloading condition, this part loss proportion highlights, so that system's conversion efficiency when underloading is lower.And modern many portable set mosts of the time operate in the standby mode of low-power consumption, i.e. underloading pattern.So the conversion efficiency that improves under the underloading condition extremely is necessary.
Summary of the invention
The present invention solves the existing technical problem of prior art; Providing a kind of can be low voltage equipment with unsettled direct voltage step-down and is converted to efficiently the galvanic current pressure.When the DC-DC converter is operated under the underloading condition, device will be closed corresponding power switch pipe and synchronous rectifier, thereby reduces the driving loss in the power circuit, improves a kind of efficient voltage reducing type DC-DC converter of underloading conversion efficiency.
It is to solve the existing technical problem of prior art that the present invention also has a purpose; Provide a kind of and can detect in real time unnecessary Dead Time, then the line item of going forward side by side joins the length of Dead Time in the switching signal by the control dead-zone circuit.Thereby minimize Dead Time, reduce the conduction loss that unnecessary Dead Time is introduced, improve a kind of efficient voltage reducing type DC-DC converter of system's conversion efficiency.
Above-mentioned technical problem of the present invention is mainly solved by following technical proposals:
A kind of efficient voltage reducing type DC-DC converter is characterized in that, comprises power circuit and control circuit module (101); Wherein the input Vin of power circuit is the power input of DC-DC converter, and its output end vo ut is the power output end of DC-DC converter, the 5bit output V of control circuit module (101)
DriveP＜4:0〉be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in the power switch pipe group SW, the 5bit output V of control circuit module (101)
DriveN＜4:0〉be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in the power switch pipe group SR, the output V of power circuit
SWLink to each other with the input of control circuit module (101), the output Vfb of power circuit links to each other with the input of control circuit module (101), the output V of power circuit
SWLink to each other with the input of control circuit module (101).
For this problem, the present invention adopts the grid width control technology, according to the load current size of Real-Time Monitoring, judges the channel width that determines power switch pipe.So that under the underloading condition, the parasitic capacitance of power switch pipe is less, thereby reduce to drive loss.
In addition, in order further to reduce the wastage, all adopt synchronous rectifier to replace traditional fly-wheel diode in present most power circuit, because select suitable synchronous rectifier, its drain-source two ends are lower than the pressure drop of fly-wheel diode two ends.Under and the application conditions that output voltage is lower large at load current, do like this energy Effective Raise conversion efficiency.But to strictly control the at work not simultaneously conducting of synchronous rectifier and power switch pipe, not so can cause unnecessary large current surge, affect circuit stability.So be necessary for the dead band that the control signal of two switching tubes adds.In the Dead Time, synchronous rectifier and power switch pipe all turn-off, at this moment, the body diode of synchronous rectifier is forced to conducting, the pressure drop at sync-body diode two ends is the pressure drop at rectifying tube drain-source two ends, this pressure drop also is the drain-source pressure drop during greater than the synchronous rectifier conducting, so this section Dead Time is the smaller the better.But traditional dead band control circuit is to add the fixedly method of Dead Time, and the Dead Time that adds to switch controlling signal is the Dead Time of the maximum that needs in the circuit working, also can work under worst case with the assurance circuit.But this can make system when normal operation, introduces unnecessary Dead Time, introduces too much unnecessary conduction loss.
For this problem, the present invention adopts the dead band Prediction and Control Technology, detects the Dead Time of this switch periods, dynamically controls the Dead Time length that next cycle need to add, thereby the Dead Time in the minimization system course of work, and then the conduction loss of reduction synchronous rectifier.
Comprise power switch pipe group SW, synchronous rectifier group SR and filtering feedback circuit (102) at the above-mentioned described power circuit of a kind of efficient voltage reducing type DC-DC converter; The input of the drain terminal of the drain terminal of described power switch pipe group SW, power switch pipe group SW and filtering feedback circuit (10) is connected to the output V of power circuit jointly
SWDescribed power switch pipe group SW comprises five P type metal-oxide-semiconductors that breadth length ratio is identical, and the source electrode of five P type metal-oxide-semiconductors all links to each other with power input Vin, and drain electrode all is connected to the output V of power circuit
SW, grid respectively with the input V of power circuit
DriveP＜4:0〉link to each other; Described synchronous rectifier group SR comprises five N-type metal-oxide-semiconductors that breadth length ratio is identical, and the drain electrode of five power switch pipes all is connected to the output V of power circuit
SW, source electrode all is connected to ground, grid respectively with the input V of power circuit (102)
DriveN＜4:0〉link to each other.
Comprise inductance L, capacitor C, resistance R 1 and R2 at above-mentioned a kind of efficient voltage reducing type DC-DC described filtering feedback circuit of converter (102); Wherein, an end of inductance L is connected to the output V of power circuit
SWThe other end is connected to the power output end Vout of DC-DC converter; Capacitor C is connected between output port of power source Vout and the ground; Resistance R 1 and R2 are connected in series between output port of power source Vout and the ground, draw the output Vfb of power circuit in the middle of R1 and R2.
Comprise current detection circuit (103), grid width control circuit (104), logic control and gate driver circuit (105), pulse width modulation circuit (106), dead-zone circuit (107) and dead band prediction circuit (108) in above-mentioned a kind of efficient voltage reducing type DC-DC described control circuit module of converter (101); The input of described current detection circuit (103) is the input V of control circuit module (101)
SW, the output Vsense of current detection circuit 103 is connected to the input of grid width control circuit (104), two input D of grid width control circuit (104)
SWAnd D
SRBe connected to the output of dead-zone circuit (107), the two-way 5bit output G of grid width control circuit (104)
SW＜4:0〉and G
SR＜＜4:0〉be connected respectively to the input of logic control and gate driver circuit (105), the two-way 5bit output of logic control and gate driver circuit (105) is the two-way 5bit output V of control circuit module (101)
DriveP＜4:0〉and V
DriveN＜4:0 〉; The input of pulse width modulation circuit (106) is the input Vfb of control circuit module (101), the output of pulse width modulation circuit (106) links to each other with the input Vpwm of dead-zone circuit (107), output Dsw and the D of dead-zone circuit (107)
SRBe connected respectively to the input of grid width control circuit (104), the two-way eight 8bit input CTL_SW＜7:0 of dead-zone circuit (107)〉and CTL_SR＜7:0 dead band prediction circuit (108) output that is connected to, two inputs of dead band prediction circuit (108) are respectively the input V of control circuit module (101)
SWRoad output voltage V with logic control and gate driver circuit (105)
DriveN0
Comprise that at above-mentioned a kind of efficient voltage reducing type DC-DC described grid width control circuit of converter (104) reference voltage electronic circuit (301), four comparator com1～com4 and logic subcircuit (302) form, the normal phase input end of four comparators all links to each other with the input Vsense of grid width control circuit (104), the inverting input of four comparators links to each other with the output Vref1～Vref4 of reference voltage electronic circuit (301) respectively, the input D of the output Vcom1_out～Vcom4_out of four comparators and grid width control circuit (104)
SWAnd D
SRBe the input of logic subcircuit (302), the two-way 5bit output G of logic subcircuit (302)
SW＜4:0〉and G
SR＜4:0〉be the output of grid width control circuit (104).
Comprise two dead band passages at above-mentioned a kind of efficient voltage reducing type DC-DC converter institute's dead-zone circuit (107): SW passage group (501) and SR passage group (502), two passages link to each other side by side, input is the input Vpwm of dead-zone circuit (107), and output is the output D of dead-zone circuit (107)
SWAnd D
SR
Described SW passage group (501) comprise the first delay circuit (503), comparator com_SW, with door and_SW and not gate Not_SW; The input Vpwm of dead-zone circuit (107) links to each other with the input of the first delay circuit (503), the output of the first delay circuit (503) is connected to the normal phase input end of comparator com_SW, the output of comparator com_SW is connected to the input with door and_SW, be connected to the input of not gate Not_SW with the output of door and_SW, the output of not gate Not_SW is the output D of dead-zone circuit (107)
SW
Described SR passage group (502) comprise not gate Not_SR, the second delay circuit (504), comparator com_SR and with door and_SR; The input of the input Vpwm NAND gate Not_SR of dead-zone circuit (107) links to each other, the output of not gate Not_SR links to each other with the input of delay circuit second (504), the output of the second delay circuit (504) is connected to the normal phase input end of comparator com_SR, the output of comparator com_SR is connected to the input with door and_SR, is the output D of dead-zone circuit (107) with the output of door and_SR
SR
Comprise a NOR gate Nor, delay circuit (601), the first shaping circuit (602), the second shaping circuit (603), the first counter (604) and the second counter (605) at above-mentioned a kind of efficient voltage reducing type DC-DC converter described dead band prediction circuit (108); Two input V of dead band prediction circuit (108)
SWAnd V
DriveNOTwo inputs of ANDORNOTgate Nor link to each other, simultaneously, and input V
SWAlso the input with the first shaping circuit (602) links to each other, input V
DriveNOAlso the input with the second shaping circuit 603 links to each other, and the output of the first shaping circuit (602) is connected to the input end of clock of the first counter (604), and the output of the second shaping circuit (603) is connected to the input end of clock of the second counter (605); The output of NOR gate Nor links to each other with the input of delay circuit (601), the data input pin of the first counter (604) and the second counter (605) links to each other with the output Delay of delay circuit (601), output CTL_SW＜the 7:0 of the 8bit output of the first counter (604) and dead band prediction circuit (108)〉link to each other the output CTL_SR＜7:0 of the 8bit output of the second counter (605) and dead band prediction circuit (108)〉link to each other.
Therefore, the present invention has following advantage: 1. can be low voltage equipment with unsettled direct voltage step-down and be converted to efficiently galvanic current and press.When the DC-DC converter is operated under the underloading condition, device will be closed corresponding power switch pipe and synchronous rectifier, thereby reduces the driving loss in the power circuit, improves the underloading conversion efficiency.2. can detect in real time unnecessary Dead Time, then the line item of going forward side by side joins the length of Dead Time in the switching signal by two-way 8bit Data Control dead-zone circuit.Thereby minimize Dead Time, reduce the conduction loss that unnecessary Dead Time is introduced, improve system's conversion efficiency.
Description of drawings
The circuit structure block diagram of the high efficiency DC-DC converter of Fig. 1.
Fig. 2 power circuit structure chart.
The structured flowchart of Fig. 3 grid width control circuit 104.
The judgement waveform schematic diagram whether Fig. 4 power switch tube S W1 enables.
Fig. 5 dead-zone circuit structure chart.
The structured flowchart of Fig. 6 dead band prediction circuit.
The work wave schematic diagram of each signal in Fig. 7 dead band prediction circuit and the dead-zone circuit.
Embodiment
Below by embodiment, and by reference to the accompanying drawings, technical scheme of the present invention is described in further detail.
Embodiment:
Below in conjunction with drawings and Examples, the present invention is described in further detail.
Buck DC-DC converter among the present invention comprises power circuit and control circuit 101 two parts.Referring to Fig. 1, the circuit beyond the control circuit 101 is power circuit.
Referring to Fig. 1, the topology of power circuit is voltage-dropping type.Include power switch tube S W, synchronous rectifier SR and filtering feedback circuit 102.The input Vin of power circuit is the power input of DC-DC converter, and its output end vo ut is the power output end of DC-DC converter.
Referring to Fig. 2, above-mentioned power switch tube S W is by 5 P type metal-oxide-semiconductors that breadth length ratio is identical: SW4～SW0 forms side by side.The source electrode of 5 P type metal-oxide-semiconductors all links to each other with power input Vin, and drain electrode all is connected to switching node Vsw, grid respectively with the output port V of control circuit 101
DriveP＜4:0 〉Link to each other.Equally, above-mentioned synchronous rectifier SR is by 5 N-type metal-oxide-semiconductors that breadth length ratio is identical: SR4～SR0 forms side by side.The drain electrode of 5 N-type metal-oxide-semiconductors all is connected to switching node Vsw, and source electrode all is connected to ground, grid respectively with the output port V of control circuit 101
DriveN＜4:0 〉Link to each other.Be the normal operation of assurance circuit, all the time conducting of SW0 and SR0, SW4～SW1 and SR4～SR1 participates in the judgement whether circuit working depends on 104 pairs of loading conditions of grid width control circuit.Be operated in the stage of output current minimum when converter, SW4～SW1 and SR4～SR1 are in off state all the time.Be operated in the stage of output current maximum when converter, SW4～SW1 and SR4～SR1 all work, and ON time is determined by the pulse duration of grid control signal.
Above-mentioned filtering feedback circuit 102 includes inductance L, capacitor C
Out, resistance R 1 and R2.Wherein an end of inductance L is connected to switching node Vsw, and the other end is connected to the power output end Vout of DC-DC variator.Capacitor C
OutBe connected between output port Vout and the ground, resistance R 1 and R2 are connected in series between output port and the ground, and the output Vfb in the middle of R1 and R2 is connected to the input of pulse width modulation module in the control circuit 101.
Above-mentioned control circuit 101 adopts pulse-width-modulated mode.Referring to Fig. 1, control circuit 101 includes current detection circuit 103, grid width control circuit 104, logic control and gate driver circuit 105, pulse width modulation circuit 106, dead-zone circuit 107 and dead band prediction circuit 108 and forms.
Above-mentioned current detection circuit 103 detects the size of current by power switch pipe in real time, and be converted to voltage signal, and with the maintenance of sampling of the detected value of power switch pipe conduction period, thereby obtain the detection signal Vsense of reflected load size of current, then be input to grid width control circuit 104.The input of current detection circuit 103 is connected to the switching node Vsw of power circuit, and output Vsense is connected to the input Vsense of grid width control circuit 104.
Above-mentioned grid width control circuit 104 is used for the number arranged side by side of control external power pipe.Respective negative is current-carrying to have less channel dimensions simultaneously so that power tube can bear, and has so just dynamically reduced the grid parasitic capacitance of power switch pipe, thereby has reduced the driving loss under the underloading condition, obviously improves the light-load efficiency of system.Referring to Fig. 3, grid width control circuit 104 is comprised of reference voltage circuit 301, four comparator com1～com4 and logic subcircuit 302.Vsense is the load current detection signal of current detection circuit input, Vsense compares by four reference voltage V ref1～Vref4 that four comparator com1～com4 and reference voltage circuit 301 provide respectively, and comparative result determines respectively whether SW4～SW1 and SR4～SR1 participate in circuit working among the metal-oxide-semiconductor SW of power circuit and the SR.For the pipe of working, its control signal is the square-wave signal D that the pulse duration of dead-zone circuit output is modulated
SWAnd D
SRThe deterministic process whether 104 couples of power switch tube S W1 of grid width control circuit work can be referring to Fig. 4.Vsense is higher than Vref1 in during t1～t2, and Vcom1_out is high level, is equivalent to SW1 and enables, and illustrates that the load current size needs SW1 to join the transmission work of electric current.Through the processing of logic subcircuit, V
DriveP1The square-wave signal that pulse duration is modulated during t1～t2, and V in during t0～t1 and the t2～t3
DriveP1Be always high level, SW1 turn-offs.In like manner, SW4～SW2 and SR4～SR1 determine V in a comparable manner
DriveP＜4:2 〉And V
DriveN＜4:1 〉Waveform.For guaranteeing the circuit normal operation, so all the time conducting of SW0 and SR0 is D
SWAnd D
SRDirectly transfer G to
SWOAnd G
SROOutput to logic control and drive circuit 105, be converted at last the grid control signal V of SW0 and SR0
DrivePOAnd V
DriveNO
Above-mentioned logic control and gate driver circuit 105 are made of some gate level circuit and inverters commonly used, are mainly used in strengthening the driving force of switching signal, and its input signal is two-way 5bit data G
SW＜4:0 〉And G
SR＜4:0 〉Two-way 5bit output signal V
DriveP＜4:0〉and V
DriveN＜4:0〉directly drive corresponding power switch pipe and synchronous rectifier.
Above-mentioned pulse width modulation circuit 106 obtains adding Dead Time switching signal before, i.e. pulse width modulating signal Vpwm according to the fixing square-wave signal of the modulation of the output voltage feedback signal Vfb in power circuit pulsewidth.The input of pulse width modulation circuit 106 is the input Vfb of control circuit, and output Vpwm links to each other with the input of dead-zone circuit 107.
Above-mentioned dead-zone circuit 107 is used for adding the Dead Time of certain-length to switching signal, and include two passage groups: SW passage group and SR passage group, rising edge and the trailing edge with Vpwm postpones respectively.This section time of delay is exactly Dead Time, and time of delay length by the two-way 8bit data CTL_SW＜7:0 of dead band prediction circuit 108 outputs and CTL_SR＜7:0 control.Referring to Fig. 6,501 is SW passage group, includes delay circuit 503, comparator com_SW, forms with door and_SW and not gate Not_SW.502 is SW passage group, includes not gate Not_SR, delay circuit 504, comparator com_SR and forms with door and_SR.Delay circuit 503 is by electric capacity R
SW, capacitor C
SWO～C
SW7Form capacitor C with K switch 0～K7
SWO～C
SW7Connect respectively the conducting of K0～K7 and the 8bit data CTL_SW＜7:0 that turn-offs by prediction circuit 105 outputs with K switch 0～K7〉control.Capacitor C when the K0 conducting
SWOAnd link delay circuit, thus increased the time constant of delay circuit, so that increase time of delay, increased at last the Dead Time of switching signal.In like manner, the working method of K1～K7 also is that similarly the switch of conducting is more among K0～K7, and the Dead Time that adds in the switching signal is longer.The inhibit signal of delay circuit 503 output through comparator com_SW shaping after with Vpwm signal phase with, to eliminate the first delay circuit 503 to the impact of Vpwm signal trailing edge.After carrying out logical synchronization through not gate not_SW again with the signal of door and_SW output, obtain adding the switching signal D in dead band
SWThe operation principle of SR passage is also similar, and just not gate Not_SR is added to before the delay circuit, is used for the trailing edge of Vpwm is become rising edge.Obtain at last adding the switching signal D in dead band
SR
Above-mentioned dead band prediction circuit 108 detects the dead band that switching signal existed in this cycle.Then the optimum dead zone time length under the actual operating conditions is recorded to counter, the two-way 8bit data of counter output output to dead-zone circuit 107.Referring to Fig. 5, dead band prediction circuit 108 comprises that NOR gate Nor, delay circuit 601, the first shaping circuit 602, the second shaping circuit 603, the first counter 604 and the second counter 605 form.Two input signals are respectively the gate drive voltage V of node voltage Vsw and the 0th synchronous rectifier SR0
DriveNOVsw and V
DriveNOCarry out or non-after obtain Nor_out, Nor_out is through being Delay behind the delay circuit 601.Then in the moment of the rising edge after the Vsw shaping, if Delay is high level, then the first counter 604 subtracts 1, otherwise the first counter 604 adds 1; Equally, at V
DriveNORising edge after the shaping detects inhibit signal Delay, if Delay is high level, then the second counter 605 subtracts 1, otherwise the second counter 605 adds 1.When the circuit steady operation, the first counter 604 and the second counter 605 record respectively the Vpwm signal in the optimum dead zone time span that should add of rising edge and falling edge like this.
The work wave of each signal can be referring to Fig. 7 in dead band prediction circuit 108 and the dead-zone circuit 107, and Vpwm is the pulse width modulating signal of pulse width modulation module output.V
DrivePOAnd V
DriveNORespectively D
SWAnd D
SRSignal after the enhancing driving force.Vsw is node voltage.Nor_out is the output waveform of NOR gate Nor in the prediction circuit of dead band, and there is situation in the dead band in the display switch signal current period.Dead-zone circuit 107 has added dead band t according to the data in the first counter 604 at the Vpwm rising edge
D1Become D
SWData according in the second counter 605 have added dead band t at the Vpwm trailing edge
D2Become D
SRVsw and V in the dead band prediction circuit 108
DriveNOCarry out or non-after the Nor_out that obtains, the pulse among the Nor_out is the dead band that detects.1., 3. and 5. dead band wherein is by the control of the SW via set in the dead- zone circuit 107, and 2. and 4. the dead band is to be controlled by the SR via set in the dead-zone circuit 107.Delay is that Nor_out is through the output waveform behind the delay circuit 601.At Vsw rising edge place, Delay is high level, and then the first counter 604 in the dead-zone circuit 107 can subtract 1, this means that the time constant of delay circuit in the dead-zone circuit 107 reduces.So the dead band of T2 is 3. 1. narrow than the dead band of T1 among the Nor_out, one-period reduces some Dead Times like this, until Dead Time is when just very few, as the dead band 2., can't detect in the clock hopping edge of counter through the waveform after postponing, this moment, the second counter 605 can add 1, and Dead Time increases.So 4. 2. wide than the dead band in T1 cycle in the dead band of T2 in the cycle.Dynamic prediction is adjusted Dead Time length like this, so that the dead band length in the switching signal is in optimum length, has reduced unnecessary dead band waste.Such dead band prediction circuit is not subjected to the impact of other conditions of work in the circuit, only is concerned about whether dead band length minimizes.
The invention provides a kind of high efficiency DC-DC converter, the unstable direct voltage step-down of input also can be converted to more stable output dc voltage efficiently.Control circuit 101 in this device and the power switch tube S W in the power circuit and SR can be integrated in the chip of mancarried electronic aid, and the available discrete component of other parts of power circuit is placed on outside the chip.
Specific embodiment described herein only is to the explanation for example of the present invention's spirit.Those skilled in the art can make various modifications or replenish or adopt similar mode to substitute described specific embodiment, but can't depart from spirit of the present invention or surmount the defined scope of appended claims.
Claims (7)
1. an efficient voltage reducing type DC-DC converter is characterized in that, comprises power circuit and control circuit module (101); Wherein the input Vin of power circuit is the power input of DC-DC converter, and its output end vo ut is the power output end of DC-DC converter, the 5bit output V of control circuit module (101)
DriveP＜4:0〉be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in the power switch pipe group SW, the 5bit output V of control circuit module (101)
DriveN＜4:0〉be connected respectively to the input of power circuit, i.e. the grid of 5 groups of metal-oxide-semiconductors in the power switch pipe group SR, the output V of power circuit
SWLink to each other with the input of control circuit module (101), the output Vfb of power circuit links to each other with the input of control circuit module (101), the output V of power circuit
SWLink to each other with the input of control circuit module (101).
2. a kind of efficient voltage reducing type DC-DC converter according to claim 1 is characterized in that, described power circuit comprises power switch pipe group SW, synchronous rectifier group SR and filtering feedback circuit (102); The input of the drain terminal of the drain terminal of described power switch pipe group SW, power switch pipe group SW and filtering feedback circuit (10) is connected to the output V of power circuit jointly
SWDescribed power switch pipe group SW comprises five P type metal-oxide-semiconductors that breadth length ratio is identical, and the source electrode of five P type metal-oxide-semiconductors all links to each other with power input Vin, and drain electrode all is connected to the output V of power circuit
SW, grid respectively with the input V of power circuit
DriveP＜4:0〉link to each other; Described synchronous rectifier group SR comprises five N-type metal-oxide-semiconductors that breadth length ratio is identical, and the drain electrode of five power switch pipes all is connected to the output V of power circuit
SW, source electrode all is connected to ground, grid respectively with the input V of power circuit (102)
DriveN＜4:0〉link to each other.
3. a kind of efficient voltage reducing type DC-DC converter according to claim 2 is characterized in that, described filtering feedback circuit (102) comprises inductance L, capacitor C, resistance R 1 and R2; Wherein, an end of inductance L is connected to the output V of power circuit
SWThe other end is connected to the power output end Vout of DC-DC converter; Capacitor C is connected between output port of power source Vout and the ground; Resistance R 1 and R2 are connected in series between output port of power source Vout and the ground, draw the output Vfb of power circuit in the middle of R1 and R2.
4. a kind of efficient voltage reducing type DC-DC converter according to claim 3, it is characterized in that, described control circuit module (101) comprises current detection circuit (103), grid width control circuit (104), logic control and gate driver circuit (105), pulse width modulation circuit (106), dead-zone circuit (107) and dead band prediction circuit (108); The input of described current detection circuit (103) is the input V of control circuit module (101)
SW, the output Vsense of current detection circuit 103 is connected to the input of grid width control circuit (104), two input D of grid width control circuit (104)
SWAnd D
SRBe connected to the output of dead-zone circuit (107), the two-way 5bit output G of grid width control circuit (104)
SW＜4:0〉and G
SR＜＜4:0〉be connected respectively to the input of logic control and gate driver circuit (105), the two-way 5bit output of logic control and gate driver circuit (105) is the two-way 5bit output V of control circuit module (101)
DriveP＜4:0〉and V
DriveN＜4:0 〉; The input of pulse width modulation circuit (106) is the input Vfb of control circuit module (101), the output of pulse width modulation circuit (106) links to each other with the input Vpwm of dead-zone circuit (107), output Dsw and the D of dead-zone circuit (107)
SRBe connected respectively to the input of grid width control circuit (104), the two-way 8bit input CTL_SW＜7:0 of dead-zone circuit (107)〉and CTL_SR＜7:0 dead band prediction circuit (108) output that is connected to, two inputs of dead band prediction circuit (108) are respectively the input V of control circuit module (101)
SWRoad output voltage V with logic control and gate driver circuit (105)
DriveN0＜4:0 〉.
5. a kind of efficient voltage reducing type DC-DC converter according to claim 4, it is characterized in that, described grid width control circuit (104) comprises reference voltage electronic circuit (301), four comparator com1～com4 and logic subcircuit (302) form, the normal phase input end of four comparators all links to each other with the input Vsense of grid width control circuit (104), the inverting input of four comparators links to each other with the output Vref1～Vref4 of reference voltage electronic circuit (301) respectively, the input D of the output Vcom1_out～Vcom4_out of four comparators and grid width control circuit (104)
SWAnd D
SRBe the input of logic subcircuit (302), the special output G of the two-way 5bit of logic subcircuit (302)
SW＜4:0〉and G
SR＜4:0〉be the output of grid width control circuit (104).
6. a kind of efficient voltage reducing type DC-DC converter according to claim 5, it is characterized in that, institute's dead-zone circuit (107) comprises two dead band passages: SW dead band passage (501) and SR dead band passage (502), two passages link to each other side by side, input is the input Vpwm of dead-zone circuit (107), and output is the output D of dead-zone circuit (107)
SWAnd D
SR
Described SW passage group (501) comprise the first delay circuit (503), comparator com_SW, with door and_SW and not gate Not_SW; The input Vpwm of dead-zone circuit (107) links to each other with the input of the first delay circuit (503), the output of the first delay circuit (503) is connected to the normal phase input end of comparator com_SW, the output of comparator com_SW is connected to the input with door and_SW, be connected to the input of not gate Not_SW with the output of door and_SW, the output of not gate Not_SW is the output D of dead-zone circuit (107)
SW
Described SR passage group (502) comprise not gate Not_SR, the second delay circuit (504), comparator com_SR and with door and_SR; The input of the input Vpwm NAND gate Not_SR of dead-zone circuit (107) links to each other, the output of not gate Not_SR links to each other with the input of delay circuit second (504), the output of the second delay circuit (504) is connected to the normal phase input end of comparator com_SR, the output of comparator com_SR is connected to the input with door and_SR, is the output D of dead-zone circuit (107) with the output of door and_SR
SR
7. a kind of efficient voltage reducing type DC-DC converter according to claim 6, it is characterized in that, described dead band prediction circuit (108) comprises a NOR gate Nor, delay circuit (601), the first shaping circuit (602), the second shaping circuit (603), the first counter (604) and the second counter (605); Two input V of dead band prediction circuit (108)
SWAnd V
DriveN0Two inputs of ANDORNOTgate Nor link to each other, simultaneously, and input V
SWAlso the input with the first shaping circuit (602) links to each other, input V
DriveN0Also the input with the second shaping circuit 603 links to each other, and the output of the first shaping circuit (602) is connected to the input end of clock of the first counter (604), and the output of the second shaping circuit (603) is connected to the input end of clock of the second counter (605); The output of NOR gate Nor links to each other with the input of delay circuit (601), the data input pin of the first counter (604) and the second counter (605) links to each other with the output Delay of delay circuit (601), output CTL_SW＜the 7:0 of the 8bit output of the first counter (604) and dead band prediction circuit (108)〉link to each other the output CTL_SR＜7:0 of the 8bit output of the second counter (605) and dead band prediction circuit (108)〉link to each other.
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| CN104702104A (en) * | 2013-12-10 | 2015-06-10 | 展讯通信（上海）有限公司 | DC-DC (direct current-direct current) conversion device |
| CN106953507A (en) * | 2017-05-04 | 2017-07-14 | 广州金升阳科技有限公司 | A kind of buck converter synchronous rectification driving circuit and control method |
| CN108347168A (en) * | 2018-03-15 | 2018-07-31 | 广州金升阳科技有限公司 | A kind of time width detection circuit and its control method |
| CN110572035A (en) * | 2019-09-30 | 2019-12-13 | 重庆中易智芯科技有限责任公司 | Floating gate width self-adaptive switching logic circuit applied to PWM DC/DC |
| CN112054678A (en) * | 2020-08-28 | 2020-12-08 | 苏州浪潮智能科技有限公司 | System and method for optimizing server power supply based on input voltage |
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| CN110572035B (en) * | 2019-09-30 | 2021-05-14 | 重庆中易智芯科技有限责任公司 | Floating gate width self-adaptive switching logic circuit applied to PWM DC/DC |
| CN110572035A (en) * | 2019-09-30 | 2019-12-13 | 重庆中易智芯科技有限责任公司 | Floating gate width self-adaptive switching logic circuit applied to PWM DC/DC |
| CN113765415A (en) * | 2020-06-03 | 2021-12-07 | 宏碁股份有限公司 | Step-down converter |
| CN113765415B (en) * | 2020-06-03 | 2023-07-21 | 宏碁股份有限公司 | Step-down converter |
| CN112054678A (en) * | 2020-08-28 | 2020-12-08 | 苏州浪潮智能科技有限公司 | System and method for optimizing server power supply based on input voltage |
| CN117040511A (en) * | 2023-10-08 | 2023-11-10 | 深圳市思远半导体有限公司 | Switching circuit and method and DCDC |
| CN117040511B (en) * | 2023-10-08 | 2024-02-02 | 深圳市思远半导体有限公司 | Switching circuit and method and DCDC |
| CN117439398A (en) * | 2023-12-20 | 2024-01-23 | 成都市易冲半导体有限公司 | Dead time optimization circuit and method, control circuit thereof and push-pull output circuit |
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