CN113765415B

CN113765415B - Step-down converter

Info

Publication number: CN113765415B
Application number: CN202010493366.2A
Authority: CN
Inventors: 詹子增
Original assignee: Acer Inc
Current assignee: Acer Inc
Priority date: 2020-06-03
Filing date: 2020-06-03
Publication date: 2023-07-21
Anticipated expiration: 2040-06-03
Also published as: CN113765415A

Abstract

A buck converter, comprising: a bridge rectifier, a power switch, an output stage circuit, a first diode, a first inductor, and a detection and compensation circuit. The bridge rectifier can generate a rectification potential according to a first input potential and a second input potential. The power switch selectively couples the bridge rectifier to a ground potential according to a time Zhong Dianwei. The output stage circuit can generate an output potential. The first inductor is coupled between the detection and compensation circuit and the output stage circuit. The detection and compensation circuit may monitor and compare the rectified potential with the output potential. If the detected rectified potential is lower than the output potential, the detection and compensation circuit readjust the rectified potential so that the readjusted rectified potential is higher than or equal to the output potential.

Description

Step-down converter

Technical Field

The present invention relates to a buck converter, and more particularly to a buck converter with high conversion efficiency.

Background

Typically low wattage power supplies typically use buck converters to boost their power factor. However, in the conventional buck converter, if the input (rectified) potential is lower than the output potential, a problem of "Dead Zone" occurs, so that the whole circuit cannot operate and the conversion efficiency is reduced. In view of this, a completely new solution has to be proposed to overcome the dilemma faced by the prior art.

Disclosure of Invention

In a preferred embodiment, the present invention proposes a buck converter comprising: a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential; a power switch selectively coupling the bridge rectifier to a ground potential according to a time Zhong Dianwei; an output stage circuit for generating an output potential; a detection and compensation circuit for monitoring and comparing the rectified potential with the output potential; a first inductor coupled between the detection and compensation circuit and the output stage circuit; and a first diode coupled to the detection and compensation circuit and the first inductor; if the rectified potential is detected to be lower than the output potential, the detection and compensation circuit readjust the rectified potential so that the readjusted rectified potential is higher than or equal to the output potential.

Drawings

Fig. 1 is a schematic diagram showing a buck converter according to an embodiment of the invention.

Fig. 2 is a schematic diagram showing a buck converter according to an embodiment of the invention.

Fig. 3 is a potential waveform diagram showing the rectified potential of a conventional buck converter.

Fig. 4 is a potential waveform diagram showing the rectified potential of the buck converter according to an embodiment of the invention.

Wherein reference numerals are as follows:

100, 200: step-down converter

110, 210: bridge rectifier

120, 220: power switching device

130, 230: output stage circuit

160, 260: detection and compensation circuit

265: comparator with a comparator circuit

311, 312: dead zone

C1: first capacitor

C2: second capacitor

D1: first diode

D2: second diode

D3: third diode

D4: fourth diode

D5: fifth diode

D6: sixth diode

D7: seventh diode

L1: first inductor

L2: second inductor

M1: first transistor

M2: second transistor

N1: first node

N2: second node

And N3: third node

N4: fourth node

N5: fifth node

N6: fifth node

NIN1: first input node

NIN2: second input node

NOUT: output node

R1: resistor

VA: clock potential

VC: controlling potential

VIN1: a first input potential

VIN2: a second input potential

VOUT: output potential

VR: rectifying potential

VSS: ground potential

Detailed Description

The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments of the invention.

Certain terms are used throughout the description and claims to refer to particular components. Those of ordinary skill in the art will appreciate that a hardware manufacturer may refer to the same element by different names. The description and claims do not take the difference in name as a way of distinguishing between elements, but rather take the difference in function of the elements as a criterion for distinguishing between them. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "substantially" means that within an acceptable error range, a person skilled in the art can solve the technical problem within a certain error range, and achieve the basic technical effect. In addition, the term "coupled" as used herein includes any direct or indirect electrical connection. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Fig. 1 is a schematic diagram illustrating a buck converter 100 according to an embodiment of the invention. For example, the buck converter 100 may be applied to a power supply, but is not limited thereto. As shown in fig. 1, the buck converter 100 includes: a bridge rectifier 110, a power switch 120, an output stage 130, a first diode D1, a first inductor L1, and a detection and compensation circuit 160. It should be noted that although not shown in fig. 1, the buck converter 100 may also include other elements, such as: a voltage stabilizer or (and) a negative feedback circuit.

The bridge rectifier 110 generates a rectified voltage VR according to a first input voltage VIN1 and a second input voltage VIN 2. The first input potential VIN1 and the second input potential VIN2 can both be from an external input power source, wherein an ac voltage with any frequency and any amplitude can be formed between the first input potential VIN1 and the second input potential VIN 2. For example, the frequency of the ac voltage may be about 50Hz or 60Hz, and the square root of the ac voltage may be about 90V to 264V, but is not limited thereto. The power switch 120 selectively couples the bridge rectifier 110 to a ground potential VSS (e.g., 0V) according to a voltage of Zhong Dianwei VA. The clock voltage VA is maintained at a constant voltage when the buck converter 100 is initialized, and a periodic clock waveform is provided after the buck converter 100 enters a normal use phase. For example, if the clock voltage VA is at a high logic level (e.g., logic "1"), the power switch 120 couples the bridge rectifier 110 to the ground voltage VSS (i.e., the power switch 120 may approximate a short circuit path); conversely, if the clock voltage VA is at a low logic level (e.g., logic "0"), the power switch 120 does not couple the bridge rectifier 110 to the ground voltage VSS (i.e., the power switch 120 may approximate an open path). The output stage 130 may generate an output voltage VOUT, which may be substantially a dc voltage. The first inductor L1 is coupled between the detection and compensation circuit 160 and the output stage circuit 130. The first diode D1 is coupled to both the detection and compensation circuit 160 and the first inductor L1. The detection and compensation circuit 160 is used to monitor and compare the rectified voltage VR with the output voltage VOUT. In detail, if the rectified voltage VR is detected to be lower than the output voltage VOUT, the detecting and compensating circuit 160 may readjust the rectified voltage VR, so that the readjusted rectified voltage VR is higher than or equal to the output voltage VOUT; otherwise, if the rectified voltage VR is detected to be higher than or equal to the output voltage VOUT, the detection and compensation circuit 160 will not readjust the rectified voltage VR. With this design, since the detection and compensation circuit 160 can ensure that the rectifying voltage VR is higher than or equal to the output voltage VOUT, no dead zone occurs in all operation cycles of the buck converter 100, so that the conversion efficiency of the buck converter 100 can be greatly improved.

The following embodiments will describe the detailed structure and operation of the buck converter 100. It is to be understood that the drawings and descriptions are proffered by way of example only and are not intended to limit the scope of the invention.

Fig. 2 is a schematic diagram illustrating a buck converter 200 according to an embodiment of the invention. In the embodiment of fig. 2, the buck converter 200 has a first input node NIN1, a second input node NIN2, and an output node NOUT, and includes a bridge rectifier 210, a power switch 220, an output stage circuit 230, a first diode D1, a first inductor L1, and a detection and compensation circuit 260. The first input node NIN1 and the second input node NIN2 of the buck converter 200 can respectively receive a first input voltage VIN1 and a second input voltage VIN2 from an external input power source, wherein an ac voltage with an arbitrary frequency and an arbitrary amplitude can be formed between the first input voltage VIN1 and the second input voltage VIN 2. The output node NOUT of the buck converter 200 may output an output voltage VOUT, which may be substantially a DC voltage.

The bridge rectifier 210 includes a second diode D2, a third diode D3, a fourth diode D4, and a fifth diode D5. The anode of the second diode D2 is coupled to the first input node NIN1, and the cathode of the second diode D2 is coupled to a first node N1 to output a rectifying potential VR. The anode of the third diode D3 is coupled to the second input node NIN2, and the cathode of the third diode D3 is coupled to the first node N1. The fourth diode D4 has an anode and a cathode, wherein the anode of the fourth diode D4 is coupled to a second node N2, and the cathode of the fourth diode D4 is coupled to the first input node NIN1. The anode of the fifth diode D5 is coupled to the second node N2, and the cathode of the fifth diode D5 is coupled to the second input node NIN2.

The power switch 220 includes a first transistor M1, which can be regarded as a main switch of the buck converter 200. The first transistor M1 may be an N-type mosfet. The control terminal of the first transistor M1 is for receiving a signal Zhong Dianwei VA, the first terminal of the first transistor M1 is coupled to the second node N2, and the second terminal of the first transistor M1 is coupled to a ground potential VSS (e.g., 0V). For example, the clock voltage VA may be maintained at a constant voltage (e.g., the ground voltage VSS) during the initialization of the buck converter 200, and a periodic clock waveform may be provided after the buck converter 200 enters a normal use phase. In some embodiments, if the clock potential VA is at a high logic level, the first transistor M1 will be enabled; conversely, if the clock VA is at a low logic level, the first transistor M1 is disabled.

The anode of the first diode D1 is coupled to the ground potential VSS, and the cathode of the first diode D1 is coupled to a third node N3.

The output stage 230 includes a first capacitor C1. The first terminal of the first capacitor C1 is coupled to the output node NOUT, and the second terminal of the first capacitor C1 is coupled to the ground potential VSS.

The first inductor L1 may be considered as a buck inductor of the buck converter 200. The first end of the first inductor L1 is coupled to the third node N3, and the second end of the first inductor L1 is coupled to the output node NOUT.

The detection and compensation circuit 260 includes: a comparator 265, a second transistor M2, a sixth diode D6, a seventh diode D7, a resistor R1, a second inductor L2, and a second capacitor C2. Comparator 265 may be implemented with an operational amplifier. In detail, the positive input of the comparator 265 is for receiving the output voltage VOUT, the negative input of the comparator 265 is for receiving the rectified voltage VR, and the output of the comparator 265 is for outputting a control voltage VC. For example, if the rectified voltage VR is lower than the output voltage VOUT, the comparator 265 will output the control voltage VC with a high logic level; conversely, if the rectified voltage VR is higher than or equal to the output voltage VOUT, the comparator 265 will output the control voltage VC with a low logic level.

The second transistor M2 may be an nmos field effect transistor. The control terminal of the second transistor M2 is for receiving the control potential VC, the first terminal of the second transistor M2 is coupled to a fourth node N4, and the second terminal of the second transistor M2 is coupled to a fifth node N5. In some embodiments, if the control potential VC is a high logic level, the second transistor M2 will be enabled; conversely, if the control potential VC is at a low logic level, the second transistor M2 will be disabled.

The anode of the sixth diode D6 is coupled to the fourth node N4, and the cathode of the sixth diode D6 is coupled to the first node N1. The first end of the resistor R1 is coupled to the first node N1, and the second end of the resistor R1 is coupled to the fifth node N5.

The first end of the second inductor L2 is coupled to the fifth node N5, and the second end of the second inductor L2 is coupled to the third node N3. The first terminal of the second capacitor C2 is coupled to the fifth node N5, and the second terminal of the second capacitor C2 is coupled to a sixth node N6. The anode of the seventh diode D7 is coupled to the sixth node N6, and the cathode of the seventh diode D7 is coupled to the third node N3. In some embodiments, the second inductor L2 is formed on the same core as the first inductor L1, such that the second inductor L2 and the first inductor L1 may be coupled to each other.

In some embodiments, the principle of operation of buck converter 200 may be as follows. In an initial mode, the buck converter 200 does not receive the first input voltage VIN1 and the second input voltage VIN2, and the clock voltage VA is maintained at a low logic level, so the first transistor M1 and the second transistor M2 are both disabled, and the first diode D1 and the seventh diode D7 are both turned off. Then, after the buck converter 200 has received the first input voltage VIN1 and the second input voltage VIN2, the buck converter 200 can alternately operate in a first mode, a second mode, and a third mode.

In the first mode, the clock voltage VA is at a high logic level to enable the first transistor M1, and the rectifying voltage VR is higher than or equal to the output voltage VOUT, so the control voltage VC is at a low logic level to disable the second transistor M2. At this time, the first diode D1 and the seventh diode D7 are both in the off state, and the first inductor L1, the second inductor L2, and the second capacitor C2 are all gradually storing energy. It should be noted that, since the seventh diode D7 is in an open state, the second capacitor C2 does not resonate with the second inductor L2, and any resonant voltage or resonant energy does not affect the operation of the buck converter 200.

In the second mode, the clock voltage VA is at a low logic level to disable the first transistor M1, and the rectifying voltage VR is higher than or equal to the output voltage VOUT, so the control voltage VC is at a low logic level to disable the second transistor M2. At this time, the first diode D1 is in a pass state, the seventh diode D7 is in an off state, the second inductor L2 and the second capacitor C2 gradually store energy, and the first inductor L1 gradually releases energy to the first capacitor C1.

In the fourth mode, the rectified voltage VR is lower than the output voltage VOUT regardless of whether the clock voltage VA is at a high logic level or a low logic level, so the control voltage VC is at a high logic level to enable the second transistor M2. At this time, the buck converter 200 is in an abnormal operation state, and the detection and compensation circuit 260 will automatically readjust the rectification voltage VR. In detail, the energy previously stored in the second capacitor C2 can be transferred to the first node N1 via the enabled second transistor M2 and the turned-on sixth diode D6 to pull up the level of the rectifying potential VR above the output potential VOUT. In addition, the second inductor L2 can supplement energy to the second capacitor C2 to maintain the rectified voltage VR at a stable level. Eventually, the buck converter 200 automatically returns to the normal operation state.

Fig. 3 is a potential waveform diagram showing the rectified potential VR of the conventional buck converter. If the detection and compensation circuit 260 is not used, at least two dead zones 311, 312 will appear in each operation cycle (i.e., when the rectified voltage VR is lower than the output voltage VOUT) in the conventional buck converter, which will negatively affect the conversion efficiency of the conventional buck converter.

Fig. 4 is a potential waveform diagram showing the rectified potential VR of the buck converter 200 according to an embodiment of the invention. If the detection and compensation circuit 260 is already added to the buck converter 200, no dead zone will occur in all operation cycles of the buck converter 200 because the rectified voltage VR is constantly higher than the output voltage VOUT. According to the actual measurement result, the conversion efficiency of the buck converter 200 using the detection and compensation circuit 260 can be greatly improved.

In some embodiments, the component parameters of buck converter 200 may be as follows. The capacitance value of the first capacitor C1 may be between 646 to 714 μf, preferably 680 μf. The capacitance value of the second capacitor C2 may be between 108 and 132 μf, preferably 120 μf. The inductance value of the first inductor L1 may be between 90.25 muh and 99.75 muh, preferably 95 muh. The inductance value of the second inductor L2 may be between 36 μh and 44 μh, preferably 40 μh. The resistance value of the resistor R1 may be between 0.9kΩ and 1.1kΩ, preferably 1kΩ. The switching frequency of the clock potential VA may be about 65kHz. The above parameter ranges are derived from a plurality of experimental results, which help to optimize the conversion efficiency of the buck converter 200.

The invention provides a novel buck converter, which comprises a detection and compensation circuit. Based on actual measurements, the dead zone in each operating cycle of the buck converter can be completely eliminated using the design described above. In general, the present invention can effectively improve the overall conversion efficiency of the buck converter, so that the buck converter is suitable for various electronic devices.

It should be noted that the above-mentioned potential, current, resistance, inductance, capacitance, and other parameters are not limitations of the present invention. The designer can adjust these settings according to different needs. The buck converter of the present invention is not limited to the states shown in fig. 1-4. The present invention may include only any one or more features of any one or more of the embodiments of fig. 1-4. In other words, not all of the illustrated features need be implemented in the buck converter of the present invention at the same time. Although the embodiments of the present invention are exemplified by using mosfet, the present invention is not limited thereto, and those skilled in the art can use other kinds of transistors, such as: junction field effect transistors, or fin field effect transistors, and the like, without affecting the effect of the present invention.

While the invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A buck converter, comprising:

a bridge rectifier for generating a rectified potential according to a first input potential and a second input potential;

a power switch selectively coupling the bridge rectifier to a ground potential according to a time Zhong Dianwei;

an output stage circuit for generating an output potential;

a detection and compensation circuit for monitoring and comparing the rectified potential with the output potential;

a first inductor coupled between the detection and compensation circuit and the output stage circuit; and

a first diode coupled to the detection and compensation circuit and the first inductor;

if the rectified potential is detected to be lower than the output potential, the detection and compensation circuit readjust the rectified potential so that the readjusted rectified potential is higher than or equal to the output potential.

2. The buck converter of claim 1 wherein the bridge rectifier includes:

a second diode having an anode and a cathode, wherein the anode of the second diode is coupled to a first input node to receive the first input potential, and the cathode of the second diode is coupled to a first node to output the rectified potential;

a third diode having an anode and a cathode, wherein the anode of the third diode is coupled to a second input node to receive the second input potential, and the cathode of the third diode is coupled to the first node;

a fourth diode having an anode and a cathode, wherein the anode of the fourth diode is coupled to a second node and the cathode of the fourth diode is coupled to the first input node; and

a fifth diode having an anode and a cathode, wherein the anode of the fifth diode is coupled to the second node and the cathode of the fifth diode is coupled to the second input node.

3. The buck converter of claim 2 wherein the power switch includes:

the first transistor is provided with a control end, a first end and a second end, wherein the control end of the first transistor is used for receiving the clock potential, the first end of the first transistor is coupled to the second node, and the second end of the first transistor is coupled to the ground potential.

4. The buck converter according to claim 2, wherein the first diode has an anode and a cathode, the anode of the first diode being coupled to the ground potential, and the cathode of the first diode being coupled to a third node.

5. The buck converter according to claim 4, wherein the output stage circuit includes:

a first capacitor having a first end and a second end, wherein the first end of the first capacitor is coupled to an output node to output the output potential, and the second end of the first capacitor is coupled to the ground potential.

6. The buck converter according to claim 5, wherein the first inductor has a first end and a second end, the first end of the first inductor being coupled to the third node, and the second end of the first inductor being coupled to the output node.

7. The buck converter according to claim 4, wherein said detection and compensation circuit includes:

the comparator is provided with a positive input end, a negative input end and an output end, wherein the positive input end of the comparator is used for receiving the output potential, the negative input end of the comparator is used for receiving the rectifying potential, and the output end of the comparator is used for outputting a control potential.

8. The buck converter according to claim 7, wherein said detection and compensation circuit further includes:

the second transistor is provided with a control end, a first end and a second end, wherein the control end of the second transistor is used for receiving the control potential, the first end of the second transistor is coupled to a fourth node, and the second end of the second transistor is coupled to a fifth node.

9. The buck converter according to claim 8, wherein said detection and compensation circuit further includes:

a sixth diode having an anode and a cathode, wherein the anode of the sixth diode is coupled to the fourth node and the cathode of the sixth diode is coupled to the first node; and

a resistor having a first end and a second end, wherein the first end of the resistor is coupled to the first node and the second end of the resistor is coupled to the fifth node.

10. The buck converter according to claim 9, wherein said detection and compensation circuit further includes:

a second inductor having a first end and a second end, wherein the first end of the second inductor is coupled to the fifth node, and the second end of the second inductor is coupled to the third node;

a second capacitor having a first end and a second end, wherein the first end of the second capacitor is coupled to the fifth node, and the second end of the second capacitor is coupled to a sixth node; and

a seventh diode having an anode and a cathode, wherein the anode of the seventh diode is coupled to the sixth node and the cathode of the seventh diode is coupled to the third node.