CN103367341A - IGBT (Insulated Gate Bipolar Translator) lining plate structure - Google Patents
IGBT (Insulated Gate Bipolar Translator) lining plate structure Download PDFInfo
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- CN103367341A CN103367341A CN2013102780501A CN201310278050A CN103367341A CN 103367341 A CN103367341 A CN 103367341A CN 2013102780501 A CN2013102780501 A CN 2013102780501A CN 201310278050 A CN201310278050 A CN 201310278050A CN 103367341 A CN103367341 A CN 103367341A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4846—Connecting portions with multiple bonds on the same bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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Abstract
The invention discloses an IGBT (Insulated Gate Bipolar Translator) lining plate structure, which comprises a lining plate, and lining plate gate electrode circuits, an IGBT chip, an FRD (Fast Recovery Diode) chip and a bus bar welding area which are arranged on the lining plate, wherein the lining plate gate circuits are positioned on both sides of the lining plate; the bus bar welding area is positioned in the middle area of the lining plate; and the IGBT chip and the FRD chip are positioned between the bus bar welding area and the lining plate gate electrode circuit. The IGBT lining plate structure has the advantages of simple and compact structure, low cost, more uniform distribution of the chips in an entire module range, simplification of the lining plate circuit design, increase in the encapsulating process efficiency, and the like.
Description
Technical field
The present invention is mainly concerned with the board design field, refers in particular to a kind of IGBT lining plate structure.
Background technology
As shown in Figure 1, have now in the employed lining plate structure of power IGBT both at home and abroad at present, liner plate 1 is generally rectangle, symmetrical two igbt chips 3 of the outermost of rectangle liner plate 1 and a FRD chip 4, the centre of liner plate 1 is various circuit regions 6, wherein IGBT is the abbreviation of Insulated Gate Bipolar Transistor, i.e. igbt; FRD is the abbreviation of Freewheel recover diode, i.e. fast recovery diode.The advantage of this structure is when realizing circuit function, image symmetrical, compact in design.But it is own that this design only is confined to liner plate 1, and ignored symmetry and the uniformity of whole module.As shown in Figure 2, for the module placement schematic diagram after liner plate 1 encapsulation, can see that the lateral separation L between inside chip is very large on the same liner plate 1, but the spacing H of 1 chip of adjacent liner plates is but very little.Chip can generate heat in switching process in a large number, and strong thermal coupling can appear in these next-door neighbours' chip chamber, finally has influence on the hot property of module.Referring to shown in Figure 3, be the thermal map of above-mentioned modular structure emulation, can see that the most obvious chip of thermal coupling is not 4 igbt chips 3 on the same liner plate 1, be 4 igbt chips 3 of adjacent liner plates on the contrary.Therefore, necessary in the layout of module aspect consideration chip on liner plate 1, to improve the module heat dissipating ability.
As shown in Figure 4, be common liner plate layout, can see that liner plate intermediate circuit layout is complicated, is unfavorable for simplifying packaging technology.Comprised in the circuit region 6 at liner plate 1 middle part that busbar connects welding zone 5, chip gate pole bonding region, chip emitter bonding region, spring wire weld zone etc., this has just increased the difficulty of packaging technology.Various circuit are crisscross, increased the interference between adjacent circuit.In addition, because liner plate 1 is standard size, the circuit region area is limited so that the bonding zone is narrow, can't be on liner plate tangent line, may affect the reliability of chip.
Summary of the invention
The technical problem to be solved in the present invention just is: for the technical problem that prior art exists, the invention provides a kind of simple and compact for structure, with low cost, can make chip in whole module scope, more evenly distribute, simplify the IGBT lining plate structure of liner plate circuit design, raising packaging technology efficient.
For solving the problems of the technologies described above, the present invention by the following technical solutions:
A kind of IGBT lining plate structure, the liner plate gate circuit, igbt chip, FRD chip and the busbar that comprise liner plate and be arranged on the liner plate connect welding zone, described liner plate gate circuit is positioned at the both sides on the liner plate, described busbar connects the central region that welding zone is positioned at liner plate, and described igbt chip, FRD chip connect between welding zone and the liner plate gate circuit at busbar.
As a further improvement on the present invention:
Along described liner plate vertically, two described igbt chips are arranged in order, described FRD chip is positioned at after the igbt chip.
Along described liner plate vertically, described FRD chip is arranged at the centre of two igbt chips.
Outermost is symmetrical arranged the gate lead bonding region on the described liner plate.
Described liner plate medium position place also is provided with spring wire weld zone and emitter bonding region.
Compared with prior art, the invention has the advantages that: IGBT lining plate structure of the present invention, simple and compact for structure, with low cost, chip more evenly distributes in whole module, is conducive to reduce the module thermal resistance, improves the reliability of module.Emitter and gate pole are respectively at chip both sides lead-in wire among the present invention, and the circuit that can reduce between gate pole and the emitter disturbs, and has also reduced the distance of gate lead simultaneously.The present invention has increased emitter bonding zone, can be at the liner plate tangent line, avoid that tangent line improves the stability of bonding technology to the damage of chip on the chip.
Description of drawings
Fig. 1 is the principle schematic of lining plate structure in the prior art.
Fig. 2 is the existing structural principle schematic diagram of lining plate structure when module is used.
Fig. 3 is the principle schematic of existing lining plate structure heat distribution when carrying out emulation after module is used.
Fig. 4 is the schematic layout pattern of existing liner plate.
Fig. 5 is the principle schematic of lining plate structure of the present invention.
Fig. 6 is the structural principle schematic diagram of lining plate structure of the present invention when module is used.
The principle schematic of Fig. 7 heat distribution when to be lining plate structure of the present invention carry out emulation after module is used.
Fig. 8 is the in another embodiment principle schematic of lining plate structure of the present invention.
Marginal data:
1, liner plate; 2, liner plate gate circuit; 3, igbt chip; 4, FRD chip; 5, busbar connects welding zone; 6, circuit region.
Embodiment
Below with reference to Figure of description and specific embodiment the present invention is described in further details.
As shown in Figure 5, a kind of IGBT lining plate structure of the present invention comprises that liner plate 1, liner plate gate circuit 2, igbt chip 3, FRD chip 4 and busbar connect welding zone 5; Liner plate 1 is used for carries chips, and realizes that the circuit of chip chamber connects.Liner plate gate circuit 2 is two and is positioned at both sides on the liner plate 1, and busbar connects the central region that welding zone 5 is positioned at liner plate 1, and igbt chip 3, FRD chip 4 connect between welding zone 5 and the liner plate gate circuit 2 at busbar.Covering the copper figure and going between among this figure on the liner plate connects the annexation that just is used for illustrating various piece on the liner plate, do not represent actual design.The present invention has increased the horizontal spacing of chip on the adjacent liner plates 1 by liner plate gate circuit 2 is designed in the both sides of liner plate 1, has reduced the thermal coupling between adjacent chips, has improved the heat-sinking capability of chip.
In the present embodiment, along liner plate 1 vertically, after two igbt chips 3 are arranged in order, arrange again a FRD chip 4.
In the present embodiment, outermost is symmetrical arranged the gate lead bonding region on liner plate 1.
In the present embodiment, busbar meets welding zone 5 residing liner plates 1 medium position place and also is provided with spring wire weld zone and emitter bonding region.
Be appreciated that in other embodiments, can also as shown in Figure 8, FRD chip 4 be put into the centre of two igbt chips 3.
As shown in Figure 6, be the schematic layout pattern of lining plate structure of the present invention when substrate is used.As shown in Figure 7, be the heat distribution schematic diagram of lining plate structure of the present invention when carrying out modular simulation.Can see, lining plate structure of the present invention not only can reduce the maximum junction temperature of module, and has reduced the maximum temperature difference of chip chamber, and the chip internal temperature is also more even.
When concrete the application, first with chip and liner plate 1 welding, namely by welding the collector electrode of a plurality of chips is connected to the collector circuit district of liner plate 1.Then, with liner plate 1 and chip lead bonding, namely realize that by Bonding the gate pole of a plurality of chips, emitter link to each other respectively with gate circuit and the emitter circuit of liner plate 1.Next, with liner plate 1 and busbar and spring wire welding, namely by the welding of liner plate 1 with busbar, realize that the collector and emitter of 1 of liner plate is interconnected respectively; Be connected with PCB by the gate pole of spring wire with liner plate 1, realize that the gate pole of each chip in the module is interconnected.At last, gate electrode resistance is welded on the PCB, wherein PCB is the abbreviation of Print circuit board, is used for as electronic devices and components provide support, and realizes the circuit interconnects of electronic devices and components.
Below only be preferred implementation of the present invention, protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art, the some improvements and modifications not breaking away under the principle of the invention prerequisite should be considered as protection scope of the present invention.
Claims (5)
1. IGBT lining plate structure, the liner plate gate circuit (2), igbt chip (3), FRD chip (4) and the busbar that comprise liner plate (1) and be arranged on the liner plate (1) connect welding zone (5), it is characterized in that, described liner plate gate circuit (2) is positioned at the both sides on the liner plate (1), described busbar connects the central region that welding zone (5) is positioned at liner plate 1, and described igbt chip (3), FRD chip (4) are positioned at busbar and connect between welding zone (5) and the liner plate gate circuit (2).
2. IGBT lining plate structure according to claim 1 is characterized in that, along described liner plate (1) vertically, two described igbt chips (3) are arranged in order, described FRD chip (4) is positioned at igbt chip (3) afterwards.
3. IGBT lining plate structure according to claim 1 is characterized in that, along described liner plate (1) vertically, described FRD chip (4) is arranged at the centre of two igbt chips (3).
4. according to claim 1 and 2 or 3 described IGBT lining plate structures, it is characterized in that, the upper outermost of described liner plate (1) is symmetrical arranged the gate lead bonding region.
5. according to claim 1 and 2 or 3 described IGBT lining plate structures, it is characterized in that, described liner plate (1) medium position place also is provided with spring wire weld zone and emitter bonding region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102780501A CN103367341A (en) | 2013-07-04 | 2013-07-04 | IGBT (Insulated Gate Bipolar Translator) lining plate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102780501A CN103367341A (en) | 2013-07-04 | 2013-07-04 | IGBT (Insulated Gate Bipolar Translator) lining plate structure |
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| Publication Number | Publication Date |
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| CN103367341A true CN103367341A (en) | 2013-10-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013102780501A Pending CN103367341A (en) | 2013-07-04 | 2013-07-04 | IGBT (Insulated Gate Bipolar Translator) lining plate structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304619A (en) * | 2014-05-28 | 2016-02-03 | 株洲南车时代电气股份有限公司 | IGBT lining board structure and preparation method thereof |
| CN110010596A (en) * | 2019-03-28 | 2019-07-12 | 西安交通大学 | A kind of multi-chip parallel power module encapsulating structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020038873A1 (en) * | 2000-09-29 | 2002-04-04 | Michiaki Hiyoshi | Semiconductor device including intermediate wiring element |
| US20090015992A1 (en) * | 2006-02-17 | 2009-01-15 | Kabushiki Kaisha Yaskawa Denki | Power conversion apparatus with bus bar |
| CN102569276A (en) * | 2012-02-14 | 2012-07-11 | 株洲南车时代电气股份有限公司 | Insulated gate bipolar transistor (IGBT) module |
-
2013
- 2013-07-04 CN CN2013102780501A patent/CN103367341A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020038873A1 (en) * | 2000-09-29 | 2002-04-04 | Michiaki Hiyoshi | Semiconductor device including intermediate wiring element |
| US20090015992A1 (en) * | 2006-02-17 | 2009-01-15 | Kabushiki Kaisha Yaskawa Denki | Power conversion apparatus with bus bar |
| CN102569276A (en) * | 2012-02-14 | 2012-07-11 | 株洲南车时代电气股份有限公司 | Insulated gate bipolar transistor (IGBT) module |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105304619A (en) * | 2014-05-28 | 2016-02-03 | 株洲南车时代电气股份有限公司 | IGBT lining board structure and preparation method thereof |
| CN110010596A (en) * | 2019-03-28 | 2019-07-12 | 西安交通大学 | A kind of multi-chip parallel power module encapsulating structure |
| CN110010596B (en) * | 2019-03-28 | 2020-11-10 | 西安交通大学 | Packaging structure for multi-chip parallel power module |
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Application publication date: 20131023 |