CN103364716B - Data sink and its method of testing - Google Patents
Data sink and its method of testing Download PDFInfo
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- CN103364716B CN103364716B CN201310115795.6A CN201310115795A CN103364716B CN 103364716 B CN103364716 B CN 103364716B CN 201310115795 A CN201310115795 A CN 201310115795A CN 103364716 B CN103364716 B CN 103364716B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
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- General Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
A kind of data receiver device includes：Logic unit, is configured as producing test mode signal, test result signal is received in test pattern, and in test pattern, test mode signal and test result signal is compared to perform test.Data sink also includes：System frequency controls circuit, is configured as being multiplied by reference clock signal with the multiplication factor received from logic unit, and export test clock signal；Output end, is configured as serializing test mode signal based on test clock signal, and output signal output；Input, is configured as recovering data-signal and data clock signal from input signal based on output signal, and serial parallel conversion is carried out to data-signal based on data clock signal, and by test result signal output to logic unit.
Description
Technical field
It is required that being submitted to the 10-2012-0035127 Korean Patents Shen of Korean Intellectual Property Office on April 4th, 2012
Priority please, its disclosure is herein incorporated by all references.
Background technology
The embodiment of present inventive concept is related to the data receiver device and its phase of selftest function built in a kind of include
The method of pass.
Built-in selftest (BIST) is a kind of test, in the test, and chip determines whether it has operation in itself
Failure.BIST functions are considered as being critically important for the performance for verifying the chip researched and developed in large-scale production.BIST can be examined
Look into other running parameters of bit error rate (BER), frequency and chip.
The BIST functions of chip are obtained in chip by the way that BIST functional blocks are integrated into.Now, it is bag according to the chip
Including the transponder chip of both transmitters and receivers, the only chip including transmitter still only includes the chip of receiver,
The realization of BIST functional blocks is different.
In transponder chip and only in the case of the chip including transmitter, in the case where not increasing the area of chip,
BIST functional blocks can be integrated.On the other hand, in the case where only including the chip (that is, receiver chip) of receiver,
In terms of chip area and design resource, the integrated of BIST functional blocks is infeasible or cost is too high.
Therefore, to realize BIST functions for receiver chip, including transmitter phased lock loop (PLL), serialization
The transmitter of device and output driver may be mounted to that in receiver chip.The PLL of transmitter specifically includes multiple cell blocks, and
Occupy big area.Therefore, because transmitter PLL is unrelated with the original function of receiver chip, therefore the integrated of it is generated
The expenditure of labo r resources is designed, and increases chip area.
Selectively, transmitter may be mounted to that outside receiver chip, and can be by between transmitters and receivers
Communication perform BIST.In this case, the offer of additional design block can be provided, but receiver can not perform test in itself,
And perform test in package level rather than wafer scale.In addition, the cost increase tested in large-scale production.
The content of the invention
Connect according to some embodiments of present inventive concept there is provided a kind of data operated in test pattern and general modfel
Receive device device.The data receiver device includes：Logic unit, is configured as detecting the current operation of data receiver device
Pattern simultaneously produces test mode signal, test result signal is received in test pattern, and in test pattern, will test mould
Formula signal is compared to perform test with test result signal.Data sink also includes：System frequency control circuit, by with
It is set to and reference clock signal is multiplied by with the multiplication factor received from logic unit, and exports test clock signal；Output end, by with
It is set to and test mode signal is serialized based on test clock signal, and passes through output pin output signal output；It is defeated
Enter end, be configured as recovering data-signal and data clock signal, base from the input signal of input pin based on output signal
Serial parallel conversion is carried out to data-signal in data clock signal, and by test result signal output to logic unit.
Include logic unit and video system FREQUENCY CONTROL there is provided one kind according to some other embodiments of present inventive concept
The numeric display unit of circuit, the numeric display unit is configured as operating in general modfel and shown to perform digital video
Processing, and be configured as operating in test pattern performing built-in selftest (BIST) processing.Numeric display unit is also wrapped
Include：Output end, is configured as serializing test mode signal based on test clock signal, and output signal output；
Input, is configured as recovering data-signal and data clock signal from input signal based on output signal, during based on data
Clock data signal signal carries out serial parallel conversion, and by test result signal output to logic unit.In test pattern, patrol
Volume unit is configured as producing test mode signal, receives test result signal, and by test mode signal and test result
Signal is compared to perform BIST processing.And in test pattern, video system frequency control circuit be configured as with from
The multiplication factor that logic unit is received is multiplied by reference clock signal, and exports test clock signal.
According to some other embodiments of present inventive concept there is provided a kind of method of testing of data receiver device, wherein,
The current mode that methods described includes detection data receiver device is test pattern or general modfel.According to detecting
Current mode is test pattern, and method of testing also includes producing test mode signal and corresponding with test mode signal pre-
Determine multiplication factor, be multiplied by reference clock signal by using multiplication factor to produce test clock signal, based on test clock signal
Test mode signal is serialized, by driving the test mode signal serialized come output signal output, based on test
Mode signal equalizing input signal, recovers data-signal and data clock signal, by based on data from equalizing input signal
Clock signal carries out serial parallel conversion to data-signal to produce test result signal, and by by test result signal with surveying
Examination mode signal is compared to perform test.
Brief description of the drawings
By detailed description below in conjunction with the accompanying drawings, the above-mentioned and further feature and advantage of present inventive concept will become aobvious
And be clear to, wherein：
Fig. 1 is the block diagram of device test system；
Fig. 2 is the block diagram of the data receiver device in test pattern of some embodiments according to present inventive concept；
Fig. 3 is to perform test according to the use inner track in test pattern of some embodiments of present inventive concept
The diagram of data receiver device；
Fig. 4 is to perform test according to the use external path in test pattern of the other embodiments of present inventive concept
The diagram of data receiver device；
Fig. 5 is the detailed of the display port acceptor device in general modfel of some embodiments according to present inventive concept
Detail flowchart；
Fig. 6 is the flow chart of the method for testing of the data receiver device of some embodiments according to present inventive concept；
Fig. 7 is the diagram of the data receiver device of another embodiment according to present inventive concept.
Embodiment
Hereinafter, present inventive concept is more fully described with reference to the accompanying drawings, the embodiment of the present invention is shown in the drawings.However,
The present invention can be embodied in many different forms, and the present invention should not be construed as limited to the embodiment of this elaboration.Phase
Instead there is provided these embodiments so as to which the disclosure will be thorough and complete, and it will fully convey the scope of the invention to this
The technical staff in field.In the accompanying drawings, the size and relative size in layer and region can be exaggerated in order to concise.Identical label is all the time
Indicate identical element.
It will be understood that, when element is referred to as " being connected to " or " being attached to " another element, the element can be directly connected to or tie
Another element is closed, or there may be intermediary element.On the contrary, when element is referred to as " being directly connected to " or " being bonded directly to "
During another element, in the absence of intermediary element.As used in this, term "and/or" includes what one or more correlations were listed
Any and all combinations, and "/" can be abbreviated as of item.
It will be understood that, although can be used term " first ", " second " etc. to describe various elements herein, these elements
It should not be limited by these terms.These terms are only used for making a distinction an element and another element.For example, not departing from
In the case of the teaching of the disclosure, the first signal is referred to alternatively as secondary signal, and similarly, secondary signal is referred to alternatively as first
Signal.
The term being used herein is only used for describing the purpose of specific embodiment, without being intended to the limitation present invention.Such as exist
Used in this, singulative is also intended to include plural form, unless the context clearly indicates otherwise.It will also be understood that working as
When using term " comprising " and/or "comprising" in this explanation, feature, region, entirety, step, operation, the member that there is narration are represented
Part and/or component, but do not preclude the presence or addition of one or more of the other feature, region, entirety, step, operation, element, group
Part and/or their group.
Unless otherwise defined, otherwise all terms (including technical term and scientific terminology) used herein have and this hair
The implication identical implication that bright those of ordinary skill in the art are generally understood that.It will also be understood that unless definitely defined here,
Otherwise term (those terms such as defined in common dictionary) should be interpreted as having with the term in association area
The consistent implication of implication in context, without that should be idealized or excessively formally explained.
Fig. 1 is the concept map of single unit system test system.Reference picture 1, device test system includes at least one automatic survey
Try equipment (ATE) 1 and multiple devices being tested (DUTs) 100 (100-1 to 100-n).
ATE1 is to meet industry testing standard (such as, the standard of the research institute of Institute of Electrical and Electric Engineers (IEEE))
Test device.It is described many to assess that ATE1 tests the multiple core block according to the characteristics of the multiple core blocks being included in DUT100
Whether individual core block suitably operates.ATE1 is connected to DUT100 by multiple passages.For example, ATE1 may include four each be used for connect
Acceptance Tests data input signal, test pattern input signal, test clock signal and the input pin for testing remaining signal, and
One output pin for the output signal that outputs test data.
DUT100 is the object of test, i.e. device being tested (DUT), it may include multiple cores with various functions.
DUT100 can be on-chip system (SoC), microprocessor or the ultra-large system integration (VLSI) device.DUT100 passes through multiple
Passage is connected to ATE1.
In the embodiment of present inventive concept, DUT100 is data sink.For example, DUT100 can have numeral aobvious
Show the display device of interface.In the example provided herein, digital display interface is opened by VESA (VESA)
The display port interface of hair.Therefore, the DUT100 of this example supports that combining low-voltage differential signal (LVDS) and digital-visual connects
The interface modes of mouth (DVI), wherein, the low-voltage differential signal (LVDS) is internal interface standard, and the digital-visual connects
Mouth (DVI) is external connection standard.
Inside between display port interface permission chip and chip connects and will be by between digitized product and product
Both external connections.It has widened data bandwidth, so as to support high color depth and resolution ratio.In addition, display port
Interface is equipped with two-way accessory channel, so as in the case of no additional interface, support such as Video chat and internet protocol
Discuss the application of phone (VoIP).
The test of display port device (that is, the device for supporting display port interface) includes link clock locking test, symbol
Number locking test, pseudo-random bit sequence (PRBS) counter test and bit error rate (BER) test.
As suggested above, the display port device (DUT100) of the present embodiment is that only the display port including receiver connects
Receive device device.However, this is for the ease of description.That is, display port device can be included the aobvious of both transmitters and receivers
Show port transceiver device or only the display port sender device including transmitter is replaced.
Fig. 2 is the block diagram of the data receiver device 100 according to some embodiments of present inventive concept.Reference picture 2, data
Acceptor device 100 includes input pin P1 and output pin P2 multiple pins, input 101, system frequency control
Circuit 140, output end 102 and logic unit 200.
Under general modfel or test pattern, input 101 recovers data based on output signal R3 from input signal S1
Signal and data clock signal CK, serial parallel conversion is carried out based on data clock signal CK to data-signal, and by test result
Signal S3 is output to logic unit 200.System frequency control circuit 140 is multiplied by with the multiplication factor M received from logic unit 200
Data clock signal CK, and export operation clock signal C.Now, system frequency control circuit 140 can use data as it is
Clock signal CK, or data clock signal CK can be multiplied by by using predetermined multiplication factor M will be suitable for each system member to produce
The operation clock signal C of part.Multiplication factor M can be set by user, and may be in response to test mode signal or test result signal
S3 and be changed.
In general modfel, output end 102 is serialized based on operation clock signal C to mode signal R1, and is produced
Output signal R3.
In general modfel, logic unit 200 produces mode signal R1 and receives test result signal S3.Logic unit
Element needed for the operation of 200 controllable data receiver devices 100.
Fig. 3 is to perform test using inner track in test pattern according to some embodiments of present inventive concept
Data receiver device 100a diagram.Reference picture 3, data receiver device 100a includes：Draw including input pin P1, output
Pin P2 and reference clock input pin P3 multiple pins, balanced device 110, clock and data recovery (CDR) unit 120, serial parallel
Converter 130, video frequencies control circuit 141, serialiser 150, test driver 160 and logic unit 200.
In test pattern, when input 101 recovers data-signal and data based on output signal from input signal S1
Clock signal, serial parallel conversion is carried out based on data clock signal to data-signal, and by test result signal output to logic list
Member 200.Input 101 includes balanced device 110, CDR units 120 and staticizer 130.Input 101 may also include choosing
Select device 105.
In test pattern, output end 102 is serialized based on test clock signal to test mode signal, so as to produce
Raw output signal.Output end 102 includes serialiser 150 and test driver 160.
The detection of logic unit 200 data receiver device 100 is in test pattern or general modfel.In detection number
After operator scheme according to acceptor device 100, logic unit 200 is according to the mode control data acceptor device 100 of detection
Element.
In test pattern, logic unit 200 produces test mode signal R1 and receives test result signal S3.Logic list
Member 200 also receives pixel clock signal CKp from video frequencies control circuit 141.
In test pattern, test mode signal R1 and test result signal S3 are compared to hold by logic unit 200
Row test.The test may include the test of PRBS counters, BER tests etc..For example, logic unit 200 can believe test pattern
Number R1 and test result signal S3 is compared to test test result signal S3 BER.
Predetermined multiplication factor M is output to video frequencies control circuit by logic unit 200 according to test mode signal R1
141.Logic unit 200 also exportable control signal SEL uses inner track.
Data receiver device 100a may also include for being performed built-in selftest (BIST) using inner track
Selector 101.Selector 101 is connected between input pin P1 and balanced device 110, and can be according to the control of logic unit 200
Signal SEL processed optionally exports the test mode signal R2 or input signal of serialization.
The equilibrium of balanced device 110 is input to data receiver device 100a input signal S1 or the mode signal of serialization
R2.The control selections device 101 of logic unit 200 exports the mode signal R2 of serialization in the test pattern using inner track
To balanced device 110.The control selections device 101 of logic unit 200 will be defeated in the test pattern of general modfel or use external path
Enter signal S1 and be output to balanced device 110.
CDR units 120 recover data clock signal CK and data-signal D from equalizing signal S2.
Staticizer 130 is based on data clock signal CK and carries out serial parallel conversion to data-signal D, so as to export knot
Fruit signal S3.In other words, serial data signal D is converted into parallel letter by staticizer 130 using data clock signal CK
Number, and consequential signal S3 is output to logic unit 200.Data receiver device 100a is in test pattern by reference to clock
Input pin P3 receives the reference clock signal RefCLK for test.
Video frequencies control circuit 141 is multiplied by reference clock signal with the multiplication factor M received from logic unit 200
RefCLK, and export test clock signal C.Now, video frequencies control circuit 141 can export reference clock signal REFCLK
For test clock signal C, or reference clock signal RefCLK can be multiplied by with multiplication factor M it be suitable for each system member to export
The test clock signal C of part.
Serialiser 150 receives test mode signal R1 from logic unit 200, based on test clock signal C to test mould
Formula signal R1 is serialized.In other words, parallel test mode signal R1 is converted into serial letter using test clock signal C
Number, it is subsequently outputted to test driver 160.
The mode signal R2 of the driving serialization of test driver 160, and pass through output pin P2 output signals R3.
As a result, in the case where not needing additional input/output pin, data receiver device 100a can be by using interior
Portion path performs BIST in package level and wafer scale.In addition, data receiver device 100a is using having been integrated into data
Frequency control circuit in acceptor device 100a is as transmitter, so that in the case of no additional design block so that
BIST execution is possibly realized.
Fig. 4 is connect according to the data tested in test pattern using external path of the other embodiments of present inventive concept
Receive device device 100b diagram.Reference picture 4, data receiver device 100b includes：Including input pin P1, output pin P2 and
Reference clock input pin P3 multiple pins, balanced device 110, CDR units 120, staticizer 130, video frequencies control
Circuit 141 processed；Serialiser 150, test driver 160 and logic unit 200.
In test pattern, logic unit 200 produces test mode signal R1 and receives test result signal S3.Logic list
Member 200 also receives pixel clock signal CKp from video frequencies control circuit 141.
In test pattern, test mode signal R1 and test result signal S3 are compared to hold by logic unit 200
Row test.The test may include the test of PRBS counters, BER tests etc..
Data receiver device 100b may also include the selector (not shown) for performing BIST using external path.
The equilibrium of balanced device 110 is input to data receiver device 100b input signal S1.
When selector is not used by, balanced device 110 is balanced anti-by the output signal that will be exported by output pin P2
It is fed to the input signal S1 of input pin P1 acquisitions.When selector is by use, the control selections device of logic unit 200 is in general mould
Formula or using input signal S1 is output into balanced device 110 in the test pattern of external path.Now, output pin P2 can be
Accessory channel pin.
CDR units 120 recover data clock signal CK and data-signal D from equalizing signal S2.Staticizer 130
Serial parallel conversion is carried out to data-signal D based on dagital clock signal CK, so that output result signal S3.In other words, serial parallel
Serial data signal D is converted to parallel signal by converter 130 using data clock signal CK, and consequential signal S3 is output to
Logic unit 200.
Data receiver device 100b receives the ginseng for test in test pattern by reference to clock input pin P3
Examine clock signal RefCLK.Video frequencies control circuit 141 with received from logic unit 200 be multiplied by by multiplication factor M refer to when
Clock signal RefCLK, and export test clock signal C.Video frequencies control circuit 141 always according to reference clock signal RefCLK
Pixel clock signal CKp is output to logic unit 200.
Now, video frequencies control the exportable reference clock signal RefCLK of circuit 141 as test clock signal C, or
Person can be multiplied by reference clock signal RefCLK with multiplication factor M and be suitable for the test clock signal C of each system element to export.
Serialiser 150 receives test mode signal R1 from logic unit 200, and based on test clock signal C to test
Mode signal R1 is serialized.In other words, using test clock signal C, parallel test mode signal R1 is converted into string
Row signal, is then output to test driver 160.The mode signal R2 of the driving serialization of test driver 160, and pass through output
Pin P2 output signals R3.
As a result, data receiver device 100b can via accessory channel pin by using external path in package level and crystalline substance
BIST is performed in chip level.In addition, data receiver device 100b is using having been integrated into data receiver device 100b
Frequency control circuit is as transmitter, so that in the case of no additional design block, makes it possible BIST execution.
Fig. 5 is the display port acceptor device 100c in general modfel of some embodiments according to present inventive concept
Detailed diagram.Reference picture 5, in general modfel, display port acceptor device 100c, which can be used, to be provided for the defeated of BIST
Enter the element at end, but the unusable element (for example, serialiser and test driver) that the output end for BIST is provided.
The equilibrium of balanced device 110 is input to data receiver device 100c input signal S1.CDR units 120 are believed from equilibrium
Recover data clock signal CK and data-signal D in number S2.In general modfel, CDR units 120 send out data clock signal CK
It is sent to video frequencies control circuit 141.
Staticizer 130 is based on data clock signal CK and carries out serial parallel conversion to data-signal D, so as to export knot
Fruit signal S3.In other words, serial data signal D is converted to parallel letter by staticizer 130 using data clock signal CK
Number, and consequential signal S3 is output to logic unit 200.
Video frequencies control circuit 141 is multiplied by data clock signal CK with the multiplication factor M received from logic unit 200,
And export operation clock signal C.Video frequencies control circuit 141 is also believed the pixel clock produced based on data clock signal CK
Number CKp is output to logic unit 200.Now, video frequencies control circuit 141 by phase-lock loop (PLL) circuit or can prolong
Slow locking ring (DLL) circuit is realized.
In other words, in general modfel, when data receiver device 100c uses the data recovered by CDR units 120
Clock signal CK controls the fundamental clock signal of circuit 141 as video frequencies.As a result, in general modfel, data sink dress
Put 100c and be based on pixel clock signal CKp output signal R4, and serial parallel conversion is carried out to consequential signal S3.
Fig. 6 is the flow chart of the method for testing of the data receiver device 100 according to some embodiments of present inventive concept.
In the operation s 10, the detection of data receiver device 100 current mode is test pattern or general modfel.When detecting
When present mode is test pattern, in operation S11, logic unit 200 exports test mode signal R1 and believed with test pattern
The corresponding predetermined multiplication factor M of number R1.In operation S12, data receiver device 100 is multiplied by reference clock with multiplication factor M
Signal RefCLK, and produce test clock signal C.In operation S13, data receiver device 100b is based on test clock signal
C is serialized to test mode signal R1, and in operation S14, drives the test mode signal R2 of serialization to export
Output signal R3.
In operation S15, when using inner track, the test pattern letter of the balanced serialization of data receiver device 100
Number R2, when data receiver device 100 is using external path, data receiver device 100 it is balanced with it is anti-via external path
The corresponding input signal S1 of output signal R3 of feedback.In operation S16, data receiver device 100 is from equalizing input signal
Recover data-signal D and data clock signal CK, and in operation S17, data-signal D is entered based on data clock signal CK
Row serial parallel is changed to produce test result signal S3.
As a result, in operation S18, data receiver device 100 is by by test result signal S3 and test mode signal
R1 is compared to perform BIST.
When it is general modfel to detect present mode, in operation S21, data receiver device 100 is balanced outside defeated
The input signal S1 entered.In operation S22, data receiver device 100 recovers data-signal D sums from equalizing input signal
According to clock signal CK, and in operation S23, serial parallel conversion is carried out to data-signal D based on data clock signal CK.Knot
Really, data receiver device 100 is used as acceptor device progress by driving and exporting the consequential signal R4 that serial parallel is changed
Operation.
Fig. 7 is the data receiver device 100d of another example embodiment according to present inventive concept diagram.In order to keep away
Exempt from redundancy, will only describe data receiver device 100, data of the data receiver device 100d with being shown in Fig. 2 to Fig. 4 and connect
Receive those difference between device device 100a and data receiver device 100b.Reference picture 7, data receiver device 100d may be used also
Including monitor block 300.
At least one in all signals that monitor block 300 will be produced by monitoring in data receiver device 100d
Formed by signal output to test driver 160.For example, monitor block 300 can monitor balanced device 110 produce signal S2,
Signal D or signal CK, the signal S3 of the generation of staticizer 130, the video frequencies control circuit 141 of the generation of CDR units 120
Signal R3, the signal R2 of the generation of serialiser 150 and the logic unit 200 that signal C, the test driver 160 of generation are produced are produced
Raw signal R1 with check each element whether normal operating.
Test driver 160 drives and exports monitoring signal.
ATE1 can receive monitoring signal from data receiver device 100d, and verify that data receiver device 100d's is each
Element whether normal operating.
As described above, according to some embodiments of present inventive concept, having been integrated into the frequency of data receiver device
Control circuit is used as transmitter, therefore, in the case of no additional design block, can perform BIST.In addition, chip area can
It is reduced, and by using the frequency control circuit for being integrated into data receiver device as transmitter, can be in wafer scale
BIST is performed with package level.
Although the exemplary embodiment with reference to present inventive concept is particularly shown and describes present inventive concept,
One of ordinary skill in the art will be understood that, in the feelings for the spirit and scope for not departing from the present inventive concept being defined by the claims
Under condition, the various changes in form and details can be carried out wherein.
Claims (20)
1. a kind of data receiver device operated in test pattern and general modfel, the data receiver device includes：
Logic unit, is configured as detecting the current mode of data receiver device and when current mode is detected as
Test mode signal is produced during test pattern, test result signal is received in test pattern, and will be surveyed in test pattern
Examination mode signal is compared to perform test with test result signal；
System frequency controls circuit, is configured as being multiplied by reference clock signal with the multiplication factor received from logic unit, and defeated
Go out test clock signal；
Output end, is configured as serializing test mode signal based on test clock signal, and pass through output pin
Output signal output；
Input, is configured as recovering data-signal and data clock letter from the input signal of input pin based on output signal
Number, serial parallel conversion is carried out to data-signal to produce test result signal based on data clock signal, and test result is believed
Number it is output to logic unit.
2. data receiver device as claimed in claim 1, wherein, output end includes：
Serialiser, is configured as serializing test mode signal based on test clock signal；
Test driver, is configured as exporting the output by driving the test mode signal of serialization to obtain by output pin
Signal.
3. data receiver device as claimed in claim 1, wherein, input includes：
Balanced device, is configured as the frequency range based on output signal equalizing input signal；
Clock data recovery unit, is configured as from equalizing input signal recovering data-signal and data clock signal；
Staticizer, is configured as carrying out serial parallel conversion to data-signal based on data clock signal, and export test
Consequential signal.
4. data receiver device as claimed in claim 1, wherein, in general modfel, system frequency controls circuit with multiplying
The method factor is multiplied by data clock signal to export operation clock signal, in test pattern, system frequency control circuit multiplication
The factor is multiplied by reference clock signal to export test clock signal.
5. data receiver device as claimed in claim 3, in addition to：Selector, be configured as being connected to input pin and
Between balanced device, and according to the control of logic unit, in the test mode signal and input signal that optionally export serialization
One.
6. data receiver device as claimed in claim 5, wherein, in test pattern, selector is according to logic unit
Control selections and the test mode signal for exporting serialization.
7. data receiver device as claimed in claim 1, wherein, input signal be exported by output pin and with
The output signal received afterwards by input pin.
8. data receiver device as claimed in claim 7, wherein, output pin is accessory channel input/output pin.
9. data receiver device as claimed in claim 1, wherein, logic unit is according to test mode signal by predetermined multiplication
The factor is output to system frequency control circuit.
10. data receiver device as claimed in claim 1, wherein, logic unit is by test mode signal and test result
The pattern of signal is compared to test the bit error rate of test result signal.
11. a kind of numeric display unit, including：
Logic unit and video system frequency control circuit, are configured as operating in general modfel and are shown to perform digital video
Processing, and be configured as operating in test pattern performing built-in selftest (BIST) processing；
Output end, is configured as serializing test mode signal based on test clock signal, and output signal output；
Input, is configured as recovering data-signal and data clock signal from input signal based on output signal, based on number
Serial parallel conversion is carried out to data-signal to produce test result signal according to clock signal, and by test result signal output to patrolling
Collect unit；
Wherein, in test pattern, logic unit is configured as producing test mode signal, receives test result signal, will survey
Examination mode signal is compared to perform BIST processing with test result signal；
Wherein, in test pattern, video system frequency control circuit is configured as with the multiplication factor received from logic unit
Reference clock signal is multiplied by, and exports test clock signal.
12. numeric display unit as claimed in claim 11, wherein, the interface of numeric display unit meets display port
DisplayPort interface standards.
13. numeric display unit as claimed in claim 11, wherein, in general modfel, video system frequency control circuit
Dagital clock signal is multiplied by with multiplication factor to export operation clock signal, and in test pattern, is multiplied by with multiplication factor
Reference clock signal exports test clock signal.
14. numeric display unit as claimed in claim 11, in addition to：Selector, be configured as being connected to input pin and
Between balanced device, and according to the control of logic unit, in the test mode signal and input signal that optionally export serialization
One.
15. numeric display unit as claimed in claim 14, wherein, in test pattern, selector is according to logic unit
Control selections and the test mode signal for exporting serialization.
16. a kind of method of testing of data receiver device, wherein, the method for testing includes：Detect data receiver device
Current mode be test pattern or general modfel, wherein, when it is test pattern to detect current mode, survey
Method for testing also includes：
Produce test mode signal and predetermined multiplication factor corresponding with test mode signal；
Reference clock signal is multiplied by by using multiplication factor to produce test clock signal；
Test mode signal is serialized based on test clock signal；
By driving the test mode signal of serialization come output signal output；
Based on test mode signal equalizing input signal；
Recover data-signal and data clock signal from equalizing input signal；
Test result signal is produced by carrying out serial parallel conversion to data-signal based on data clock signal；
By the way that test result signal and test mode signal are compared to perform test.
17. method of testing as claimed in claim 16, wherein, by the way that outside will be output to via data receiver device
Output signal feeds back to data receiver device to obtain input signal.
18. method of testing as claimed in claim 16, wherein, the test mode signal serialized by internal feedback is obtained
Input signal.
19. method of testing as claimed in claim 16, wherein, the step of performing test includes：By test mode signal with surveying
The pattern of test result signal is compared, and tests the bit error rate of test result signal.
20. method of testing as claimed in claim 16, wherein, the interface of data receiver device meets display port
DisplayPort interface standards.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020120035127A KR101918627B1 (en) | 2012-04-04 | 2012-04-04 | Data receiver device and testing method thereof |
| KR10-2012-0035127 | 2012-04-04 |
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| US (1) | US8949680B2 (en) |
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| KR101918627B1 (en) | 2018-11-15 |
| KR20130112611A (en) | 2013-10-14 |
| US8949680B2 (en) | 2015-02-03 |
| CN103364716A (en) | 2013-10-23 |
| US20130268819A1 (en) | 2013-10-10 |
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