CN116593864A - Test method and integrated circuit device - Google Patents

Abstract

A test method and an integrated circuit device. The test method comprises the following steps: respectively executing a first test mode and a second test mode on the integrated circuit device to perform a test, wherein in the first test mode, a first transmitting path of the first chip is selected to transmit first internal test data through a transmitting driver, and a first receiving path of the second chip is selected to receive first result data corresponding to the first internal test data through a receiving driver; the first loop-back path of the first chip is selected to bypass the transmitting driver to transmit the second internal test data and receive the first internal result data corresponding to the second internal test data in the second test mode, and the second loop-back path of the second chip is selected to bypass the receiving driver to receive the second internal result data corresponding to the third internal test data of the second chip. The testing method is beneficial to improving the testability of advanced packaging, reducing the testing cost and accelerating the testing process by detecting abnormal modules in the accurate positioning chip in a segmented way.

Description

Test method and integrated circuit device

Technical Field

Embodiments of the present disclosure relate to a test method and an integrated circuit device.

Background

Advanced packaging technology is an important means capable of breaking through the limitation of moore's law, and multiple chips can be integrated together, for example, a system on chip (SoC) and a memory chip can be integrated together to form a 2.5D package assembly or a 3D package assembly, so as to realize chip connection with higher quality, lower power consumption, higher performance and better integration level.

The testability is an indispensable part of improving the chip yield, reducing the test cost and accelerating the test process, but with the continuous development of semiconductor technology and manufacturing process, the testability becomes more difficult and complex, and especially for advanced technology nodes and advanced packaging technology, how to improve the testability becomes a problem to be solved urgently.

Disclosure of Invention

At least one embodiment of the present disclosure provides a test method, including: executing a first test mode and a second test mode on an integrated circuit device respectively to perform a test, wherein the integrated circuit device comprises a first chip, a second chip and a package connecting member, and a transmitting driver of the first chip is connected with a receiving driver of the second chip through a data channel in the package connecting member;

The executing the first test mode includes:

selecting a first transmission path of the first chip to transmit first internal test data through the transmission driver, and selecting a first reception path of the second chip to receive first result data corresponding to the first internal test data through the reception driver;

the executing the second test mode includes:

a first loopback path of the first chip is selected to bypass the transmit driver to transmit second internal test data and receive first internal result data corresponding to the second internal test data, and a second loopback path of the second chip is selected to bypass the receive driver to receive second internal result data corresponding to third internal test data of the second chip.

For example, the test method provided in at least one embodiment of the present disclosure further includes: in response to a test result of the first test mode being incorrect and a test result of the second test mode being correct, determining that at least one of the transmit driver of the first chip, the package connection member, and the receive driver of the second chip is malfunctioning.

For example, in the test method provided in at least one embodiment of the present disclosure, the first chip or the second chip further includes an analog circuit module and a digital circuit module, the digital circuit module provides a signal to the analog circuit module, the analog circuit module provides a signal to the transmitting driver or the receiving driver, and the first transmitting path and the first loopback path of the first chip both pass through the analog circuit module and the digital circuit module of the first chip; the first receiving path and the second loop-back path of the second chip both pass through an analog circuit module and a digital circuit module of the second chip.

For example, the test method provided in at least one embodiment of the present disclosure further includes: executing a third test mode on the integrated circuit device, wherein the executing the third test mode comprises: and selecting a third loop path of the first chip to test the digital circuit module of the first chip, and selecting a fourth loop path of the second chip to test the digital circuit module of the fourth chip.

For example, the test method provided in at least one embodiment of the present disclosure further includes: responding to the test result error of the third test mode, and determining that the digital circuit modules of the first chip and the second chip work abnormally; and determining that the analog circuit modules of the first chip and the second chip work abnormally in response to the fact that the test result of the second test mode is wrong and the test result of the third test mode is correct.

For example, the test method provided in at least one embodiment of the present disclosure further includes: executing a fourth test mode on the integrated circuit device, wherein the executing the fourth test mode comprises: and selecting a second transmitting path of the first chip to transmit fourth internal test data of the first chip through the transmitting driver connected with the first conductive connecting piece, and selecting a second receiving path of the second chip to receive first external test data through the receiving driver connected with the second conductive connecting piece.

For example, the test method provided in at least one embodiment of the present disclosure further includes: determining that the transmission driver of the first chip works abnormally in response to the fact that the test result of the fourth test mode for testing the first chip is wrong and the test result of the second test mode is correct; determining that the receiving driver of the second chip works abnormally in response to the fact that the test result of the fourth test mode for testing the second chip is wrong and the test result of the second test mode is correct; and determining that the data channel of the packaging connecting member works abnormally in response to the fourth test mode that the test result of the fourth test mode for testing the first chip and the second chip is correct and the test result of the second test mode is incorrect.

For example, in a test method provided by at least one embodiment of the present disclosure, the transmitting driver and the receiving driver are configured to be connectable with an external test device through the first conductive connection and the second conductive connection, respectively.

For example, the test method provided in at least one embodiment of the present disclosure further includes: performing a fifth test mode on the integrated circuit device, wherein the performing the fifth test mode comprises: the second receiving path of the second chip is selected to receive second external test data transmitted from the external test device through the second conductive connection to the receiving driver, and the second transmitting path of the first chip is selected to transmit external result data corresponding to the second external test data to the external test device through the first conductive connection to the transmitting driver.

For example, the test method provided in at least one embodiment of the present disclosure further includes: observing, by the external detection device, the second external test data and the external result data.

At least one embodiment of the present disclosure also provides an integrated circuit device comprising: the first chip comprises a first sending path for sending first internal test data through a sending driver and a first loop-back path for sending second internal test data by bypassing the sending driver, wherein the first chip receives first internal result data corresponding to the second internal test data through the first loop-back path.

For example, at least one embodiment of the present disclosure provides an integrated circuit device, further comprising: the second chip comprises a first receiving path for receiving first result data through a receiving driver and a second loop-back path for receiving second internal result data by bypassing the receiving driver, the second chip receives second internal result data corresponding to third internal test data of the second chip through the second loop-back path, and the transmitting driver of the first chip is connected with the receiving driver of the second chip through a data channel in the packaging connecting member.

For example, in an integrated circuit device provided in at least one embodiment of the present disclosure, the first chip or the second chip further includes an analog circuit module and a digital circuit module, the digital circuit module providing signals to the analog circuit module, the analog circuit module providing signals to the transmit driver or the receive driver, the first transmit path and the first loopback path of the first chip both passing through the analog circuit module and the digital circuit module of the first chip; the first receiving path and the second loop-back path of the second chip both pass through an analog circuit module and a digital circuit module of the second chip.

For example, in an integrated circuit device provided in at least one embodiment of the present disclosure, the first chip further includes a third loop-back path passing through only the digital circuit module of the first chip, and the second chip further includes a fourth loop-back path passing through only the digital circuit module of the second chip, the third loop-back path and the fourth loop-back path being used for testing digital ports of the first chip and the second chip, respectively.

For example, in an integrated circuit device provided in at least one embodiment of the present disclosure, the first chip further includes a second transmission path, and the second chip further includes a second reception path, where the second transmission path includes a first conductive connection connected to the transmission driver, and the second reception path includes a second conductive connection connected to the reception driver.

For example, in an integrated circuit device provided in at least one embodiment of the present disclosure, the transmitting driver and the receiving driver are configured to be connectable with an external detection device through the first conductive connection and the second conductive connection, respectively.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure, not to limit the present disclosure.

FIG. 1 is a schematic diagram of an internal loopback test for a single chip;

FIG. 2 is a schematic diagram of an external loopback test between two chips;

FIG. 3 is a schematic diagram of a 2.5D package structure;

FIG. 4 is a schematic diagram of a communication channel between two chips within a package structure;

FIG. 5 is a schematic block diagram of an integrated circuit device provided in accordance with at least one embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another integrated circuit device provided in accordance with at least one embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a first test mode provided by at least one embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a second test mode provided by at least one embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a third test mode provided by at least one embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a fourth test mode provided by at least one embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a fifth test mode provided by at least one embodiment of the present disclosure; and

fig. 12 is a flow chart of a testing method according to at least one embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

The present disclosure is illustrated by the following several specific examples. Detailed descriptions of known functions and known parts (elements) may be omitted for the sake of clarity and conciseness in the following description of the embodiments of the present disclosure. When any part (element) of an embodiment of the present disclosure appears in more than one drawing, the part (element) is denoted by the same or similar reference numeral in each drawing.

Chip testing refers to the detection of the function, performance, reliability, stability, etc. of a chip. The chip is tested to fully and quantitatively reflect various indexes from structure, function to electrical characteristics of each chip, and unqualified chips can be detected, so that the yield and the production efficiency of the chips are ensured.

Chip testing typically includes board level testing, wafer (CP) testing, final Test (FT) testing, system level (System Level Test, SLT) testing, reliability testing, and the like. The board-level test is mainly used for testing the functions of the chip, and leads out the interface of the chip to a printed circuit board (Printed Circuit Board, PCB), so that a simulated working environment is built to detect the functions of the chip. The CP test and the FT test are mainly used for carrying out result inspection on the chip so as to ensure that the qualified chip enters a packaging link or enters the market.

CP testing, which is one type of Design For Test (DFT), refers to testing the performance and function of chips on a wafer by probing the pins of the chips with probes (probes). For example, a wafer to be tested is placed on a probe station (Prober), a probe is fixed on the probe station, all test programs are transmitted to the wafer through the probe during testing, the probe can input various signals into a chip, output responses of the chip can be captured, and the quality of the chip can be detected through comparison and calculation of the input signals and the output signals. After testing one chip, the probe station moves to the next chip, and other chips are continuously tested, so that unqualified chips can be screened out before packaging.

FT testing is typically the final test of the chip after subsequent processes of the integrated circuit such as dicing, bonding, packaging, and burn-in, because the chip may damage portions of the chip's circuitry during, for example, packaging, and therefore FT testing of the packaged integrated circuit is required to pick out a good finished product.

The CP test and the FT test can be performed on the chip, so that the yield of the product can be timely and effectively fed back, the packaging cost is reduced, and the quality of the product delivered from the factory is ensured. At present, two testing methods for detecting ports and functional modules are mainly available, one is a loop-back test of a single chip, and the other is a loop-back test between two chips.

FIG. 1 is a schematic diagram of an internal loopback test for a single chip. As shown in fig. 1, the chip DIEA includes a pseudo random bit sequence (Pseudo Random Binary Sequence, PRBS) generator, a PRBS verifier, a plurality of data transceiving modules, and a clock module. For example, the plurality of data transceiving modules include a plurality of transmitting units TX-A1 to TX-AN and a plurality of receiving units RX-A1 to RX-A2, and the plurality of data transceiving modules may share a clock of the same clock module CLK to transmit and receive data. For example, when the internal loopback test is performed on the chip DIEA, as shown by a dotted line in fig. 1, a test signal is generated by a PRBS generator inside the chip DIEA, the internal test signal is circulated to a PRBS verifier inside the chip DIEA after passing through a transmitting unit and a receiving unit of each data transceiver module, the PRBS verifier verifies whether the test signal is correct, if the test signal received by the PRBS verifier is correct, it indicates that the data transceiver module and the port of the chip DIEA are normal, and if the test signal received by the PRBS verifier is incorrect, it indicates that there is a fault inside the chip DIEA.

Fig. 2 is a schematic diagram of an external loop-back test between two chips. As shown in fig. 2, the chip DIEA includes a PRBS generator, a clock module, and a plurality of data transmission units TX-A1 to TX-AN, which may share the clock of the clock module of the chip DIEA to transmit data. The chip DIEB includes a PRBS verifier, a clock module, and a plurality of data receiving units RX-B1 to RX-BN, which can receive data by sharing the clock of the clock module of the chip DIEB. The chip DIEA and the chip DIEB are connected to each other through a plurality of data transmission units TX-A1 to TX-AN and a plurality of data reception units RX-B1 to RX-BN to achieve communication (only the transmission of data from the chip DIEA to the chip DIEB is shown in the figure). For example, when performing a loop-back test between the chip DIEA and the chip DIEB, as shown by a dotted line in fig. 2, a test signal is generated by a PRBS generator inside the chip DIEA, and the test signal reaches a PRBS verifier inside the chip DIEB after passing through a data transmitting unit of the chip DIEA and a data receiving unit of the chip DIEB, and the PRBS verifier of the chip DIEB verifies whether the test signal is correct, so that whether a connection between two chips has a fault can be detected.

There may be two cases where the connection between the two chips fails, one is that the transmitting port or the receiving port of the two chips fails, and the other is that the connection member between the two chips fails. If the ports and connection members of the two chips can be exposed, the two cases can be easily detected separately. However, for advanced packaging, the ports and connection members of the two chips are enclosed in one housing, so it is difficult to detect the ports and connection members of the two chips in the package structure, respectively.

Fig. 3 is a schematic diagram of a 2.5D package structure. As shown in fig. 3, the package structure includes a CPU chip, a memory (DRAM) chip, a micro bump 10, an interposer 20, a bump 30, a package substrate 40, and a Ball Grid Array (BGA) 50. For example, the CPU chip and the DRAM chip have Physical layers (PHYs) therein, and the PHYs of the CPU chip and the DRAM chip are connected to conductive traces in the interposer 20 through the microbumps 10, and after the packaging is completed, the CPU chip, the DRAM chip, and the microbumps 10 are all encapsulated in an encapsulation Layer (not shown in the figure), and thus cannot be exposed to the outside. Other circuit pins of the CPU chip and the DRAM chip may be further connected to the package substrate 40 through the interposer 20 and the bump 30, and then connected to the printed circuit board through the BGA, thereby being connected to other devices, and realizing connection of the internal chip and the external circuit.

Fig. 4 is a schematic diagram of a communication channel between two chips in a package structure. As shown in fig. 4, there may be multiple communication channels between two die DIEA and DIEB, for example, 16 or 64, and in each communication channel, a digital signal Data enters the Data transmission module of the whole DIEA from the parallel input port of the die DIEA, and after being converted into a high-speed serial signal by the serializer, is sent out by the transmission driver TXD of the die DIEA to be output onto the microbump. The output high-speed signal Data is transmitted to a high-speed signal inlet of the chip DIEB through a conductive Data channel of the intermediate layer, then is converted into a parallel signal through a deserializer after being subjected to delay removal processing by a receiving driver RXD of the chip DIEB, and finally is output back into a digital signal through a first-in first-out (First In First Out, FIFO) buffer of the chip DIEB, so that the digital signal Data realizes communication from the chip DIEA to the chip DIEB.

However, while this package structure meets the requirements for high-speed signal transmission, the data transceiver drivers (e.g., TXD and RXD) of the PHY chip are connected to the microbumps, which are often relatively prone to failure.

As described above, since the ports and connection members of the two chips are not exposed to the outside after the package, the test signals inside the 2.5D package cannot be directly observed at the time of the PCB board level test. In addition, the fault part of the chip is difficult to accurately position by using the internal loop-back test of a single chip and the external loop-back test between two chips, so that the test efficiency is low, and the follow-up debugging and improvement are not facilitated.

At least some embodiments of the present disclosure provide a test method comprising: executing a first test mode and a second test mode on the integrated circuit device respectively to perform a test, wherein the integrated circuit device comprises a first chip, a second chip and a packaging connecting member, and a transmitting driver of the first chip is connected with a receiving driver of the second chip through a data channel in the packaging connecting member; executing a first test mode, comprising: selecting a first transmission path of the first chip to transmit the first internal test data through the transmission driver, and selecting a first reception path of the second chip to receive first result data corresponding to the first internal test data through the reception driver; executing a second test mode, comprising: the first loop-back path of the first chip is selected to transmit second internal test data around the transmit driver and receive first internal result data corresponding to the second internal test data, and the second loop-back path of the second chip is selected to receive second internal result data corresponding to third internal test data of the second chip around the receive driver. The test method realizes the sectional detection by comparing the test results of the first test mode and the second test mode, thereby being capable of precisely positioning the abnormal module in the chip, being beneficial to improving the testability of advanced packaging, reducing the test cost and accelerating the test process.

At least some embodiments of the present disclosure also provide an integrated circuit device comprising: the first chip comprises a first transmission path for transmitting first internal test data through the transmission driver and a first loop-back path for transmitting second internal test data by bypassing the transmission driver, wherein the first chip receives first internal result data corresponding to the second internal test data through the first loop-back path.

At least some embodiments of the present disclosure provide an integrated circuit device further comprising: the second chip comprises a first receiving path for receiving first result data through a receiving driver and a second loop-back path for receiving second internal result data by bypassing the receiving driver, the second chip receives second internal result data corresponding to third internal test data of the second chip through the second loop-back path, and a transmitting driver of the first chip is connected with a receiving driver of the second chip through a data channel in the packaging connecting member.

The integrated circuit device provided by at least some embodiments of the present disclosure has the advantages of simple structure, strong testability, low cost, and the like, and can be applied to various test stages such as CP test and FT test, and can realize segment detection by comparing test results of different paths, thereby accurately positioning an abnormal module in a chip, contributing to improving the testability of advanced packaging, reducing test cost, and accelerating test process.

Embodiments of the present disclosure are described in detail below with reference to the attached drawings.

Some embodiments of the present disclosure provide an integrated circuit device, and fig. 5 is a schematic block diagram of an integrated circuit device provided by at least one embodiment of the present disclosure. As shown in fig. 5, the integrated circuit device includes a first chip DIE1, the first chip DIE1 including a first transmission path through which the first internal test data tx_data0 is transmitted through the transmission driver TXD and a first loop-back path through which the second internal test data tx_data1 is transmitted around the transmission driver TXD, the first chip DIE1 receiving the first internal result data rx_data1 corresponding to the second internal test data tx_data1 through the first loop-back path.

It should be noted that the first internal test data tx_data0 and the second internal test data tx_data1 are test patterns or test vectors generated internally by the first chip DIE1, not provided by an external test device. For example, the first chip DIE1 has therein components for generating test signals, including but not limited to a pseudo random bit sequence (Pseudo Random Binary Sequence, PRBS) generator, a Custom signal generator (also called Custom generator), etc., so that internal test data can be generated without connecting the first chip DIE1 to an external test device, and the first chip DIE1 also has therein components for verifying test signals, including but not limited to a PRBS verifier, etc., so that test results of the second internal test data tx_data1 after passing through the first loop path can be verified to facilitate completion of an internal loop-back test on the first chip DIE 1. The components for generating the test signal and verifying the test signal in the chip may be conventional components existing at present or may be custom test components according to test requirements, and the embodiments of the present disclosure are not limited thereto.

For example, the first and second internal test data tx_data0 and tx_data1 may be digital signals, which may be converted into analog signals through a digital-to-analog converter inside the first chip DIE1, and thus provided to an analog circuit module inside the first chip DIE 1.

For example, the first internal test data tx_data0 and the second internal test data tx_data1 may be the same test pattern or test vector, or may be different test patterns or test vectors. For example, in at least one embodiment of the present disclosure, the first internal test data tx_data0 and the second internal test data tx_data1 are the same test pattern, thereby facilitating more visual and quick comparison of test results of the test pattern after passing through the first transmission path and the first loopback path.

For example, the transmission driver TXD of the first chip DIE1 is connected to a functional module (not shown) inside the first chip DIE1, and is configured to transmit data processed by the functional module to an external circuit.

For example, the first chip DIE1 may include a plurality of (e.g., 10 or 16 or more) transmission units connected to a plurality of functional modules, each transmission unit including a transmission driver TXD, a first transmission path, and a first loopback path as shown in fig. 5. By testing the first transmission path and the first loop path of the plurality of transmission units, respectively, it can be determined whether the transmission driver TXD in the plurality of transmission units of the first chip DIE1 operates normally.

It should be noted that, the first transmission path and the first loopback path both pass through the same functional module, and the difference between the first transmission path and the first loopback path is only whether the first transmission path passes through the transmission driver TXD, so as to ensure that whether the functional module works normally or not, whether the transmission driver TXD has a fault can be determined by comparing the detection results of the two paths.

For example, a switch for testing, such as a transistor, a gate or other circuit structures as would be readily apparent to a person skilled in the art, may be designed inside the first chip DIE 1. For example, it is possible to choose whether the first transmit path or the first loop path is tested by means of a control switch, i.e. whether the transmit driver TXD is bypassed or not can be chosen by means of a control switch.

For example, the first chip DIE1 further includes a clock module for providing a clock for data communication, and a plurality of transmitting units of the first chip DIE1 may share the clock module, where the clock module includes conventional circuits such as a Phase-Locked Loop (PLL) and a clock transmitting terminal, and the circuit structure of the clock module is not limited by the embodiments of the present disclosure.

The first chip DIE1 provided in at least one embodiment of the present disclosure has two test paths for segment detection, which not only has a simple circuit structure and enhances the testability of the chip, but also helps to quickly detect whether the transmission driver TXD of the first chip DIE1 has a fault.

Some embodiments of the present disclosure also provide an integrated circuit device, and fig. 6 is a schematic diagram of another integrated circuit device provided in at least one embodiment of the present disclosure. As shown in fig. 6, the integrated circuit device includes a first chip DIE1, a second chip DIE2, and a package connection member IP. For example, the structure of the first chip DIE1 may refer to the related description of fig. 5, which is not repeated here. For example, the second chip DIE2 includes a first reception path receiving the first result data rx_data0 through the reception driver RXD and a second loop-back path receiving the second internal result data rx_data2 bypassing the reception driver RXD, and the second chip DIE2 receives the second internal result data rx_data2 corresponding to the third internal test data tx_data2 of the second chip DIE2 through the second loop-back path. For example, the transmit driver TXD of the first chip DIE1 is connected to the receive driver TXD of the second chip DIE2 through a data channel within the encapsulation connection IP.

For example, the package connection member IP may be an interposer (also referred to as an interposer) or other conductive connection member, and embodiments of the present disclosure are not limited to package connection members. For example, the interposer may include conductive traces and through substrate vias (through substrate via, TSVs) and the like that can form connection structures for data channels. For example, the first chip DIE1 and the second chip DIE2 may realize high-speed signal transmission through a data channel in the package connection member IP.

For example, the third internal test data tx_data2 is a test pattern or a test vector internally generated by the second chip DIE2, not provided by an external test device. For example, the second chip DIE2 has therein a component generating a test signal, including but not limited to a PRBS generator or the like, so that the third internal test data tx_data2 can be generated without connecting the second chip DIE2 with an external test device, and a component capable of verifying the test signal, including but not limited to a PRBS verifier or the like, so that the test result of the third internal test data tx_data2 after passing through the second loopback path can be verified to complete the internal loopback test of the second chip DIE 2.

For example, the third internal test data tx_data2 may be a digital signal, which may be converted into an analog signal through a digital-to-analog converter inside the second chip DIE2, and thus provided to an analog circuit module inside the second chip DIE 2.

For example, the receiving driver RXD of the second chip DIE2 is connected to a functional module (not shown) inside the second chip DIE2 for receiving data from an external circuit, such as the first internal test data tx_data0 from the first chip DIE1, and providing it to the functional module of the second chip DIE2 for processing or verification.

For example, the second chip DIE2 may include a plurality of receiving units (e.g., 10 or 16 or more) connected to a plurality of functional modules, each receiving unit including a receiving driver RXD, a first receiving path, and a second loopback path as shown in fig. 6. By testing the first reception path and the second loop path of the plurality of reception units, respectively, it can be determined whether the reception driver RXD of the second chip DIE2 is operating normally.

It should be noted that, the first receiving path and the second loopback path both pass through the same functional module, and the first receiving path and the second loopback path only differ in whether the receiving driver RXD passes through, so as to ensure that whether the functional module works normally or not, whether the receiving driver RXD has a fault or not can be determined by comparing the detection results of the two paths.

For example, a switch for testing, such as a transistor, a gate or other circuit structures as would be readily apparent to a person skilled in the art, may be designed inside the second chip DIE 2. For example, it is possible to choose whether the first receive path or the second loop path is tested by means of a control switch, i.e. it is possible to choose whether the receive driver RXD is bypassed or not by means of a control switch.

For example, the second chip DIE2 may further include a clock module for providing a clock for data communication, and a plurality of receiving units of the second chip DIE2 may share the clock module, and the clock module may include conventional circuits such as a Phase Locked Loop (PLL) and a clock receiving terminal, and the circuit structure of the clock module is not limited in the embodiments of the present disclosure.

It should be noted that at least some embodiments of the present disclosure provide a channel for transmitting data from a first chip DIE1 to a second chip DIE2, however this is not a limitation of the present disclosure. In at least some embodiments of the present disclosure, the first chip DIE1 may have the same receiving unit as the second chip DIE2, and the second chip DIE2 may have the same transmitting unit as the first chip DIE1, so that transmitting data from the second chip DIE1 to the first chip DIE1 may be achieved. That is, in the integrated circuit device provided in at least some embodiments of the present disclosure, the first chip DIE1 and the second chip DIE2 may have a basic circuit structure similar to the chip DIE shown in fig. 1, such as a transmitting unit, a receiving unit, and a common clock module, unlike the chip DIE, in that a test path for segment detection is newly added to the first chip DIE1 and the second chip DIE2, so that a fault location in the chip can be rapidly and precisely located without damaging a package structure or relying on an external tester.

For example, in an integrated circuit device provided in at least some embodiments of the present disclosure, the first chip DIE1 or the second chip DIE2 further includes an analog circuit module and a digital circuit module, the digital circuit module providing a signal to the analog circuit module, and the analog circuit module providing a signal to the transmit driver TXD or the receive driver RXD. As shown in fig. 7, the first transmission path and the first loopback path of the first chip DIE1 pass through the analog circuit module PMA1 and the digital circuit module NPL1 of the first chip DIE1, and the first reception path and the second loopback path of the second chip DIE2 pass through the analog circuit module PMA2 and the digital circuit module NPL2 of the second chip DIE 2.

At least one embodiment of the present disclosure provides a test method that includes performing a first test mode and a second test mode, respectively, on an integrated circuit device for testing.

For example, the test method may be used with the integrated circuit device shown in fig. 6. For example, the integrated circuit device includes a first chip DIE1, a second chip DIE2, and a package connection member IP, and a transmit driver TXD of the first chip DIE1 and a receive driver RXD of the second chip DIE2 are connected through a data channel within the package connection member IP.

Fig. 7 is a schematic diagram of a first test mode provided by at least one embodiment of the present disclosure, fig. 8 is a schematic diagram of a second test mode provided by at least one embodiment of the present disclosure, and the test method is described in detail below with reference to fig. 7 and 8.

For example, the data flow of the test data for executing the first test mode may be as shown by the dotted line in fig. 7. For example, the first internal test data tx_data11 is transmitted through the transmit driver TXD by selecting the first transmit path of the first chip DIE1 through the off switch sw1, and the first result data rx_data21 corresponding to the first internal test data tx_data11 is received through the receive driver RXD by selecting the first receive path of the second chip DIE2 through the off switch sw 2.

For example, comparing the first result data rx_data21 with expected result data of the first internal test data tx_data11, if the first result data rx_data21 and the expected result data are identical, it is explained that the digital circuit modules (NPL 1 and NPL 2), the analog circuit modules (PMA 1 and PMA 2), the transceiving drivers (TXD and RXD) and the package connection means IP inside the first chip DIE1 and the second chip DIE2 are normal; if the first result data rx_data21 and the expected result data are not identical, it is indicated that at least one of the digital circuit blocks (NPL 1 and NPL 2), the analog circuit blocks (PMA 1 and PMA 2), the transceiving drivers (TXD and RXD) and the package connection means IP inside the first chip DIE1 and the second chip DIE2 has a fault, and further detection is required to determine the fault location.

For example, the data flow of the test data for performing the second test mode may be as shown by the dotted line in fig. 8. For example, the first loop path of the first chip DIE1 is selected by closing the switch sw1 to transmit the second internal test data tx_data12 around the transmit driver TXD and receive the first internal result data rx_data12 corresponding to the second internal test data tx_data12. For example, the second loopback path of the second chip DIE2 is selected by closing the switch sw2 to receive the second internal result data rx_data22 corresponding to the third internal test data tx_data22 of the second chip DIE2 by bypassing the receiving driver RXD.

For example, comparing the first internal result data rx_data12 of the first chip DIE1 with the expected result data of the second internal test data tx_data12, if the first internal result data rx_data12 and the expected result data are the same, it is indicated that the digital circuit module NPL1 and the analog circuit module PMA1 of the first chip DIE1 are normal; if the first internal result data rx_data12 and the expected result data are not identical, it is indicated that at least one of the digital circuit module NPL1 and the analog circuit module PMA1 of the first chip DIE1 is faulty.

For example, comparing the second internal result data rx_data22 of the second chip DIE2 with the expected result data of the third internal test data tx_data22, if the second internal result data rx_data22 and the expected result data are the same, it is indicated that the digital circuit module NPL2 and the analog circuit module PMA2 of the second chip DIE2 are normal; if the second internal result data rx_data22 and the expected result data are not identical, it is indicated that at least one of the digital circuit module NPL2 and the analog circuit module PMA2 of the second chip DIE2 has a fault.

In at least some embodiments of the present disclosure, for convenience of description, a case where the result data is identical to the expected result data is referred to as "test result correct", and a case where the result data is not identical to the expected result data is referred to as "test result error".

For example, in at least one embodiment, the above test method further comprises: in response to the test result of the first test mode being incorrect and the test result of the second test mode being correct, it is determined that at least one of the transmit driver TXD of the first chip DIE1, the package connection member IP, and the receive driver RXD of the second chip DIE2 is abnormally operated.

The test method realizes the segment detection by comparing the test results of the first test mode and the second test mode, and can position the abnormal module in the chip as the transmitting driver TXD of the first chip DIE1, the package connecting member IP or the receiving driver RXD of the second chip DIE2, thereby greatly improving the testability of advanced package, reducing the test cost and accelerating the test process under the conditions of not damaging the package structure and not depending on an external tester.

As described above, in the case where the test result of the second test mode performed on the first chip DIE1 is wrong, it is still impossible to determine whether there is a failure of the digital circuit module NPL1 or a failure of the analog circuit module PMA1 of the first chip DIE 1. Similarly to the case where the second test mode is performed on the second chip DIE2, it is not possible to determine whether there is a failure in the digital circuit module NPL2 or in the analog circuit module PMA2 of the second chip DIE 2. Accordingly, at least some embodiments of the present disclosure provide further segmented test paths to more accurately locate whether a fault occurred in a digital circuit module or an analog circuit module.

Fig. 9 is a schematic diagram of a third test mode provided by at least one embodiment of the present disclosure, as shown by the dashed line in fig. 9, in the integrated circuit device provided by at least some embodiments of the present disclosure, the first chip DIE1 further includes a third loopback path through only the digital circuit module NPL1 of the first chip DIE1, the second chip DIE2 further includes a fourth loopback path through only the digital circuit module NPL2 of the second chip DIE2, and the third loopback path and the fourth loopback path are used for testing digital ports of the first chip DIE1 and the second chip DIE2, respectively.

For example, in at least one embodiment, the above test method further comprises: a third test mode is performed on the integrated circuit device. For example, the third loop path of the first chip DIE1 is selected to test the digital circuit module NPL1 of the first chip DIE1, and the fourth loop path of the second chip DIE2 is selected to test the digital circuit module NPL2 of the fourth chip.

For example, the third loop path of the first chip DIE1 is selected to transmit the fifth internal test data tx_data13 and receive the third internal result data rx_data13 corresponding to the fifth internal test data tx_data13. For example, a fourth loop-back path of the second chip DIE2 is selected to transmit the sixth internal test data tx_data23 and receive fourth internal result data rx_data23 corresponding to the sixth internal test data tx_data23.

For example, in at least one embodiment, the above test method further comprises: and responding to the test result error of the third test mode, and determining that the digital circuit modules of the first chip DIE1 and the second chip DIE2 work abnormally.

For example, comparing the third internal result data rx_data13 of the first chip DIE1 with the fifth internal test data tx_data13, if the two are the same, it is indicated that the digital circuit module NPL1 of the first chip DIE1 is normal; if the two are different, the digital circuit module NPL1 of the first chip DIE1 has faults.

For example, comparing the fourth internal result data rx_data23 of the second chip DIE2 with the sixth internal test data tx_data23, if the two are the same, it is indicated that the digital circuit module NPL2 of the second chip DIE2 is normal; if the two are different, it is indicated that the digital circuit module NPL2 of the second chip DIE2 has a fault.

For example, in at least one embodiment, the above test method further comprises: and determining that the analog circuit modules of the first chip DIE1 and the second chip DIE2 work abnormally in response to the fact that the test result of the second test mode is wrong and the test result of the third test mode is correct.

For example, for the first chip DIE1, if the second test mode is executed to indicate that at least one of the digital circuit module NPL1 and the analog circuit module PMA1 of the first chip DIE1 has a fault, the third test mode may be executed again to further determine whether the digital circuit module NPL1 has a fault or the analog circuit module PMA1 has a fault. For example, if the third test mode shows that the digital circuit module NPL1 is working properly, it is indicated that the analog circuit module PMA1 is malfunctioning. The positioning detection process of the digital circuit module NPL2 and the analog circuit module PMA2 of the second chip DIE2 is similar to the detection process of the first chip DIE1, and will not be repeated here.

As described above, after the first test mode and the second test mode are performed on the first chip DIE1 and the second chip DIE2, it can be detected that a failure occurs in the section of the transmission driver TXD, the reception driver RXD, and the package connection member which are relatively vulnerable, but it is still not possible to determine whether there is a failure of the data channel within the transmission driver TXD of the first chip DIE1, the reception driver RXD of the DIE2 of the second chip, or the package connection member IP. Thus, at least some embodiments of the present disclosure provide further segmented test paths to more accurately locate whether a fault occurred in TXD, RXD, or IP.

Fig. 10 is a schematic diagram of a fourth test mode provided by at least one embodiment of the present disclosure, as shown by the dashed line in fig. 10, in the integrated circuit device provided by at least some embodiments of the present disclosure, the first chip DIE1 further includes a second transmission path, and the second chip DIE2 further includes a second reception path, wherein the second transmission path includes a first conductive connection C1 connected to the transmission driver TXD, and the second reception path includes a second conductive connection C2 connected to the reception driver RXD.

For example, in at least some embodiments of the present disclosure, the transmit driver TXD and the receive driver RXD are configured to be connectable with an external detection device through a first conductive connection C1 and a second conductive connection C2, respectively. For example, the external detection device may be an oscilloscope or a probe in wafer testing, etc., to which embodiments of the present disclosure are not limited.

For example, the first conductive connector C1 and the second conductive connector C2 include conductive bumps, such as controlled collapse chip connection (Controlled collapsed chip connection, C4) bumps, as embodiments of the disclosure are not limited in this regard.

For example, the second transmission path transmits fourth internal test data tx_data14 internally generated by the first chip DIE1, to the outside of the first chip DIE1 through the transmission driver TXD, for example, to an external inspection device connected to the first chip DIE 1.

For example, the second reception path receives the first external test data ex_data2 from the external inspection device connected to the second chip DIE2 through the reception driver RXD, and the second external result data rx_data24 corresponding to the first external test data ex_data2 is received by the internal signal verification device (e.g., PRBS verifier) of the second chip DIE 2.

It should be noted that, in some embodiments of the present disclosure, the first transmission path in the first test mode and the second transmission path in the fourth test mode both pass through the same functional module, and the first transmission path and the second transmission path only differ in that internal test data is transmitted to the second chip DIE2 or the external detection device, so as to ensure that whether the functional module works normally or not, whether the transmission driver TXD fails or not can be determined by comparing the detection results of the first transmission path and the second transmission path. Similarly, the first receiving path in the first test mode and the second receiving path in the fourth test mode both pass through the same functional module, and the first receiving path and the second receiving path differ only in whether the test data is from the second chip DIE2 or the external test device, for example, the first receiving path in the first test mode receives the second internal test data tx_data12 from the inside of the second chip DIE2, and the second receiving path in the fourth test mode receives the first external test data ex_data2 from the external test device.

For example, the first internal test data tx_data11 and the fourth internal test data tx_data14 may be the same test pattern or test vector, or may be different test patterns or test vectors. For example, in at least one embodiment of the present disclosure, the first internal test data tx_data11 and the fourth internal test data tx_data14 are the same test pattern, thereby facilitating more visual and quick comparison of test results of the test pattern after passing through the first transmission path and the second transmission path.

For example, in at least one embodiment, the above test method further comprises: a fourth test mode is performed on the integrated circuit device. For example, the second transmission path of the first chip DIE1 is selected to transmit the fourth internal test data tx_data14 of the first chip DIE1 through the transmission driver TXD connected to the first conductive connection C1, and the second reception path of the second chip DIE2 is selected to receive the first external test data ex_data2 through the reception driver RXD connected to the second conductive connection C2.

For example, as shown in fig. 10, the external inspection apparatus receives the first external result data ex_data1 corresponding to the fourth internal test data tx_data14 and compares the first external result data ex_data1 with expected result data of the fourth internal test data tx_data14, and if the first external result data ex_data1 and the expected result data are identical, it is illustrated that the digital circuit module NPL1, the analog circuit module PMA1 and the transmission driver TXD of the first chip DIE1 are normal; if the first external result data ex_data1 and the expected result data are not identical, it is indicated that at least one of the digital circuit module NPL1, the analog circuit module PMA1 and the transmit driver TXD of the first chip DIE1 is faulty.

For example, in at least one embodiment, the above test method further comprises: and responding to the error of the test result of the fourth test mode for testing the first chip DIE1 and the correct test result of the second test mode, and determining that the TXD of the transmission driver of the first chip DIE1 works abnormally.

For example, as shown in fig. 10, the internal signal verification device of the second chip receives the second external result data rx_data24 corresponding to the first external test data ex_data2 and compares the second external result data rx_data24 with expected result data of the first external test data ex_data2, and if the second external result data tx_data24 and the expected result data are identical, it is indicated that the digital circuit module NPL2, the analog circuit module PMA2 and the receiving driver RXD of the second chip DIE2 are normal; if the second external result data tx_data24 and the expected result data are not identical, it is indicated that at least one of the digital circuit module NPL2, the analog circuit module PMA2 and the receiving driver RXD of the second chip DIE2 has a fault.

For example, in at least one embodiment, the above test method further comprises: and responding to the error of the test result of the fourth test mode for testing the second chip DIE2 and the correct test result of the second test mode, and determining that the receiving driver RXD of the second chip DIE2 works abnormally.

For example, in at least one embodiment, the above test method further comprises: and determining that the data channel of the packaging connecting member works abnormally in response to the fact that the test result of the fourth test mode for testing the first chip DIE1 and the second chip DIE2 is correct and the test result of the second test mode is incorrect.

The test method realizes segment detection by comparing the test results of the second test mode and the fourth test mode, and can further accurately position whether the transmitting driver TXD of the first chip DIE1, the package connecting member IP or the receiving driver RXD of the second chip DIE2 has faults, thereby greatly improving the testability of advanced packaging, reducing the test cost and accelerating the test process.

As described above, the fourth test mode is capable of separately testing the failure condition of the first chip DIE1 and the second chip DIE2, respectively, but since in the fourth test mode, the test data of the first chip DIE1 is still generated internally by the first chip, there is a case that the test data generated by the first chip DIE1 is itself erroneous, in order to further eliminate the problem of the signal source, and to test the integrity of the entire link of the first chip DIE1 to the second chip DIE2 and the quality of the real-time observation signal, at least one embodiment of the present disclosure also provides a detection method of the fifth test mode, in which a variable test signal is provided through the entire link of the first chip DIE1 to the second chip DIE2 by an external detection device.

Fig. 11 is a schematic diagram of a fifth test mode according to at least one embodiment of the present disclosure.

For example, in at least one embodiment, the above test method further comprises: a fifth test mode is performed on the integrated circuit device, for example, selecting the second reception path of the second chip DIE2 to receive the second external test data etx _data received from the external test device through the second conductive connector C2 connected to the reception driver RXD, and selecting the second transmission path of the first chip DIE1 to transmit the external result data erx _data corresponding to the second external test data etx _data to the external test device through the first conductive connector C1 connected to the transmission driver TXD.

For example, in at least one embodiment, the above test method further comprises: the second external test data etx _data and the external result data erx _data are observed by the external inspection device.

For example, in this embodiment, the external detection device is an oscilloscope. For example, the oscilloscope is used as a signal source to generate a test signal etx _data different from the test data in the first chip, the second external test data etx _data enters the second chip DIE2 through the receiving end of the second chip DIE2, after passing through the second chip DIE2 and the first chip DIE1, the signal is sent to the oscilloscope by the sending end of the first chip DIE1, the external result data erx _data corresponding to the second external test data etx _data is displayed by the oscilloscope, and the change condition of the test signal after passing through the whole complete communication link can be obtained quickly and intuitively by observing the external result data erx _data, that is, whether the result data is correct or not can be observed, and the advantages and disadvantages of the result data can be observed, for example, the problems of error rate and signal integrity of the test signal can be determined.

According to the testing method, the circuit connection and communication conditions of the first chip DIE1 to the second chip DIE2 can be more conveniently and completely detected by observing the testing result of the fifth testing mode in real time, and subsequent debugging and improvement can be better assisted according to the trend of the testing signals, so that the testability of advanced packaging is greatly improved, the testing cost is reduced, and the testing process is accelerated.

At least some embodiments of the present disclosure may perform one or more of the first test mode, the second test mode, the third test mode, the fourth test mode, and the fifth test mode described above on a first chip and a second chip in an integrated circuit device, and may precisely locate a fault module in the integrated circuit device through a combination of any two test modes. It should be noted that, the execution sequence of the plurality of test modes is not limited in the embodiments of the present disclosure, and those skilled in the art may flexibly select the plurality of test modes and arrange the execution sequence of the plurality of test modes according to actual test requirements.

Fig. 12 is a flow chart of a testing method according to at least one embodiment of the present disclosure. For example, only the case of a test result error in the first to fourth test modes is shown in fig. 12, and the test method may sequentially detect the correctness of the digital circuit modules (NPL 1, NPL 2), analog circuit modules (PMA 1, PMA 2), TXD, RXD, and the package connection member IP of the first chip DIE1 and the second chip DIE2 in sections.

For example, as shown in fig. 12, a third test mode is first performed on the integrated circuit device to test the correctness of the digital circuit modules of the first chip DIE1 and the second chip DIE2, respectively.

For example, a third loop path of the first chip DIE1 is selected to test the digital circuit module of the first chip DIE1 and/or a fourth loop path of the second chip DIE2 is selected to test the digital circuit module of the fourth chip. For example, if the test result after the third test mode is executed is not identical to the expected test result, it may be first determined that the digital ports of the first chip DIE1 and/or the second chip DIE2 are abnormally operated.

For example, if the test result after the third test mode is executed is correct, which indicates that the digital ports of the first chip DIE1 and/or the second chip DIE2 can work normally, the second test mode may be executed continuously to test the correctness of the analog circuit modules of the first chip DIE1 and the second chip DIE2 respectively. For example, the second test mode may be applied in the CP phase.

For example, a first loop-back path of the first chip DIE1 is selected to bypass the analog circuit module PMA1 of the first chip DIE1 tested by the transmit driver TXD and/or a second loop-back path of the second chip DIE2 is selected to bypass the analog circuit module PMA2 of the second chip tested by the receive driver RXD. For example, if the test result after the second test mode is executed is not the same as the expected test result, it may be determined that the analog circuit module of the first chip DIE1 and/or the second chip DIE2 is abnormally operated.

For example, if the test results after the third test mode is performed on the first chip DIE1 and the second chip DIE2 are correct, which means that the analog circuit modules of the first chip DIE1 and the second chip DIE2 can each operate normally, the first test mode may be continuously performed to test whether a failure occurs in the high speed section, for example, to test the correctness of the data channels in the transmission driver TXD of the first chip DIE1, the reception driver RXD of the second chip DIE2, and the package connection member IP. For example, a third test mode may be applied in the FT phase

For example, the first transmission path of the first chip DIE1 is selected to transmit the first internal test data tx_data11 through the transmission driver TXD, and the first reception path of the second chip DIE2 is selected to receive the first result data rx_data21 corresponding to the first internal test data tx_data11 through the reception driver RXD. For example, if the test result after the execution of the first test mode is different from the expected test result, it may be determined that a failure occurs in the high-speed block, and it may be that one of the transmit driver TXD of the first chip DIE1, the receive driver RXD of the second chip DIE2, and the data path within the package connection member IP has failed.

For example, it is possible to continue to perform the fourth test mode on the first chip DIE1 and the second chip DIE2, respectively, to test whether a failure occurs in the transmit driver TXD of the first chip DIE1, the receive driver RXD of the second chip DIE2, or the data path within the package connection member IP. For example, the second test mode may be applied to a stage of platform testing.

According to the test method provided by the embodiment, through the sequential detection of the plurality of test modes and the combination comparison of the test results, the abnormal modules in the chip can be detected in an omnibearing and accurate segmented manner, so that the test cost is reduced, the test process is accelerated, and the follow-up debugging and improvement are facilitated.

While the disclosure has been described in detail with respect to the general description and the specific embodiments thereof, it will be apparent to those skilled in the art that certain modifications and improvements may be made thereto based on the embodiments of the disclosure. Accordingly, such modifications or improvements may be made without departing from the spirit of the disclosure and are intended to be within the scope of the disclosure as claimed.

For the purposes of this disclosure, the following points are also noted:

(1) The drawings of the embodiments of the present disclosure relate only to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

(2) In the drawings for describing embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced for clarity, i.e., the drawings are not drawn to actual scale.

(3) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.

The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.

Claims (16)

1. A method of testing, comprising:

the first test mode and the second test mode are performed on the integrated circuit device for testing,

the integrated circuit device comprises a first chip, a second chip and a packaging connecting component, wherein a transmitting driver of the first chip and a receiving driver of the second chip are connected through a data channel in the packaging connecting component;

the executing the first test mode includes:

selecting a first transmission path of the first chip to transmit first internal test data through the transmission driver, and selecting a first reception path of the second chip to receive first result data corresponding to the first internal test data through the reception driver;

The executing the second test mode includes:

a first loopback path of the first chip is selected to bypass the transmit driver to transmit second internal test data and receive first internal result data corresponding to the second internal test data, and a second loopback path of the second chip is selected to bypass the receive driver to receive second internal result data corresponding to third internal test data of the second chip.

2. The test method of claim 1, further comprising:

in response to a test result of the first test mode being incorrect and a test result of the second test mode being correct, determining that at least one of the transmit driver of the first chip, the package connection member, and the receive driver of the second chip is malfunctioning.

3. The test method of claim 1, wherein the first chip or the second chip further comprises an analog circuit module and a digital circuit module, the digital circuit module providing a signal to the analog circuit module, the analog circuit module providing a signal to the transmit driver or the receive driver,

the first transmitting path and the first loopback path of the first chip pass through an analog circuit module and a digital circuit module of the first chip;

The first receiving path and the second loop-back path of the second chip both pass through an analog circuit module and a digital circuit module of the second chip.

4. The test method of claim 3, further comprising:

a third test mode is performed on the integrated circuit device,

wherein said executing said third test pattern comprises:

and selecting a third loop path of the first chip to test the digital circuit module of the first chip, and selecting a fourth loop path of the second chip to test the digital circuit module of the fourth chip.

5. The test method of claim 4, further comprising:

responding to the test result error of the third test mode, and determining that the digital circuit modules of the first chip and the second chip work abnormally;

and determining that the analog circuit modules of the first chip and the second chip work abnormally in response to the fact that the test result of the second test mode is wrong and the test result of the third test mode is correct.

6. The test method of any one of claims 1-5, further comprising:

a fourth test mode is performed on the integrated circuit device,

wherein said executing said fourth test pattern comprises:

And selecting a second transmitting path of the first chip to transmit fourth internal test data of the first chip through the transmitting driver connected with the first conductive connecting piece, and selecting a second receiving path of the second chip to receive first external test data through the receiving driver connected with the second conductive connecting piece.

7. The test method of claim 6, further comprising:

determining that the transmission driver of the first chip works abnormally in response to the fact that the test result of the fourth test mode for testing the first chip is wrong and the test result of the second test mode is correct;

determining that the receiving driver of the second chip works abnormally in response to the fact that the test result of the fourth test mode for testing the second chip is wrong and the test result of the second test mode is correct;

and determining that the data channel of the packaging connecting member works abnormally in response to the fourth test mode that the test result of the fourth test mode for testing the first chip and the second chip is correct and the test result of the second test mode is incorrect.

8. The test method of claim 7, wherein the transmit driver and the receive driver are configured to be connectable with an external test device through the first conductive connection and the second conductive connection, respectively.

9. The test method of claim 8, further comprising:

a fifth test mode is performed on the integrated circuit device,

wherein said executing said fifth test pattern comprises:

the second receiving path of the second chip is selected to receive second external test data transmitted from the external test device through the second conductive connection to the receiving driver, and the second transmitting path of the first chip is selected to transmit external result data corresponding to the second external test data to the external test device through the first conductive connection to the transmitting driver.

10. The test method of claim 9, further comprising:

observing, by the external detection device, the second external test data and the external result data.

11. An integrated circuit device, comprising:

a first chip including a first transmission path for transmitting first internal test data through a transmission driver and a first loopback path for transmitting second internal test data bypassing the transmission driver,

the first chip receives first internal result data corresponding to the second internal test data through the first loop path.

12. The integrated circuit device of claim 11, further comprising: a second chip and a package connection member,

wherein the second chip comprises a first receive path for receiving first result data via a receive driver and a second loop-back path for receiving second internal result data bypassing the receive driver,

the second chip receives the second internal result data corresponding to the third internal test data of the second chip through the second loop circuit,

the transmit driver of the first chip and the receive driver of the second chip are connected by a data channel within a package connection member.

13. The integrated circuit device of claim 12, wherein the first chip or the second chip further comprises an analog circuit module and a digital circuit module, the digital circuit module providing signals to the analog circuit module, the analog circuit module providing signals to the transmit driver or the receive driver,

the first transmitting path and the first loopback path of the first chip pass through an analog circuit module and a digital circuit module of the first chip;

the first receiving path and the second loop-back path of the second chip both pass through an analog circuit module and a digital circuit module of the second chip.

14. The integrated circuit device of claim 13, wherein the first chip further comprises a third loop-back path through only digital circuit modules of the first chip, the second chip further comprises a fourth loop-back path through only digital circuit modules of the second chip,

the third loop-back path and the fourth loop-back path are used for testing digital ports of the first chip and the second chip respectively.

15. The integrated circuit device of any of claims 12-14, wherein the first chip further comprises a second transmit path, the second chip further comprises a second receive path,

wherein the second transmit path includes a first conductive connection to the transmit driver and the second receive path includes a second conductive connection to the receive driver.

16. The integrated circuit device of claim 15, wherein the transmit driver and the receive driver are configured to be connectable with an external detection device through the first conductive connection and the second conductive connection, respectively.