WO2022126655A1

WO2022126655A1 - Data processing method and device, and data processing system of board card

Info

Publication number: WO2022126655A1
Application number: PCT/CN2020/137777
Authority: WO
Inventors: 黄小雄; 周晶晶
Original assignee: 西安诺瓦星云科技股份有限公司
Priority date: 2020-12-18
Filing date: 2020-12-18
Publication date: 2022-06-23
Also published as: CN115004622A; CN115004622B

Abstract

Disclosed in the present invention are a data processing method and device, and a data processing system of a board card. A first chip communicates with a second chip by means of low voltage differential signaling. The data processing method comprises: after a first chip is powered on, locking a receiving phase to each first phase to be tested in a first set of phases to be tested; each time after the receiving phase is locked to one first phase to be tested, the first chip receiving a test package sent by a second chip, and determining a receiving state so as to obtain a receiving state corresponding to each first phase to be tested; the first chip determining, according to the receiving state corresponding to each first phase to be tested, a first target phase corresponding to the receiving phase; and the first chip locking the receiving phase to the first target phase so as to enable a receiving port of the first chip to communicate with the second chip under the first target phase. By means of the present invention, the technical problem in the prior art of data transmission being unstable when an LVDS communication link is used for communication between chips is solved.

Description

Data processing method and device, data processing system of board card

technical field

The present invention relates to the field of communication technologies, and in particular, to a data processing method and device, and a data processing system of a board card.

Background technique

A board is a common printed circuit board used to control the operation of hardware. At present, communication links between boards and chips on boards are mainly established through interface chips such as 100M PHY (Physical Layer, port physical layer) to achieve interconnection, but interface chips such as PHY have certain requirements for data transmission speed and wiring resources. limitations. Compared with the communication link established by the PHY interface chip, the LVDS (Low Voltage Differential Signaling, abbreviation for Low Voltage Differential Signaling) communication link is a data transmission technology based on low-swing differential signals, with low power consumption, low error The advantages of code rate, low crosstalk and low radiation can not only increase the data transmission rate, but also reduce the limitations brought by wiring resources and interface chips. However, the interconnection method established by the existing LVDS communication link will cause the phase shift between the boards, which in turn leads to unstable data transmission, which limits the application of the LVDS communication link in the interconnection between the boards.

Aiming at the technical problem of unstable data transmission in the above-mentioned prior art when the LVDS communication link is used for communication between chips, an effective solution has not yet been proposed.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a data processing method and device, and a data processing system for a board card, so as to at least solve the technical problem of unstable data transmission when an LVDS communication link is used for communication between chips.

According to an aspect of the embodiments of the present invention, a data processing method is provided, including: communicating between a first chip and a second chip through a low-voltage differential signal, and the data processing method includes: after the first chip is powered on, receiving The phase is locked to each first phase to be measured in the first group of phases to be measured; after the receiving phase is locked to a first phase to be measured each time, the first chip receives the test packet sent by the second chip and determines the receiving state to obtain the receiving state corresponding to each first phase to be measured; the first chip determines the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured; the first chip locks the receiving phase to the first target phase for the receive port of the first chip to communicate with the second chip at the first target phase.

Further, the first group of phases to be measured is obtained based on the clock cycle of the signal received by the first chip and the preset number of phases; or, the difference between two adjacent first phases to be measured in the first group of phases to be measured is the clock. Period divided by the preset number of phases.

Further, after the receiving phase is locked to the first phase to be measured each time, the first chip receives the test packet sent by the second chip, and determines the receiving state, and obtains the receiving state corresponding to each first phase to be measured, including: A chip receives multiple consecutive test packets sent by the second chip; if the first chip receives all the consecutive multiple test packets correctly, it is determined that the first chip is in the current receiving state of the first phase to be tested as the receiving state; if the first chip receives all the consecutive multiple test packets correctly; A chip receives errors or fails to receive any one or more test packets over time, and determines that the receiving state of the first chip in the current first phase to be tested is a receiving error state.

Further, determining the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured includes: determining that the first phase to be measured whose receiving state is a receiving correct state is the first target phase corresponding to the receiving phase.

Further, when the receiving state is that the first phase to be measured in the receiving state is a plurality of consecutive phases, it is determined that the first phase to be measured in the receiving state is the receiving correct state is the first target phase corresponding to the above-mentioned receiving phase, including: : Determine the phase in the center of the multiple consecutive phases as the first target phase corresponding to the receiving phase.

Further, the above method also includes: the first chip locks the transmission phase to each second phase to be measured in the second group of phases to be measured; The chip sends a test packet, wherein after the first chip sends the test packet to the second chip, the second chip returns the receiving state of the test packet to the first chip; the first chip receives the receiving state of the test packet, according to the receiving state of the test packet Determine the transmission state corresponding to each second phase to be measured; determine the second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured; the first chip locks the transmission phase to the second target phase, wherein, The transmit port of the first chip communicates with the second chip at the second target phase.

Further, the first chip receives the reception state of the test package, and determines the corresponding transmission state of each second phase to be tested according to the reception state of the test package, including: if the reception state of the test package is all received correctly, determine the second phase to be tested. The sending state corresponding to the phase is the correct sending state; if the receiving state of any one or more test packets is the receiving error or the timeout is not received, it is determined that the sending state corresponding to the second phase to be tested is the sending error state.

Further, determining the second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured includes: determining that the second phase to be measured whose transmission state is the correct transmission state is the second target phase corresponding to the transmission phase.

Further, in the case where the second phase to be measured whose transmission state is the correct transmission state is a plurality of continuous phases, it is determined that the second phase to be measured whose transmission state is the correct transmission state is the second target phase corresponding to the transmission phase, including: The middle phase among the multiple consecutive phases is determined as the first target phase corresponding to the transmission phase.

Further, after the first chip locks the transmission phase to the second target phase, the method further includes: the first chip sends a completion packet to the second chip; wherein, after receiving the test packet, the second chip determines whether the test packet is To complete the package, if the test package is a complete package, the second chip and the first chip enter the communication mode; if the test package is not a complete package, the second chip returns the receiving state of the test package to the first chip.

Further, the second group of phases to be measured is obtained based on the clock cycle of the signal sent by the first chip and the preset number of phases, or the difference between two adjacent first phases to be measured in the first group of phases to be measured is the first The clock period the chip sends the signal is divided by the preset number of phases.

Further, the number of the first chips is multiple, the multiple first chips are arranged on multiple different first boards, the second chips are arranged on the second boards, and the second boards are connected to the multiple first boards. Each board in the card communicates.

Further, the first chip and the second chip are both FPGA chips, and the receiving phase is respectively locked to each first phase to be measured in the first group of phases to be measured by the clock manager in the first chip.

Further, after the first chip locks the transmission phase to the second target phase, the above method further includes: the first chip communicates with the second chip, and the step of the first chip communicating with the second chip includes: the first chip The data to be transmitted is encapsulated according to preset rules to obtain an encapsulated data packet; the first chip encodes the encapsulated data packet to obtain an encoding result; the first chip scrambles the encoding result to obtain a scrambled result; the first chip scrambles The result is subjected to parallel-to-serial conversion, and the data packet obtained after the parallel-to-serial conversion is sent to the second chip; wherein the second chip receives the data packet sent by the first chip, performs serial-to-parallel conversion on the received data packet, and performs serial-to-parallel conversion on the received data packet. And the conversion result is descrambled, the descramble result is decoded, the encapsulation result of the data to be transmitted is obtained, and the verification is performed according to the encapsulation result, and if the verification is correct, the data to be transmitted is sent to the corresponding processing unit.

According to another aspect of the embodiments of the present invention, a data processing method is further provided, including: when the second chip on the second board detects an idle code sent by the first chip on the first board A chip sends a test packet; until the second chip detects the completion packet sent by the first chip, the second chip stops sending the test packet.

Further, the second chip communicates with a plurality of first chips through low-voltage differential signals, and the data processing method includes: a receiving port of the second chip collects a test packet sent by the first chip, wherein the first chip will send the phase Lock to each second phase to be tested in the second group of phases to be tested, and after the transmission phase is locked to a second phase to be tested each time, send a test packet to the second chip; the second chip judges whether the test packet is correct The second chip returns the receiving state of the test package to the first chip according to the judgment result; wherein, the first chip receives the receiving state of the test package, determines the corresponding transmission state of each second phase to be measured according to the receiving state of the test package, and The second target phase corresponding to the transmission phase is determined according to the transmission state corresponding to each second phase to be measured.

Further, when the second chip judges that the test package is correct, after the second chip returns the receiving state of the test package to the first chip according to the judgment result, the method further includes: the second chip judges whether the test package is a completed package, Wherein, after the first chip determines the second target phase of the sending port, it sends a completion packet to the second chip; if the test packet is a completion packet, the second chip and the first chip enter the communication mode; if the test packet is not a completion packet, enter the first chip The receiving port of the second chip collects the test packet sent by the first chip.

According to another aspect of the embodiments of the present invention, a data processing apparatus is also provided, in which the first chip and the second chip communicate through low-voltage differential signals, and the data processing apparatus includes: a phase locking module for After a chip is powered on, the receiving phase is locked to each first phase to be measured in the first group of phases to be measured; the phase test module is used to make the first phase to be measured after the receiving phase is locked to a first phase to be measured each time. A chip receives the test packet sent by the second chip, determines the receiving state, and obtains the receiving state corresponding to each first phase to be measured; the phase selection module is used for the first chip to obtain the receiving state corresponding to each first phase to be measured. Determine the first target phase corresponding to the receiving phase; the phase adjustment module is used to make the first chip lock the receiving phase to the first target phase, so that the receiving port of the first chip can perform the first target phase with the second chip under the first target phase. communication.

According to another aspect of the embodiments of the present invention, a data processing apparatus is further provided, which is characterized by comprising: a sending module for detecting the first chip on the first board by the second chip on the second board When the idle code is sent, continue to send the test packet to the first chip; stop the sending module, which is used to stop sending the second chip until the second chip detects the completion packet sent by the first chip. test package.

According to another aspect of the embodiments of the present invention, a data processing system for board cards is further provided, including a plurality of first board cards and a second board card, wherein the first board cards and the second board cards are both disposed on the backplane Above, each first board communicates with the second board through low-voltage differential signals, and the second board is used to send a test packet to the first board; the first board is used to The receiving phase is respectively locked to each first phase to be measured in the first group of phases to be measured, receives the test packet sent by the second board, and determines the receiving state, and obtains the receiving state corresponding to each first phase to be measured; A board is further configured to determine the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured, so that the receiving port of the first board can perform the communication with the second board under the first target phase. communication; the first board is also used to lock the transmission phase to each second phase to be measured in the second group of The card sends the test package; the second board is also used to judge whether the test package is correct, and returns the receiving state of the test package to the first board according to the judgment result; the first board is also used to receive the receiving state of the test package, according to the test The reception state of the packet determines the transmission state corresponding to each second phase to be measured, and determines the second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured.

According to another aspect of the embodiments of the present invention, a data processing system for a board is also provided, including a first board and a second board, both of which are arranged between the backplane On, the first board and the second board communicate through low-voltage differential signals, and the second board is used to send test packets to the first board; the first board is used to separate the receiving phases after power-on Lock to each first phase to be tested in the first group of phases to be tested, receive the test packet sent by the second board, and determine the receiving state to obtain the receiving state corresponding to each first phase to be tested; the first board It is also used to determine the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured, so that the receiving port of the first board card communicates with the second board card under the first target phase; The first board is also used to send the test package to the second board; the second board is also used to lock the receiving phase to each third phase to be measured in the third group of phases to be measured after power-on, respectively, to receive The test package sent by the first board card, and the receiving state is determined, and the receiving state corresponding to each third phase to be tested is obtained; the second board card is also used to determine the corresponding receiving phase according to the receiving state corresponding to each third phase to be tested. The third target phase is used for the receiving port of the second board to communicate with the first board in the third target phase.

According to another aspect of the embodiments of the present invention, a storage medium is further provided, including a stored program, wherein when the program is run, a device where the storage medium is located is controlled to execute the above data processing method.

According to another aspect of the embodiments of the present invention, a processor is further provided for running a program, wherein the data processing method is executed when the program is running.

In the embodiment of the present invention, by determining the data transmission state of the second chip and the receiving state of the data of the first chip under the corresponding phase, the optimal phase is selected, and the receiving phase of the clock of the first chip is adjusted accordingly, so as to realize the first chip. The phase of the chip is consistent with the phase of the second chip, which avoids the phase shift between chips in the LVDS communication link, improves the data transmission stability and data transmission efficiency of the LVDS communication link, and solves the problem in the prior art. The technical problem of unstable data transmission when the LVDS communication link is used for communication between chips.

Description of drawings

The accompanying drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached image:

1 is a flowchart of a data processing method according to an embodiment of the present invention;

2a is a flowchart of a data processing method according to an embodiment of the present invention;

2a is a flowchart of an optional data processing method according to an embodiment of the present invention;

3 is a flowchart of an optional data processing method according to an embodiment of the present invention;

4 is a flowchart of an optional data processing method according to an embodiment of the present invention;

5 is a schematic diagram of an optional LVDS communication module;

6 is a schematic diagram of an optional data processing method according to an embodiment of the present invention;

7 is a schematic diagram of a data processing apparatus according to an embodiment of the present invention;

8 is a schematic diagram of another data processing apparatus according to an embodiment of the present invention;

9 is a schematic diagram of a data processing system for a board card according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a data processing system of a board card according to an embodiment of the present invention.

Detailed ways

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used may be interchanged under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

The data transmission or reception between the first board and the second board in the following implementation is actually the communication method between the chip on the first board and the chip on the second board (that is, the Inter-chip communication), the communication between the first chip and the second chip, including the communication between different chips on the same board and the chip communication between different boards.

Example 1

According to an embodiment of the present invention, an embodiment of a data processing method for a board card is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.

FIG. 1 is a data processing method according to an embodiment of the present invention, which includes: a low-voltage differential signal communicates between a first chip and a second chip. As shown in FIG. 1 , the method includes the following steps:

Step S101 , after the first chip is powered on, the receiving phase is locked to each first phase to be measured in the first group of phases to be measured.

The receiving phase locking of the above-mentioned first chip can be completed by MMCM (Mixed Mode Clock Manager, mode clock manager). The above-mentioned first group of phases to be measured includes a plurality of first phases to be measured, and it is necessary to lock each of the first phases to be measured, so as to realize the data transmission test under each of the first phases to be measured. Optionally, the first group of phases to be measured includes at least 32 first phases to be measured.

It should be noted that, after the first chip is powered on, the MMCM can be automatically triggered to lock the receiving phase, or the MMCM can be controlled to achieve phase locking by manually sending an instruction. The above-mentioned first chip and second chip may be chips on the same board or chips on different boards.

Step S102 , after the receiving phase is locked to a first phase to be measured each time, the first chip receives the test packet sent by the second chip, and determines the receiving state to obtain the receiving state corresponding to each first phase to be measured.

The above test packets include data sequences. The reception status includes correct reception (represented by 1) and reception error (represented by 0), wherein the reception correct status includes that the test packet data received by the first chip is correct, and the reception error status includes that the first chip receives the test packet data error Or the first chip times out and does not receive the test packet. If the receiving state is correct, it means that the receiving clock of the first chip is in the current phase, and the receiving port can receive data accurately.

Each first phase to be measured in the first group of phases to be measured will have a definite receiving state. For example, if the first group of phases to be measured contains N first phases to be measured in total, then according to step S102, it will be obtained N receiving states corresponding to the first phase to be measured one-to-one, where N is an integer.

Step S103, the first chip determines the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured;

The above-mentioned first target phase can be understood as the best phase selected according to the receiving state of the first chip in the first group of phases to be measured, and the first target phase should be the first phase to be measured with the correct receiving state, so that the The data sequence received by the first chip in the first target phase is consistent with the data sequence sent by the second chip. For example, for the N first phases to be measured in the first group of phases to be measured, N corresponding receiving states are obtained respectively, and the first target phase can be screened and determined from the first phases to be measured whose receiving states are correct. .

Step S104, the first chip locks the receiving phase to the first target phase, so that the receiving port of the first chip can communicate with the second chip under the first target phase.

According to the first target phase screened in step S103, adjust the clock of the receiving port of the first chip to the first target phase, and complete the adjustment of the clock phase of the receiving port of the first chip, so that the receiving port of the first chip is optimal phase.

In the above steps, the second chip is used as the data sending end, the first chip is used as the data receiving end, and the phase of the receiving port of the first chip is adjusted to the first target phase. It can be considered that the above steps S101-S104 realize the downlink of the first chip. The taming process of the link, the downlink after taming is stable.

It should be noted that, when two chips A and B that communicate through LVDS are in one-to-one correspondence, the above-mentioned first chip may be any one of chip A and chip B. In an optional embodiment, chip A is used as the first chip and chip B is used as the second chip to complete the downlink taming of chip A; then chip B is used as the first chip, and chip B is used as the first chip. Chip A is used as the second chip to complete the downlink taming of chip B. Through the above two times of taming, the transceiver between chip A and chip B can be in a stable state.

Through the above steps, by determining the data transmission state of the second chip and the receiving state of the first chip data under the corresponding phase, the optimal phase is screened out, and the receiving phase of the first chip clock is adjusted accordingly based on the optimal phase, thereby avoiding The phase offset between chips in the LVDS communication link improves the stability of data transmission and the efficiency of data transmission in the LVDS communication link, thereby solving the problem of inconsistency in data transmission when the LVDS communication link is used for communication between chips in the prior art. Stable technical issues.

As an optional embodiment, the first group of phases to be measured is obtained based on the clock period of the signal received by the first chip and the preset number of phases; or, the difference between two adjacent first phases to be measured in the first group of phases to be measured The difference is the clock period divided by the preset number of phases.

The above-mentioned preset number of phases can be understood as the number of phases in the first group of phases to be measured. For example, if the clock cycle of the first chip receiving the signal is 50ns, and the preset number of phases can be selected as 32, then the number of phases to be measured in the first group of phases is 50ns. The difference between two adjacent first phases to be measured is 50ns/32. Set the initial value of the first phase to be measured, and increase or decrease the initial value in steps of 50ns/32. A plurality of first to-be-measured phases in a group of to-be-measured phases.

As an optional embodiment, after the receiving phase is locked to the first phase to be measured each time, the first chip receives the test packet sent by the second chip, determines the receiving state, and obtains the corresponding value of each first phase to be measured. The receiving state includes: the first chip receives multiple consecutive test packets sent by the second chip; if the first chip receives all the continuous multiple test packets correctly, it is determined that the receiving state of the first chip under the current first phase to be tested is: The receiving state is correct; if the first chip receives any one or more test packets incorrectly or fails to receive it over time, it is determined that the receiving state of the first chip in the current first phase to be tested is a receiving error state.

It should be noted that when the second chip sends multiple test packets in succession, the receiving correct state is only that the data of the multiple test packets are all correct. If the data of a certain test packet or some fields of the data in a certain test packet are wrong or lost in multiple test packets, it belongs to the receiving error state.

According to the above steps, by increasing the number of test packets, the number of samples for data sequence comparison is increased, thereby realizing a more accurate judgment of the receiving state.

As an optional embodiment, determining the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured includes: determining that the first phase to be measured whose receiving state is the correct receiving state is corresponding to the receiving phase the first target phase.

Corresponding to the first target phase, the data of the test packet received by the first chip is consistent with the data of the test packet sent by the second chip, that is, the receiving port of the first chip has an optimal phase, which can be used as the clock phase of the receiving end during normal data transmission. , so that the first chip is in a stable state when receiving data.

Through the above steps, the method for determining the first target phase is clarified, and the problem of how to determine the first target phase of the first chip is solved.

As an optional embodiment, when the first phase to be measured whose receiving state is the correct receiving state is a plurality of consecutive phases, it is determined that the first phase to be measured whose receiving state is the correct receiving state is the one corresponding to the foregoing receiving phase. The first target phase includes: determining the middle phase among the multiple continuous phases as the first target phase corresponding to the receiving phase.

Since the first group of phases to be measured includes a plurality of first phases to be measured, the receiving states corresponding to the plurality of first phases to be measured include a receiving correct state 1 and a receiving error state 0. Typically, the first phase to be measured with the received correct state 1 is a continuous phase. If the phase with the receiving correct state 1 is an even number of consecutive phases, select any one of the two phases in the center position as the first target phase, for example, the first group of phases to be measured includes 7 first phases to be measured , the corresponding receiving state is 0011110 in sequence, from which it can be obtained that the phases with the receiving order of the third, fourth, fifth and sixth have the correct receiving state, then it is determined that the first target phase can be the fourth position. The phase of the bit may be the phase of the fifth bit. If the first phase to be measured with the receiving correct state 1 is an odd number of consecutive phases, the phase in the middle of the bits is selected as the first target phase corresponding to the receiving phase. For example, the first group of phases to be measured includes 6 first phase to be measured. The corresponding receiving states are 001110 in turn. From this, it can be obtained that the phases whose receiving order is the 3rd, 4th, and 5th digit have the correct receiving state. Among them, the phase whose position is the 4th digit is in the middle position, then The phase whose position is determined to be the 4th bit is the first target phase.

Through the above steps, it is achieved that a unique first target phase is determined from a plurality of first phases to be measured that have a receiving correct state, and the method for determining the first target phase is further clarified.

The above-mentioned embodiment proposes the taming process of the chip for the downlink. In the case of one-to-one data transmission between the two chips, the two chips can tame their respective downlinks and then communicate with each other, so that the communication between the two chips is relatively stable. But there is a situation that the second chip communicates with multiple first chips, in this case, if the second chip does its own downlink tame, the operation of the second chip will be very complicated, so In this case, the taming of the uplink is performed by the first chip. The manner in which the first chip performs uplink taming will be described below.

As an optional embodiment, the above data processing method further includes the following steps:

Step S105, the first chip locks the transmission phase to each second phase to be measured in the second group of phases to be measured;

The above-mentioned transmission phase locking of the first chip can be completed by the MMCM, so as to realize the data transmission test under each second phase to be tested. The second group of phases to be measured includes a plurality of second phases to be measured. Optionally, the second group of phases to be measured includes 32 second phases to be measured.

Step S106, after the transmission phase is locked to a second phase to be tested each time, a test packet is sent to the second chip, wherein after the first chip sends the test packet to the second chip, the second chip returns the test to the first chip The reception status of the packet.

The reception status includes correct reception (represented by 1) and reception error (represented by 0). The receiving correct state includes that the data of the test packet received by the second chip is correct (that is, the data in the test packet received by the second chip is the same as the data in the test packet sent by the first chip), and the receiving error state includes the second chip receiving The data to the test packet was wrong or the test packet was not received.

For each second phase to be tested, the second chip will generate a receiving status for determining the test packet, and return the receiving status to the first chip. Optionally, for receiving the correct test packet, the second chip will return the test packet to the first chip.

Step S107 , the first chip receives the reception status of the test packet, and determines the transmission status corresponding to each second phase to be tested according to the reception status of the test packet.

The receiving state of the test package by the second chip should be consistent with the sending state of the test package by the first chip. If the receiving state of the second chip is correct, the sending state of the first chip corresponding to the second phase to be tested can be determined. If the receiving state of the second chip is a receiving error, it can be determined that the sending state of the first chip corresponding to the second phase to be measured is a sending error. For example, for the five locked second phases to be measured, the receiving status returned by the second chip is 00110 in sequence, and the sending status of the first chip corresponding to the group of second phases to be measured is 00110.

Since in this embodiment, the second chip communicates with multiple first chips, if the second chip judges the receiving state of the test packets sent by each first chip, the calculation process is complicated and requires a long working time . Optionally, in the currently locked second phase to be tested, if the first chip receives data in a test packet with the same content sent by the first chip, it is determined that the sending state of the first chip in the second phase to be tested is sending. correct state. In this method, for a test packet with the correct status of receiving, the second chip does not return the direct receiving status to the first chip, but the data of the test packet, and the first chip judges that it has received the test packet by Whether the data packets sent by it are the same to determine the sending state corresponding to the phase. Through this method, the calculation amount of the second chip in the process of judging the receiving state can be reduced.

Step S108: Determine a second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured.

The above-mentioned second target phase can be understood as the best phase selected according to the transmission state of the first chip in the second group of phases to be measured, and the second target phase should be the phase with the correct transmission state, so that the first chip is in the first phase. The data sent in the two target phases is consistent with the data received by the second chip.

Step S109, the first chip locks the transmit phase to the second target phase, wherein the transmit port of the first chip communicates with the second chip under the second target phase

The clock of the transmission port of the first chip is adjusted to the second target phase, and the adjustment of the clock phase of the transmission port of the first chip is completed, that is, the taming of the uplink is completed.

Through the above steps S105-S109, the second chip is used as the test packet data receiving terminal, and the first chip is used as the test packet data transmission terminal. For the phase adjustment of the sending port, it can be considered that the above steps S105-S109 realize the taming of the data uplink between chips.

According to the above steps S101-S109, by adjusting the phase of the MMCM transceiver bidirectional (including data uplink and data downlink) clocks, the bidirectional adjustment of the clocks of the transmitting port and the receiving port of the first chip is completed, solving the problem of It solves the problem of phase deviation in the communication between chips based on LVDS communication link, and solves the problem of unstable data transmission when the communication between chips adopts LVDS communication link. A stable and reliable LVDS communication link is established, which improves the data transmission efficiency.

As an optional embodiment, the first chip receives the reception status of the test packet, and determines the transmission status corresponding to each second phase to be tested according to the reception status of the test packet, including: if the reception status of the test packet is all received correctly , determine that the sending state corresponding to the second phase to be tested is the correct sending state; if the receiving state of any one or more test packets is a receiving error or the timeout is not received, determine that the sending state corresponding to the second phase to be tested is a sending error state .

In the case where each second phase to be tested corresponds to multiple test packets, the receiving state of the second chip is correct, which means that the data of the multiple test packets are all correct, that is, the data of each test packet in the multiple test packets is correct. The reception should be consistent with the data of each test packet sent by the first chip; the reception status of any one or more test packets is reception error or timeout not received, which is understood as the timing error of different test packets or the error in each timing packet. Data errors are all cases where the reception status is an error. Since the receiving state of the second chip to the test packet is consistent with the sending state of the first chip to the test packet, the receiving state of the second chip is correct or incorrect, and it can be determined that the transmitting state corresponding to the second phase to be tested is correct or incorrect state.

According to the above steps, the sending state of the first chip is determined according to the receiving state of the second chip.

As an optional embodiment, determining the second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured includes: determining that the second phase to be measured whose transmission state is the correct transmission state is corresponding to the transmission phase the second target phase.

Corresponding to the second target phase, the data of the test packet sent by the first chip is consistent with the data of the test packet received by the second chip, that is, the sending port of the first chip has the best phase, which can be used as the clock of the sending end during normal data transmission. phase.

The first target phase and the second target phase may be the same or different.

As an optional embodiment, when the second phase to be measured whose transmission state is the correct transmission state is a plurality of consecutive phases, it is determined that the second phase to be measured whose transmission state is the correct transmission state is the first phase corresponding to the transmission phase. Two target phases, including: determining a middle phase among the multiple continuous phases as the first target phase corresponding to the transmission phase.

Since the second group of phases to be measured includes a plurality of phases to be measured, the transmission states corresponding to the plurality of phases to be measured include a transmission correct state 1 and a transmission error state 0. In general, the second phase to be measured with the transmission correct state 1 is a continuous phase. If the phase with the correct state 1 is an even number of consecutive phases, select any one of the two phases in the center position as the second target phase, for example, the second group of phases to be measured contains 7 phases to be measured. , the corresponding sending status is 0011110 in turn, from this, it can be obtained that the phases whose sending order is the 3rd, 4th, 5th and 6th have the correct sending status, then it is determined that the second target phase can be the 4th position. The phase of the bit may be the phase of the fifth bit. If the second phase to be measured with the correct transmission state 1 is an odd number of consecutive phases, the phase in the middle of the bits is selected as the second target phase corresponding to the transmitted phase. For example, the second group of phases to be measured contains 6 If the phase is measured, the corresponding transmission state is 001110 in turn. From this, it can be obtained that the phases whose transmission order is the 3rd, the 4th, and the 5th have the correct transmission state. Among them, the phase whose position is the 4th is in the middle position, then The phase whose position is determined to be the 4th bit is the second target phase.

As an optional embodiment, after the first chip locks the transmission phase to the second target phase, the above method further includes: the first chip sends a completion packet to the second chip; wherein the second chip receives the test packet after receiving the test packet. After that, it is judged whether the test packet is a complete packet, if the test packet is a complete packet, the second chip and the first chip enter the communication mode; if the test packet is not a complete packet, enter the receiving state where the second chip returns the test packet to the first chip A step of.

It should be noted that when the first chip locks the transmission phase to the second target phase, it is understood that the first chip has completed the two-way taming of the uplink and the downlink, and the above completion package indicates that the first chip has completed the two-way taming and can enter the Normal communication mode. For example, the first chip is the chip on the AUX (Auxiliary, auxiliary output or auxiliary output interface) card, and the second chip is the chip on the daughter card. The chip sends the completion packet, and the chip of the AUX card feeds back the completion packet to the sub-card after receiving the completion packet, and the chip of the AUX card and the chip of the sub-card enter the communication mode.

As an optional embodiment, the second group of phases to be measured is obtained based on the clock cycle of the signal sent by the first chip and the preset number of phases, or between two adjacent first phases to be measured in the first group of phases to be measured The difference is the clock period of the signal sent by the first chip divided by the preset number of phases.

As an optional embodiment, the number of the first chips is multiple, the multiple first chips are deployed on multiple different first boards, the second chips are deployed on the second boards, and the second boards Communicate with each of the plurality of first boards.

In the LVDS communication link, there is usually one AUX card and multiple daughter cards. In an optional embodiment, the above-mentioned multiple first boards are all daughter cards, and the second board is an AUX card. The daughter card dominates the taming process of the entire communication link. Card) to tame, based on the downlink tame result, and then tame the uplink (daughter card to AUX), and enter the normal communication process after the tame is completed.

As an optional embodiment, the first chip and the second chip are both FPGA chips, and the receiving phase is respectively locked to each of the first to-be-measured phases in the first group of phases to be measured by the clock manager in the first chip. phase.

As an optional embodiment, after the first chip locks the transmission phase to the second target phase, the above method further includes: the first chip communicates with the second chip, and the first chip communicates with the second chip include:

Step S109, the first chip encapsulates the data to be transmitted according to a preset rule to obtain an encapsulated data packet.

The following table 1 is an optional format of encapsulating data packets. After the first chip receives a complete packet of data to be transmitted, it encapsulates the data to be transmitted according to the rules of Table 1, including preamble, Length, TYPE, Reserve in turn. , HEAD_CHK, Payload and CRC8.

Table 1

The preamble is 8 bytes (ie 55555555555555D5), Length is 2 bytes, Payload is the field length of the data to be transmitted, TYPE is 1 byte, Reserve is 2 bytes, HEAD_CHK is 1 byte, and HEAD_CHK is the check digit of the Length, TYPE, Reserve fields, and CRC is the check digit of the packet header and end.

Step S110, the first chip encodes the encapsulated data packet to obtain an encoding result.

After the data to be transmitted is repackaged, it is encoded by the encoding module. Optionally, the encoding module is an 8B10B encoding module, and K28.1 is selected as the idle time encoding, K28.5 is used as the start of the encapsulated data packet, and K28.7 is used as the end of the encapsulated data packet to obtain the encoding result.

Step S111, the first chip scrambles the encoding result to obtain a scrambled result;

Optionally, the coding result can be scrambled by a 10-bit parallel scrambling module, and the data to be transmitted is coded and scrambled close to white noise, which ensures the DC balance in the data communication process.

Step S112, the first chip performs parallel-serial conversion on the scrambling result, and sends the data packet obtained after the parallel-serial conversion to the second chip;

Optionally, the scrambled result that has been scrambled enters the dual-clock fifo, crosses the 250M clock domain, enters the PISO module and completes the parallel-serial conversion and sends it to the second chip.

The second chip receives the data packet sent by the first chip, performs serial-to-parallel conversion on the received data packet, descrambles the serial-to-parallel conversion result, decodes the descramble result, and obtains the encapsulation result of the data to be transmitted, The verification is performed according to the encapsulation result, and if the verification is correct, the data to be transmitted is sent to the corresponding processing unit.

As an optional embodiment, the serial-to-parallel conversion can be completed by the SIPO module, and the data packets obtained after the serial-to-parallel conversion are written into the dual-clock FIFO to complete the conversion of the 250M to 25M clock domain. After the conversion is completed, the Descrambler module performs the conversion. In the descrambling operation, the descrambling completed data enters the 8B10B decoding module to complete the 8B10B decoding, and completes the byte alignment operation.

After decoding the data, according to the K code, packet header format, correctly parse the preamble, after length and type information, perform check_sum bit verification, if the verification is wrong, discard the data packet, and re-detect the preamble; if the verification is correct , then according to the length information, collect the data packet of this length, and perform CRC 8-bit check on the data. If the CRC 8-bit check is correct, output the transmission data to the corresponding processing unit for subsequent processing; if the CRC 8-bit check is incorrect, discard it. The data packet returns to the above step of detecting the preamble.

Through the above steps, the normal communication of data under the LVDS communication link is realized. Through the scrambling and encoding process of the data to be transmitted, the data signal to be transmitted is made close to white noise, which ensures the DC balance of the LVDS communication link and can be more effective. to improve the reliability and stability of data transmission.

As an optional embodiment, the data transmission steps of the above steps S109-S112 are implemented by the LVDS sending module (ie the lvds_send module) and the LVDS receiving module (ie the lvds_rec module), which respectively implement the sending and receiving of the data to be transmitted. Figure 5 is a schematic diagram of an optional LVDS communication module. The LVDS sending module and LVDS receiving module between chips of different boards can be interconnected with external logic by using an 8-bit serial interface. ) completes data exchange with the LVDS interface.

Figure 6 is a schematic diagram of an optional data processing, including the data transmission path in the LVDS communication link, Table 2 is the description of the external interface of the LVDS sending module, and Table 3 is the description of the external interface of the LVDS receiving module:

Table 2

PORT NAME端口名称PORT NAME port name	WIDTH宽度WIDTH width	Direction指向Direction points to	Description描述DescriptionDescription
sys_rstsys_rst	11	inputinput	本地复位信号local reset signal
sys_clksys_clk	11	inputinput	系统工作时钟System working clock
send_datasend_data	88	inputinput	发送数据send data
send_data_ensend_data_en	11	inputinput	发送数据有效信号Send data valid signal
send_data_lengthsend_data_length	1616	inputinput	当前发送数据包长度Current sent packet length
send_data_pkg_validsend_data_pkg_valid	11	inputinput	发送数据包完成信号Send packet completion signal
send_data_typesend_data_type	88	inputinput	数据包类型packet type
fifo_readyfifo_ready	11	outputoutput	表示是否能接收新的数据包Indicates whether new packets can be received
lvds_out_clklvds_out_clk	11	inputinput	发送侧MMCM输出时钟250MSending side MMCM output clock 250M
lvds_data_outlvds_data_out	11	outputoutput	lvds接口发送数据lvds interface to send data
lvds_25M_clklvds_25M_clk	11	inputinput	发送侧MMCM同步时钟25MSending side MMCM synchronous clock 25M

table 3

PORT NAME端口名称PORT NAME port name	WIDTH宽度WIDTH width	Direction指向Direction points to	Description描述DescriptionDescription
sys_rstsys_rst	11	inputinput	本地复位信号local reset signal
sys_clksys_clk	11	inputinput	系统工作时钟System working clock
rec_datarec_data	88	outputoutput	接收数据Receive data
rec_data_enrec_data_en	11	outputoutput	接收数据有效信号Receive data valid signal
rec_data_lengthrec_data_length	1616	outputoutput	接收数据包长度Received packet length
rec_data_pkg_validrec_data_pkg_valid	11	inputinput	接收数据包完成信号Receive packet completion signal
rec_data_typerec_data_type	88	inputinput	数据包类型packet type
lvds_in_clklvds_in_clk	11	inputinput	接收侧MMCM输出时钟250MReceive side MMCM output clock 250M
lvds_data_inlvds_data_in	11	inputinput	lvds接口接收数据lvds interface to receive data
lvds_25M_clklvds_25M_clk	11	inputinput	接收侧MMCM同步时钟25MReceive side MMCM synchronization clock 25M

In the data transmission path shown in Figure 6, the lvds_send module receives the data to be transmitted and stores it in the fifo module, and feeds back the signal to the preceding logic through the fifo_ready terminal to indicate whether new data can be received at present. After receiving one complete data packet, the state machine is started, the data is read out from the fifo, and the data is encapsulated according to step S109 to obtain an encapsulated data packet. The encapsulated data packet is sent to the 8B10B encoding module for encoding, and the 10bit parallel scrambling module (scrambler_10) for scramble. After scrambled, the data enters the dual-clock fifo, crosses the 250M clock domain, and enters the PISO module to complete the parallel-to-serial conversion. Sent to the external interface of the lvds_rec module.

After the lvds_rec module receives the data, it enters the SIPO module to complete the serial-to-parallel conversion, and writes the dual clock FIFO to complete the conversion of the 250M to 25M clock domain. After the conversion is completed, it enters the Descrambler module for descrambling operation, and the descrambling completed data enters the 8B10B decoding module to complete 8B10B decoding, and complete the byte alignment operation. After decoding the data, CRC 8-bit verification is performed on the data to be transmitted according to the internal process of step S112, and the rec_data_pkg_valid signal is output according to the correct verification result and fed back to the external logic for subsequent processing.

As an optional embodiment, the first board is a daughter card, the second board is an AUX card, the first chip is a chip on the daughter card, and the second chip is an AUX card chip. After the daughter card is powered on, the MMCM locks the receiving phase of the daughter card. In the current phase, the AUX card sends a test packet to the daughter card. The daughter card receives the test packet and determines the receiving state, and then enters the next clock sequence, repeating the above AUX The card sends the test package to the daughter card, and the daughter card receives and determines the steps of receiving status. After continuously recording the receiving states of N receiving phases, select an optimal phase among the receiving phases with the correct receiving state, and adjust the receiving phase of the daughter card to the optimal phase, so that the receiving phases of the AUX card and the daughter card are consistent. performance adjustment to complete the downlink tame between the AUX card and the daughter card (ie, the phase adjustment of the data downlink).

FIG. 3 provides a flowchart of an optional data processing method between the daughter card and the AUX card (ie, between the chip of the daughter card and the chip of the AUX card). As shown in Figure 3, the method includes the following steps:

Step S301, the main control card sends whether the sub-card is online; after the system is powered on, the main control card cyclically detects whether the sub-card is powered on, once it is detected that the sub-card is powered on, the main control card sends a taming instruction to the AUX card (taming is understandable In order to adjust the phase of the MMCM transceiver bidirectional clock), make the AUX card enter the tamed state, and enter step S302;

Step S302, the AUX card sends the downlink taming sequence, so that the daughter card enters the taming state, and then goes to step S303;

Step S303, the AUX card detects whether it receives the uplink taming sequence (that is, the test packet) or the completion sequence sent by the subcard; In the step of port phase adjustment, the AUX card receives the uplink taming sequence sent by the daughter card, and judges the receiving state of the current test packet. If the receiving state is correct, then enter step S304; if the receiving state is error or timeout, then Returning to step S302, the downlink taming sequence is periodically sent to the daughter card until the daughter card enters the taming state; the above-mentioned completion sequence is understood as the above-mentioned second target phase;

Step S304, loop back the current test packet data to the daughter card, and determine whether the test packet with the correct receiving state is a complete packet (that is, a test packet with a completed sequence), if the current test packet is a complete packet, then enter step S305; If the test package is not a complete package, then return to step S303, and the AUX card continues to receive the uplink taming sequence sent by the sub-card until the completion sequence is selected;

Step S305, the taming is completed, the AUX card exits the taming state, and enters the normal data receiving state, and feeds back the taming completion state to the main control card at the same time.

Through the above steps S301-S305, the transmission phase of the sub-card is adjusted to the optimum phase, so as to realize the consistency adjustment of the reception phase between the AUX card and the sub-card, and complete the uplink taming between the AUX card and the sub-card (that is, the data uplink). phase adjustment).

As an optional example, the link for receiving data and the link for sending data in two chips may be independent links, so for the first chip, it can perform downlink taming and uplink at the same time The tameness of the road.

Example 2

According to an embodiment of the present invention, an embodiment of a data processing method is provided. FIG. 2a is a flowchart of a data processing method according to an embodiment of the present invention. As shown in FIG. 2a, the above data processing method includes:

Step S209, when the second chip on the second board detects the idle code sent by the first chip on the first board, it continues to send a test packet to the first chip.

Step S210, until the second chip detects the completion packet sent by the first chip, the second chip stops sending the test packet.

It should be noted that the above-mentioned idle code is a trigger mechanism for the second chip on the second board to send the test packet to the first chip on the first board, and the above-mentioned completion packet is the stop of sending the second chip on the second board. Triggering mechanism for the test package. After the first board is powered on, the first chip starts to send the idle code, and the second chip of the second board is used as the sender for detection. When the idle code is detected, the test packet starts to be sent. The chip actively sends an idle code when detecting that the board is inserted into the backplane. When the second chip detects the completion packet sent by the first chip, it feeds back the completion packet to the first chip. At this time, the first chip has completed its uplink and downlink tame, and the second chip and the first chip enter the communication mode.

As an optional embodiment, the second chip communicates with a plurality of first chips through low-voltage differential signals. As shown in FIG. 2b, the above method further includes the following steps:

Step S201 , the receiving port of the second chip collects the test packet sent by the first chip, wherein the first chip locks the transmission phase to each second phase to be measured in the second group of phases to be measured, and the transmission phase is After locking to a second phase to be tested, send a test packet to the second chip;

Step S202, the second chip determines whether the test package is correct;

The data in the test packet received by the second chip is the same as the data in the test packet sent by the first chip, then the second chip judges that the test packet is correct, if the data in the test packet received by the second chip is the same as the data in the test packet sent by the first chip If the data in the sent test packet is different or the second chip does not receive the test packet, the second chip determines that the test packet is an error. Optionally, if the judgment result is correct, it is represented by 1; if the judgment result is wrong, it is represented by 0.

Step S203, the second chip returns the receiving state of the test packet to the first chip according to the judgment result;

When the judgment result is correct, the second chip sends a receiving correct status to the first chip, and when the judgment result is incorrect, the second chip sends a receiving error status to the first chip. Optionally, when the judgment result is correct, the second chip sends 1 to the first chip, and when the judgment result is wrong, the second chip sends 0 to the first chip.

Step S204, the first chip receives the receiving state of the test packet, determines the transmission state corresponding to each second phase to be measured according to the receiving state of the test packet, and determines the corresponding transmission state according to the transmission state corresponding to each second phase to be measured. Second target phase.

Through the above steps, the second chip directly feeds back the receiving state to the first chip, so that the first chip determines the corresponding sending state of each second phase to be measured according to the receiving state, and finds the second target phase. Therefore, a method for determining the optimal phase of the transmitting port of the first chip when the second chip communicates with the plurality of first chips in the LVDS communication link is provided.

As an optional embodiment, when the second chip judges that the test packet is correct, after the second chip returns the receiving state of the test packet to the first chip according to the judgment result, the above method further includes: the second chip judges the test Whether the package is a completion package, wherein after the first chip determines the second target phase of the sending port, it sends the completion package to the second chip; if the test package is a completion package, the second chip and the first chip enter the communication mode; if the test package does not In order to complete the packet, the step of entering the receiving port of the second chip to collect the test packet sent by the first chip.

The above-mentioned completion packet is a test packet including a completed data sequence, and the completed data sequence is a test packet corresponding to the second target phase. When the second chip receives the completion packet, it indicates that the sending port of the first chip has adjusted the clock phase according to the second target phase, so that the clock phase of the sending port of the first chip is the optimal phase, and the second chip and the A chip can enter normal communication mode.

As an optional embodiment, the first chip and the second chip are chips of different sub-cards. FIG. 4 provides a flowchart of an optional data processing method between the sub-card and the chips of the sub-card. As shown in Figure 4, the method includes the following steps:

Step S401, the sub-card is powered on reset or soft reset;

Step S402, adjust the phase of the clock on the receiving side of the MMCM, and the MMCM completes the phase locking;

Step S403, the daughter card receives the downlink taming sequence, and records the current phase receiving state; if the taming code is received correctly or the taming code is not received over time, the receiving state of the current phase (correctly received or incorrectly received) is recorded;

Step S404, the loop counter is incremented by 1, and it is judged whether the loop counter is greater than or equal to 32; in the current downlink taming process, there are 32 phases to be tested, and the 32 phases to be tested need to be recorded one by one for the receiving state of the test packet; If it reaches 32, then go back to step S402, lock the phase to be measured, and execute the steps of judging and recording the phase receiving state in step S403; if the counter reaches 32, then enter step S405;

If the taming code is not received over time, adjust the phase of the lvds_in_clk output by the MMCM, reset the timeout counter after the clock is locked, and go to step S403 to restart receiving the taming code.

Step S405, according to the recorded receiving states of the 32 phases, determine whether there is an optimal phase on the input side, if so, go to step S406; but if there is no optimal phase, go to step S417 to feed back the daughter card MCU (controller), and the output is wrong ;

Step S406, the optimal phase is fed back to the daughter card MCU, and the input side clock (ie lvds_in_clk) is adjusted to the optimal phase;

Step S407, the downlink taming of the sub-card is completed, and the current state is fed back to the sub-card MCU;

Step S408, start the uplink taming process of the daughter card, and adjust the clock phase on the sending side of the MMCM;

Step S409, the daughter card sends the uplink taming sequence;

Step S410, the daughter card receives the uplink taming sequence, and records the current phase receiving state;

Step S411, the loop counter is incremented by 1, and it is judged whether the loop counter is greater than or equal to 32; in the current uplink taming process, there are 32 phases to be tested, and the 32 phases to be tested need to be recorded one by one test packet transmission state; When the count reaches 32, go to step S412;

Step S412, according to the recorded transmission states of the 32 phases, comprehensively judge whether there is an optimal phase on the output side;

In step S413, the optimal phase in step S412 is fed back to the sub-card MCU, and the clock on the output side is adjusted to the optimal phase;

Step S414, the uplink taming of the sub-card is completed, and the current state is fed back to the sub-card MCU;

Step S415, the sub-card sends the taming completion sequence to the AUX card, and waits for a confirmation;

Step S416, the taming is completed, and the normal communication mode is entered.

Through the above steps, the two-way clock phase adjustment of data reception and data transmission between chips between multiple sub-cards is realized.

It should be noted that in the LVDS communication link, there is usually an AUX card and multiple sub-cards. The sub-card dominates the taming process of the entire communication link. First, the downlink (AUX to the sub-card) is tamed. Based on the downlink After taming the result, the uplink (daughter card to AUX) is tamed, and the normal communication process is entered after the taming is completed.

Example 3

According to an embodiment of the present invention, an embodiment of a data processing apparatus is provided. FIG. 7 is a schematic diagram of a data processing apparatus according to an embodiment of the present invention. As shown in FIG. For low-voltage differential signal communication, the above-mentioned data processing device includes: a phase locking module 71 for locking the receiving phase to each first phase to be measured in the first group of phases to be measured after the first chip is powered on; the phase The test module 72 is configured to enable the first chip to receive the test packet sent by the second chip after the receiving phase is locked to a first phase to be measured each time, and to determine the receiving state, and to obtain the reception corresponding to each first phase to be measured. The phase selection module 73 is used for the first chip to determine the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured; the phase adjustment module 74 is used to make the first chip lock the receiving phase to A first target phase for the receive port of the first chip to communicate with the second chip at the first target phase.

The above-mentioned apparatus further includes modules for executing other method steps in Embodiment 1, which will not be repeated here.

In this embodiment, by determining the data transmission state of the second chip and the receiving state of the data of the first chip under the corresponding phase, the optimal phase is selected, and the receiving phase of the clock of the first chip is adjusted accordingly based on the optimal phase, so as to avoid The phase offset between the chips in the LVDS communication link is improved, the stability of the data transmission of the LVDS communication link and the efficiency of the data transmission are improved, and the data transmission when the LVDS communication link is used for communication between the chips in the prior art is solved. Unstable technical issues.

Example 4

According to an embodiment of the present invention, an embodiment of a data processing apparatus is provided. FIG. 8 is a schematic diagram of another data processing apparatus according to an embodiment of the present invention. As shown in FIG. 8 , the apparatus includes:

The sending module 80 is used for continuously sending a test packet to the first chip when the second chip on the second board detects the idle code sent by the first chip on the first board;

The stop sending module 82 is configured to stop sending the test packet by the second chip until the second chip detects the completion packet sent by the first chip.

The above-mentioned apparatus further includes modules for executing other method steps in Embodiment 2, and details are not described herein again.

Example 5

According to an embodiment of the present invention, an embodiment of a data processing system for a board card is provided. FIG. 9 is a schematic diagram of a data processing system for a board card according to an embodiment of the present invention. As shown in FIG. 9 , the data processing system includes a plurality of A first board and a second board, the first board and the second board are both arranged on the backplane, and each first board and the second board communicate through low-voltage differential signals, and the second board The board is used to send the test package to the first board; the first board is used to lock the receiving phase to each first phase to be tested in the first group of phases to be tested after power-on, and receive the second board The first board card is also used to determine the first corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured. The target phase is used for the receiving port of the first board to communicate with the second board under the first target phase; the first board is also used to lock the transmit phase to each of the second sets of phases to be tested. Two phases to be tested, and after the sending phase is locked to a second phase to be tested each time, a test package is sent to the second board; the second board is also used to judge whether the test package is correct, and send the test package to the first board according to the judgment result. The board returns the receiving state of the test package; the first board is also used to receive the receiving state of the test package, determine the sending state corresponding to each second phase to be tested according to the receiving state of the test package, and according to the receiving state of each second test package The transmission state corresponding to the phase determines the second target phase corresponding to the transmission phase.

Specifically, after the sub-card is powered on, the MMCM locks the receiving phase of the sub-card. Under the current phase, the AUX card sends a test packet to the sub-card, and the sub-card receives the test packet and determines the receiving state, and then enters the next clock sequence. Repeat the above steps that the AUX card sends the test package to the daughter card, and the daughter card receives and determines the receiving status. After continuously recording the receiving states of N receiving phases, select an optimal phase among the receiving phases with the correct receiving state, and adjust the receiving phase of the daughter card to the optimal phase, so that the receiving phases of the AUX card and the daughter card are consistent. performance adjustment to complete the downlink tame between the AUX card and the daughter card (ie, the phase adjustment of the data downlink).

After completing the downlink taming, the main control card cyclically detects whether the daughter card is powered on. Once it detects that the daughter card is powered on, the main control card sends a taming command to the AUX card (taming can be understood as sending and receiving the phase of the two-way clock through the MMCM make adjustments), make the AUX card enter the taming state, the AUX card sends the downlink taming sequence to make the daughter card enter the taming state, and the AUX card detects whether it receives the uplink taming sequence (ie test packet) sent by the daughter card or completes the sequence ; If the AUX card receives the uplink taming sequence sent by the daughter card, it means that it has entered the step of adjusting the phase of the sending port of the daughter card. The status is judged. If the receiving status is correct, loop back the current test package data to the daughter card. If the current test package is a complete package and the taming is completed, the AUX card exits the taming status and enters the normal data receiving status. At the same time, the taming completion status is fed back. to the main control card. According to the above steps, the transmission phase of the sub-card is adjusted to the optimal phase, so as to realize the consistency adjustment of the receiving phase between the AUX card and the sub-card, and complete the uplink taming between the AUX card and the sub-card (that is, the phase adjustment of the data uplink). ).

It should be noted that when the second board communicates with multiple first boards, if the second board tames its own downlink, the operation of the second board will be very complicated. Therefore, the operation of the second board will be very complicated. In this case, the taming of the uplink is performed by the first board.

In this embodiment, the second board serves as both the sending end and the receiving end, sending test packets to multiple first boards and receiving test packets sent by multiple first boards, so that each of the multiple first boards Each board determines the optimal phase of its receive phase and transmit phase. By adjusting the phase of the MMCM sending and receiving two-way (including data uplink and data downlink) clocks, the two-way adjustment of the clocks of the sending port and the receiving port of the first board is completed, which solves the problem of LVDS-based communication links. There is the problem of phase deviation in the communication between the boards, which solves the problem of unstable data transmission when the LVDS communication link is used for communication between the boards, ensures that the data on the LVDS line can be sampled normally, and establishes a stable relationship between the boards. Reliable LVDS communication link improves data transmission efficiency.

Example 6

According to an embodiment of the present invention, an embodiment of a data processing system for a board card is provided. FIG. 10 is a schematic diagram of a data processing system for a board card according to an embodiment of the present invention. As shown in FIG. 10 , the data processing system includes a first A board and a second board, the first board and the second board are both arranged on the backplane, the first board and the second board communicate through low-voltage differential signals, and the second board uses It is used to send the test package to the first board; the first board is used to lock the receiving phase to each first phase to be measured in the first group of phases to be measured after power-on, and receive the test packets, and determine the receiving state, and obtain the receiving state corresponding to each first phase to be tested; the first board is also used to determine the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured, The receiving port for the first board is used to communicate with the second board in the first target phase; the first board is also used to send a test package to the second board; the second board is also used to power on After that, lock the receiving phase to each third phase to be measured in the third group of phases to be measured, receive the test packet sent by the first board, determine the receiving state, and obtain the corresponding receiving phase of each third phase to be measured. state; the second board is also used to determine the third target phase corresponding to the receiving phase according to the receiving state corresponding to each third phase to be measured, so that the receiving port of the second board is in the third target phase and the first board to communicate.

It should be noted that, when two boards A and B that communicate through LVDS are in one-to-one correspondence, the above-mentioned first board may be any one of board A and board B. In an optional embodiment, first board A is used as the above-mentioned first board, and board B is used as the above-mentioned second board to complete the taming of the downlink of board A; then board B is used as the above-mentioned second board. In the above-mentioned first board, the board A is used as the above-mentioned second board, so as to complete the taming of the downlink of the board B. Through the above two times of taming, the transceiver between the board A and the board B can be in a stable state.

Specifically, in an optional implementation, the first board is a sub-card A, the second board is a sub-card B, and the sub-card A and the sub-card B are in one-to-one correspondence. After the subcard A is powered on, the MMCM locks the receiving phase of the subcard A. Under the current phase, the subcard B sends a test packet to the subcard A, and the subcard A receives the test packet and determines the receiving state, and then enters the next clock sequence, repeating the above steps of subcard B sending a test packet to subcard A, and subcard A receiving and determining the receiving state. After continuously recording the receiving states of N receiving phases, among the receiving phases with the correct receiving state, an optimal phase is selected, and the receiving phase of sub-card A is adjusted to the optimal phase, so as to realize the communication between sub-card B and sub-card A. Receive phase consistency adjustment to complete downlink taming of daughter card A (ie, data downlink phase adjustment).

After the downlink taming of the subcard A is completed, the MMCM locks the receiving phase of the subcard B. Under the current phase, the subcard A sends a test packet to the subcard B, and the subcard B receives the test packet and determines the receiving state. , and then enter the next clock sequence, and repeat the above steps of subcard A sending a test packet to subcard B, and subcard B receiving and determining the receiving state. After continuously recording the receiving states of N receiving phases, among the receiving phases with the correct receiving state, an optimal phase is selected, and the receiving phase of sub-card B is adjusted to the optimal phase, so as to realize the communication between sub-card B and sub-card A. Receive phase consistency adjustment to complete downlink taming of daughter card B (that is, phase adjustment of data downlink). Through the above two times of taming, the sending and receiving between board A and board B can be in a stable state.

In this embodiment, by determining the data transmission state of the second board and the receiving state of the first board data under the corresponding phase, the optimal phase is screened out, and based on the optimal phase, the receiving phase of the clock of the first board is calculated accordingly. Adjust, correspondingly, determine the optimal phase of the receiving phase of the clock of the second board and adjust accordingly, avoid the phase offset between different boards in the LVDS communication link, and improve the data of the LVDS communication link The stability of transmission and the efficiency of data transmission further solve the technical problem of unstable data transmission in the prior art when LVDS communication links are used to communicate between different boards in one-to-one correspondence.

Example 7

According to an embodiment of the present invention, an embodiment of a storage medium is provided, wherein the storage medium includes a stored program, wherein when the program runs, a device where the storage medium is located is controlled to execute the data processing method.

According to an embodiment of the present invention, an embodiment of a processor is provided, and the processor is used for running a program, wherein the data processing method is executed when the program is running.

The above-mentioned serial numbers of the embodiments of the present invention are only for description, and do not represent the advantages or disadvantages of the embodiments.

In the above-mentioned embodiments of the present invention, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units may be a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or may be Integration into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of units or modules, and may be in electrical or other forms.

The units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.

The integrated unit, if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes .

The above are only the preferred embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims

A data processing method, characterized in that a first chip and a second chip communicate through a low-voltage differential signal, and the data processing method includes:

After the first chip is powered on, the receiving phase is locked to each first phase to be measured in the first group of phases to be measured;

After the receiving phase is locked to one of the first phases to be measured each time, the first chip receives the test packet sent by the second chip, determines the receiving state, and obtains the corresponding value of each first phase to be measured. receiving state;

The first chip determines the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured;

The first chip locks the receive phase to the first target phase for a receive port of the first chip to communicate with the second chip at the first target phase.
The data processing method according to claim 1, wherein the first group of phases to be measured is obtained based on a clock cycle of the signal received by the first chip and a preset number of phases; or, the first group of phases to be measured The difference between two adjacent first phases to be measured in the phase is the clock period divided by the preset number of phases.
The data processing method according to claim 1, wherein after the receiving phase is locked to the first phase to be tested each time, the first chip receives the test packet sent by the second chip, and Determine the receiving state, and obtain the receiving state corresponding to each first phase to be measured, including:

The first chip receives a plurality of consecutive test packets sent by the second chip;

If the first chip receives all the consecutive multiple test packets correctly, it is determined that the receiving state of the first chip in the current first phase to be tested is a correct receiving state;

If the first chip receives any one or more test packets incorrectly or fails to receive it over time, it is determined that the receiving state of the first chip in the current first phase to be tested is a receiving error state.
The data processing method according to claim 3, wherein determining the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured comprises:

It is determined that the first phase to be measured whose receiving state is the correct receiving state is the first target phase corresponding to the receiving phase.
The data processing method according to claim 4, wherein when the first phase to be measured whose receiving state is the correct receiving state is a plurality of consecutive phases, it is determined that the first waiting state whose receiving state is the correct receiving state is the first phase to be measured. The measured phase is the first target phase corresponding to the received phase, including:

The middle phase among the plurality of continuous phases is determined as the first target phase corresponding to the receiving phase.
The data processing method according to claim 1, wherein the method further comprises:

the first chip locks the transmission phase to each second phase to be measured in the second group of phases to be measured;

After the sending phase is locked to one of the second phases to be tested each time, a test packet is sent to the second chip, wherein after the first chip sends the test packet to the second chip, the second chip returns the receiving state of the test packet to the first chip;

The first chip receives the reception status of the test packet, and determines the transmission status corresponding to each of the second phases to be tested according to the reception status of the test packet;

Determine the second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured;

The first chip locks the transmit phase to the second target phase, wherein the transmit port of the first chip communicates with the second chip at the second target phase.
The data processing method according to claim 6, wherein the first chip receives the reception status of the test packet, and determines the transmission corresponding to each second phase to be tested according to the reception status of the test packet status, including:

If the reception status of the test packet is that all receptions are correct, determine that the transmission status corresponding to the second phase to be tested is the correct transmission status;

If the reception status of any one or more test packets is a reception error or a timeout is not received, it is determined that the transmission status corresponding to the second phase to be tested is a transmission error status.
The data processing method according to claim 6, wherein determining the second target phase corresponding to the transmission phase according to the transmission state corresponding to each second phase to be measured, comprising:

It is determined that the second phase to be measured whose transmission state is the correct transmission state is the second target phase corresponding to the transmission phase.
The data processing method according to claim 8, wherein when the second phase to be measured whose transmission state is the correct transmission state is a plurality of consecutive phases, it is determined that the second phase to be measured whose transmission state is the correct transmission state is the second phase to be measured. is the second target phase corresponding to the transmission phase, including:

The middle phase among the plurality of continuous phases is determined as the first target phase corresponding to the transmission phase.
The data processing method according to claim 7, wherein after the first chip locks the transmission phase to the second target phase, the method further comprises:

the first chip sends a completion packet to the second chip;

Wherein, after receiving the test packet, the second chip determines whether the test packet is a completion packet, and if the test packet is the completion packet, the second chip and the first chip enter into communication mode; if the test packet is not the completion packet, enter the step of returning the receiving state of the test packet to the first chip by the second chip.
The data processing method according to claim 7, wherein the second group of phases to be measured is obtained based on a clock cycle of a signal sent by the first chip and a preset number of phases, or

The difference between two adjacent first phases to be measured in the first group of phases to be measured is the clock cycle of the signal sent by the first chip divided by the preset number of phases.
The data processing method according to claim 1, wherein the number of the first chips is multiple, and a plurality of the first chips are deployed on a plurality of different first boards, and the second chips Deployed on a second board, the second board communicates with each of the plurality of first boards.
The data processing method according to claim 1, wherein the first chip and the second chip are both FPGA chips, and the receiving phase is respectively locked to the said first chip by a clock manager in the first chip. Each first phase to be measured in the first group of phases to be measured.
The data processing method according to claim 8, wherein after the first chip locks the transmission phase to the second target phase, the method further comprises: the first chip and the The second chip communicates, and the step of communicating between the first chip and the second chip includes:

The first chip encapsulates the data to be transmitted according to a preset rule to obtain an encapsulated data packet;

The first chip encodes the encapsulated data packet to obtain an encoding result;

The first chip scrambles the encoding result to obtain a scrambled result;

The first chip performs parallel-serial conversion on the scrambled result, and sends the data packet obtained after the parallel-serial conversion to the second chip;

The second chip receives the data packet sent by the first chip, performs serial-to-parallel conversion on the received data packet, descrambles the serial-to-parallel conversion result, decodes the descramble result, and obtains the The encapsulation result of the transmitted data is verified according to the encapsulation result, and if the verification is correct, the data to be transmitted is sent to the corresponding processing unit.
A data processing method, characterized in that the method comprises:

When the second chip on the second board detects the idle code sent by the first chip on the first board, it continues to send a test packet to the first chip;

Until the second chip detects the completion packet sent by the first chip, the second chip stops sending the test packet.
The data processing method according to claim 15, wherein the second chip communicates with a plurality of first chips through a low-voltage differential signal, and the data processing method comprises:

The receiving port of the second chip collects the test packet sent by the first chip, wherein the first chip locks the sending phase to each second phase to be measured in the second group of After the transmission phase is locked to a second phase to be tested each time, a test packet is sent to the second chip;

The second chip determines whether the test package is correct;

The second chip returns the receiving state of the test packet to the first chip according to the judgment result;

The first chip receives the reception state of the test packet, determines the transmission state corresponding to each of the second phases to be measured according to the reception state of the test packet, and determines the transmission state corresponding to each second phase to be measured according to the reception state of the test packet A second target phase corresponding to the transmission phase is determined.
The data processing method according to claim 16, wherein when the second chip judges that the test package is correct, the second chip returns the test to the first chip according to the judgment result After the receiving state of the packet, the method further includes:

The second chip determines whether the test packet is a completion packet, wherein the first chip sends the completion packet to the second chip after determining the second target phase of the sending port;

If the test package is the completion package, the second chip and the first chip enter a communication mode;

If the test packet is not the completion packet, enter the receiving port of the second chip to collect the test packet sent by the first chip.
A data processing device, characterized in that a first chip and a second chip communicate through a low-voltage differential signal, and the data processing device comprises:

a phase locking module, configured to lock the receiving phase to each first phase to be measured in the first group of phases to be measured after the first chip is powered on;

The phase test module is configured to enable the first chip to receive the test packet sent by the second chip after the receiving phase is locked to one of the first phases to be tested each time, and determine the receiving state, and obtain each the receiving state corresponding to the first phase to be measured;

a phase selection module, used for the first chip to determine the first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured;

A phase adjustment module, configured to enable the first chip to lock the receiving phase to the first target phase, so that the receiving port of the first chip can communicate with the second chip under the first target phase chip to communicate.
A data processing device, comprising:

a sending module, used for continuously sending a test packet to the first chip when the second chip on the second board detects the idle code sent by the first chip on the first board;

A stop sending module, configured to stop sending the test packet by the second chip until the second chip detects the completion packet sent by the first chip.
A data processing system for boards, characterized in that it includes a plurality of first boards and a second board, the first board and the second board are both arranged on the backplane, each The first board and the second board communicate through low-voltage differential signals,

the second board is used for sending a test package to the first board;

The first board is used to lock the receiving phase to each first phase to be tested in the first group of phases to be tested after power-on, receive the test package sent by the second board, and determine the receiving phase. state, to obtain the receiving state corresponding to each first phase to be measured;

The first board is further configured to determine a first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured, so that the receiving port of the first board is in the first phase. communicate with the second board in the target phase;

The first board is also used to lock the transmission phase to each second phase to be measured in the second group of phases to be measured, and after the transmission phase is locked to one of the second phases to be measured each time, sending a test package to the second board;

The second board is also used for judging whether the test package is correct, and returns the receiving state of the test package to the first board according to the judgment result;

The first board is also used to receive the reception status of the test packet, determine the transmission status corresponding to each second phase to be measured according to the reception status of the test packet, and determine the corresponding transmission status of each second phase to be measured according to the reception status of the test packet, and The corresponding transmission state determines the second target phase corresponding to the transmission phase.
A data processing system for board cards, characterized in that it includes a first board card and a second board card, the first board card and the second board card are both arranged on a backplane, and the first board card and the second board card are both arranged on a backplane. A low-voltage differential signal communicates between a board and the second board,

the second board is used for sending a test package to the first board;

The first board is used to lock the receiving phase to each first phase to be tested in the first group of phases to be tested after power-on, receive the test package sent by the second board, and determine the receiving phase. state, to obtain the receiving state corresponding to each first phase to be measured;

The first board is further configured to determine a first target phase corresponding to the receiving phase according to the receiving state corresponding to each first phase to be measured, so that the receiving port of the first board is in the first phase. communicating with the second board in the target phase;

The first board is also used for sending a test package to the second board;

The second board is also used to lock the receiving phase to each third phase to be tested in the third group of phases to be tested after power-on, receive the test package sent by the first board, and determine receiving state, to obtain the receiving state corresponding to each third phase to be measured;

The second board is further configured to determine a third target phase corresponding to the receiving phase according to the receiving state corresponding to each third phase to be measured, so that the receiving port of the second board is in the third phase. communicate with the first board in the target phase.
A storage medium, characterized in that the storage medium includes a stored program, wherein when the program runs, a device where the storage medium is located is controlled to execute the data processing method according to any one of claims 1 to 17.
A processor, characterized in that the processor is used for running a program, wherein when the program runs, the data processing method according to any one of claims 1 to 17 is executed.