CN103346781A

CN103346781A - Mechanical relay driving output protective circuit

Info

Publication number: CN103346781A
Application number: CN2013102378142A
Authority: CN
Inventors: 刘寅
Original assignee: WUJIANG SHENGBORUI INFORMATION TECHNOLOGY Co Ltd
Current assignee: WUJIANG SHENGBORUI INFORMATION TECHNOLOGY Co Ltd
Priority date: 2013-06-17
Filing date: 2013-06-17
Publication date: 2013-10-09

Abstract

The invention discloses a mechanical relay driving output protective circuit which comprises an oscillator, a signal A and a signal B, wherein the oscillator is connected with two frequency dividers which generate clock signals CLKF and CLKS to six triggers D, and a combinatorial logic circuit generates signals CA, CB, CC and CD. By means of the mechanical relay driving output protective circuit, a relay driver can regulate and drive clock behaviors according to input inductive reactance of a relay when driving the relay containing output inductive reactance, and better balance between power consumption and reliability can be obtained.

Description

A kind of mechanical relay drives output protection circuit

Technical field

The present invention relates to a kind of thermo-mechanical drive output protection mechanism, what be specifically related to is that a kind of mechanical relay drives output protection circuit.

Background technology

Relay drive produces the difference current output signal, drives relay, thereby realizes changing the purpose of relay state.But under actual conditions, because the imperfection of relay, input port contains emotional resistance, and the differential driving electric current that this emotional resistance produces relay drive can't turn-off at once, and this electric current brings very big integrity problem to relay drive.For fear of this phenomenon, common processing mode can connect big electric capacity in driver output and absorb this electric current, and this mode can cause output current producing concussion; When electric current was excessive, this mode is poor effect also; Equally also can influence the switching response speed of relay.

For this reason, need a kind of novel relay drive circuit, make in relay drive work, can accept the relay of bigger perception input.Can not produce the phenomenon of reliability or disabler because of the input impedance of relay perception.

Summary of the invention

The objective of the invention is to overcome the above problem that prior art exists; a kind of mechanical relay drive output protection circuit is provided; make switching sequence generation circuit and pierce circuit produce the driving signal of certain sequential; when switching signal is switched; the flow direction of control relay electric current, thus relay input induction reactance reduced to the full extent to the influence of driver.

For realizing above-mentioned technical purpose, reach above-mentioned technique effect, the present invention is achieved through the following technical solutions:

A kind of mechanical relay drives output protection circuit, comprise oscillator, signal A and signal B, described oscillator produces oscillator signal to the first frequency divider and second frequency divider, the CLK end of described first frequency divider clocking CLKF to the first d type flip flop and the CLK end of four d flip-flop, the CLK end of clock signal clk S to the 3d flip-flop that described second frequency divider produces and the CLK end of the 6th d type flip flop; Described signal A is sent to first NAND gate and second NAND gate through first non-goalkeeper's signal, another input of described first NAND gate connects the output of described second NAND gate, the output of described first NAND gate is sent to signal at the D end of described first d type flip flop, the Q end of described first d type flip flop is sent to the D end of second trigger and the input of described second NAND gate with signal, the QB end of described first d type flip flop sends signal NA to combinational logic circuit, the Q end of described second trigger connects the D end of the 3rd trigger, the CLK end of described second trigger connects the CLK end of the 5th d type flip flop, the QB end of described the 3rd trigger connects described second NAND gate, the CLK end of described the 3rd trigger connects the CLK end of the 6th d type flip flop, and the Q end of described the 3rd trigger sends signal AD to described combinational logic circuit; Described signal B is sent to the 3rd NAND gate and the 4th NAND gate through second non-goalkeeper's signal, described the 3rd NAND gate output connects the D end of described four d flip-flop, the QB end of described four d flip-flop sends signal NB to described combinational logic circuit, the Q end of described four d flip-flop connects the D end of described the 5th d type flip flop and the input of described the 4th NAND gate, the Q end of described the 5th d type flip flop sends signal BD to described combinational logic circuit, the QB end of described the 6th d type flip flop connects described the 4th NAND gate, and described combinational logic circuit sends signal CA, CB, CC, CD.

Further, described signal CA, CB, CC, CD connect field effect transistor PMOS1, NMOS1, PMOS2, NMOS2 respectively, the source electrode of described PMOS1 connects power vd D, drain electrode connects the OA end of relay, grid connects signal CA, the drain electrode of described NMOS1 connects the OA end of described relay, source ground, and grid connects signal CB; Described power vd D connects the source electrode of described PMOS2, the drain electrode of described PMOS2 connects the OB end of described relay, grid connects signal CC, the source ground of described NMOS2, grid connects signal CD, and drain electrode connects the OB end of relay, the positive pole of the source electrode connector diode D1 of described NMOS1, the negative pole of described body diode D1 connects the drain electrode of described NMOS1, the positive pole of the source electrode connector diode D2 of described NMOS2, and the negative pole of described body diode D2 connects the drain electrode of described NMOS2

The invention has the beneficial effects as follows:

The invention enables relay drive when driving contains the relay of perceptual output impedance; can protect relay drive, make its operate as normal, and can be according to the input induction reactance of relay; adjust and drive the clock behavior, it is compromised between power consumption and reliability preferably.

Description of drawings

Fig. 1 is that switching signal of the present invention produces circuit diagram;

The switching signal that Fig. 2 is required for Fig. 1 drives;

Fig. 3 is drive circuit figure.

Number in the figure explanation: 1, oscillator, 2, first frequency divider, 3, second frequency divider, 4, first d type flip flop, 5, second d type flip flop, 6,3d flip-flop, 7, four d flip-flop, the 8, the 5th d type flip flop, the 9, the 6th d type flip flop, 10, first not gate, 11, first NAND gate, 12, second NAND gate, 13, second not gate, 14, the 4th NAND gate, the 15, the 5th NAND gate, 16, combinational logic circuit.

Embodiment

Below with reference to the accompanying drawings and in conjunction with the embodiments, describe the present invention in detail.

With reference to shown in Figure 1, a kind of mechanical relay drives output protection circuit, comprise oscillator 1, signal A and signal B, described oscillator 1 produces oscillator signal to the first frequency divider 2 and second frequency divider 3, the CLK end of described first frequency divider, 2 clocking CLKF to the first d type flip flops 4 and the CLK end of four d flip-flop 7, the CLK end of clock signal clk S to the 3d flip-flop 6 that described second frequency divider 3 produces and the CLK end of the 6th d type flip flop 9; Described signal A is sent to first NAND gate 11 and second NAND gate 12 through first not gate 10 with signal, another input of described first NAND gate 11 connects the output of described second NAND gate 12, the output of described first NAND gate 11 is sent to signal at the D end of described first d type flip flop 4, the Q end of described first d type flip flop 4 is sent to the D end of second trigger 5 and the input of described second NAND gate 12 with signal, the QB end of described first d type flip flop 4 sends signal NA to combinational logic circuit 16, the Q end of described second trigger 5 connects the D end of the 3rd trigger 6, the CLK end of described second trigger 5 connects the CLK end of the 5th d type flip flop 8, the QB end of described the 3rd trigger 6 connects described second NAND gate 12, the CLK end of described the 3rd trigger 6 connects the CLK end of the 6th d type flip flop 9, and the Q end of described the 3rd trigger 6 sends signal AD to described combinational logic circuit 16; Described signal B is sent to the 3rd NAND gate 15 and the 4th NAND gate 14 through second not gate 13 with signal, described the 3rd NAND gate 15 outputs connect the D end of described four d flip-flop 7, the QB end of described four d flip-flop 7 sends signal NB to described combinational logic circuit 16, the Q end of described four d flip-flop 7 connects the D end of described the 5th d type flip flop 8 and the input of described the 4th NAND gate 14, the Q end of described the 5th d type flip flop 8 sends signal BD to described combinational logic circuit 16, the QB end of described the 6th d type flip flop 9 connects described the 4th NAND gate 14, and described combinational logic circuit 16 sends signal CA, CB, CC, CD.

With reference to shown in Figure 3, described signal CA, CB, CC, CD connect field effect transistor PMOS1, NMOS1, PMOS2, NMOS2 respectively, the source electrode of described PMOS1 connects power vd D, drain electrode connects the OA end of relay, grid connects signal CA, the drain electrode of described NMOS1 connects the OA end of described relay, source ground, and grid connects signal CB; Described power vd D connects the source electrode of described PMOS2, the drain electrode of described PMOS2 connects the OB end of described relay, grid connects signal CC, the source ground of described NMOS2, grid connects signal CD, and drain electrode connects the OB end of relay, the positive pole of the source electrode connector diode D1 of described NMOS1, the negative pole of described body diode D1 connects the drain electrode of described NMOS1, the positive pole of the source electrode connector diode D2 of described NMOS2, and the negative pole of described body diode D2 connects the drain electrode of described NMOS2

The operation principle of present embodiment is as follows:

With reference to shown in Figure 2, when CA is low level, CD is high level, and electric current flows to OB from OA, if CA is set to high level, PMPS1 turn-offs, and CD is set to low level, and NMOS2 turn-offs.Because the perceptual input impedance of relay, electric current from OA to OB can be kept, size is constant substantially, continue for some time. so just need to give path of electric current. this design is at PMOS1, when NMOS2 disconnects, it is as follows to change work schedule: making CA earlier is high level, PMOS1 turn-offs, and maintenance CD is high level, and NMOS2 opens, the non-coincidence then CB level that makes is height, NMOS1 opens, and allows NMOS1/NMOS2 open certain time interval T 1 simultaneously, and the reverse current path is provided. at this moment, electric current can flow into relay OA by the parasitic body diode D1 of NMOS1, by NMOS2 from the OB inflow place. in the time of design, by the counting to oscillator, come T1 is adjusted, from several millisecond to a few tens of milliseconds, then by testing to determine best T1.

In like manner, when CC is low level, CB is high level, and electric current flows to OA from OB, if CC is set to high level, PMPS2 turn-offs, and CC is set to low level, and NMOS2 turn-offs.Because the perceptual input impedance of relay, electric current from OB to OA can be kept, size is constant substantially, continue for some time. so just need to give path of electric current. this design is at PMOS2, when NMOS1 disconnects, it is as follows to change work schedule: making CC earlier is high level, PMOS2 turn-offs, and maintenance CB is high level, and NMOS1 opens, the non-coincidence then CD level that makes is height, NMOS2 opens, and allows NMOS1/NMOS2 open certain time interval T 1 simultaneously, and the reverse current path is provided. at this moment, electric current can flow into relay OB by the parasitic body diode D2 by NMOS2, by NMOS2 from the OA inflow place.

Claims

1. a mechanical relay drives output protection circuit, it is characterized in that: comprise oscillator (1), signal A and signal B, described oscillator (1) produces oscillator signal to the first frequency divider (2) and second frequency divider (3), the CLK end of described first frequency divider (2) clocking CLKF to the first d type flip flop (4) and the CLK end of four d flip-flop (7), the CLK end of clock signal clk S to the 3d flip-flop (6) that described second frequency divider (3) produces and the CLK end of the 6th d type flip flop (9); Described signal A is sent to first NAND gate (11) and second NAND gate (12) through first not gate (10) with signal, another input of described first NAND gate (11) connects the output of described second NAND gate (12), the output of described first NAND gate (11) is sent to signal at the D end of described first d type flip flop (4), the Q end of described first d type flip flop (4) is sent to the D end of second trigger (5) and the input of described second NAND gate (12) with signal, the QB end of described first d type flip flop (4) sends signal NA to combinational logic circuit (16), the Q end of described second trigger (5) connects the D end of the 3rd trigger (6), the CLK end of described second trigger (5) connects the CLK end of the 5th d type flip flop (8), the QB end of described the 3rd trigger (6) connects described second NAND gate (12), the CLK end of described the 3rd trigger (6) connects the CLK end of the 6th d type flip flop (9), and the Q end of described the 3rd trigger (6) sends signal AD to described combinational logic circuit (16); Described signal B is sent to the 3rd NAND gate (15) and the 4th NAND gate (14) through second not gate (13) with signal, described the 3rd NAND gate (15) output connects the D end of described four d flip-flop (7), the QB end of described four d flip-flop (7) sends signal NB to described combinational logic circuit (16), the Q end of described four d flip-flop (7) connects the D end of described the 5th d type flip flop (8) and the input of described the 4th NAND gate (14), the Q end of described the 5th d type flip flop (8) sends signal BD to described combinational logic circuit (16), the QB end of described the 6th d type flip flop (9) connects described the 4th NAND gate (14), and described combinational logic circuit (16) sends signal CA, CB, CC, CD.

2. mechanical relay according to claim 1 drives output protection circuit, it is characterized in that: described signal CA, CB, CC, CD connect field effect transistor PMOS1, NMOS1, PMOS2, NMOS2 respectively, the source electrode of described PMOS1 connects power vd D, drain electrode connects the OA end of relay, grid connects signal CA, the drain electrode of described NMOS1 connects the OA end of described relay, source ground, and grid connects signal CB; Described power vd D connects the source electrode of described PMOS2, the drain electrode of described PMOS2 connects the OB end of described relay, grid connects signal CC, the source ground of described NMOS2, grid connects signal CD, and drain electrode connects the OB end of relay, the positive pole of the source electrode connector diode D1 of described NMOS1, the negative pole of described body diode D1 connects the drain electrode of described NMOS1, the positive pole of the source electrode connector diode D2 of described NMOS2, and the negative pole of described body diode D2 connects the drain electrode of described NMOS2.