CN103346168A - Silicon quantum dot floating gate nonvolatile memory based on SiCx texture and its preparation method - Google Patents

Abstract

The invention discloses a silicon quantum dot floating gate nonvolatile semiconductor memory based on SiC _x texture and a preparation method thereof, comprising a silicon substrate, a source conduction region and a drain conduction region formed by doping on the silicon substrate, And a tunnel oxide layer, a charge storage layer, a control gate oxide layer, and a metal gate layer that are sequentially grown on the _carrier channel between the source and drain; Silicon quantum dots in _x- texture. The invention effectively utilizes the tunneling potential barrier between silicon quantum dots-SiC _x texture, and constitutes a double-step potential barrier charge storage of control gate oxide layer-SiC _x texture-Si quantum dots-SiC _x texture-tunneling oxide layer structure; not only can realize the effective discrete storage of charges, enhance the charge retention characteristics, but also allow the device to have a thinner tunnel oxide layer, which speeds up the erasing and writing speed of charges, so that the comprehensive performance of the memory is comprehensively improved, and the size of the device is Technical support is provided for further zooming out.

Description

Silicon quantum dot floating gate nonvolatile memory based on SiCx texture and its preparation method

technical field

The invention belongs to the technical field of microelectronics, and more specifically relates to a silicon quantum dot floating gate nonvolatile semiconductor memory based on SiC _x texture and a preparation method thereof.

Background technique

With the development of the information industry and semiconductor integrated circuits, the efficient and safe storage and acquisition of a large amount of information has become one of the core technologies of the information age. The integration of large-scale non-volatile memory is to support national network communications, high performance computing and digital The core technology for the development of the electronic information industry, such as application and consumer electronics, is one of the key bottlenecks for the comprehensive, rapid and balanced development of the entire information industry. How to achieve large-scale storage with large capacity, fast read and write speed, low operating voltage and high reliability is a key issue for new non-volatile memories.

Due to the thickness of its own tunneling dielectric layer, the traditional floating gate memory faces great challenges as its size gradually decreases. On the one hand, to achieve faster read and write speeds and lower operating voltage, the tunneling dielectric layer needs to be as thin as possible; on the other hand, to achieve high reliability and high durability, the tunneling dielectric needs to be as thick as possible, which is not good. Take care. With the continuous deepening of research, the rapid development of nanotechnology and the continuous emergence of new materials and new structures, it is necessary to improve the performance of semiconductor memory and develop non-volatile memory with large capacity, high density storage, high speed and low power consumption. good opportunity. The new silicon nanocrystalline non-volatile memory can realize charge separation storage, take into account high read and write speed, low operating voltage and high data retention characteristics, and can solve the above contradictions. Compared with traditional floating gate memory, silicon nanocrystal memory has better data retention characteristics; in addition, since the tunnel oxide layer of silicon nanocrystal memory can be thinner (<5nm), it is more conducive to achieving low operating voltage. However, at present, the silicon nanocrystal non-volatile memory has not yet achieved the expected effect. The main reason is that the separate storage effect of the single silicon nanocrystal is not obvious enough for the charge and the thinner tunnel oxide layer is easy to cause charge leakage, resulting in memory retention characteristics. worse. Therefore, it is of great significance for the development of new non-volatile memory to study how to improve the discrete storage effect of charges, reduce the charge leakage of the tunnel oxide layer, increase the charge retention time, and at the same time achieve high read/write speed and low voltage operation.

At present, the preparation method of the nanocrystalline floating gate charge storage structure is mainly the layer-by-layer growth method. The nanocrystalline floating gate obtained by this method has no obvious effect on the discrete storage of charges, and the preparation process is cumbersome, which is comparable to the traditional CMOS process. Compatibility is poor. Therefore, with the continuous deepening of scientific research, the realization of completely separate storage of charge and the design of a new charge storage structure to obtain high charge retention characteristics and fast reading and writing, to meet the requirements of shrinking device feature size, to find a solution that is comparable to the traditional CMOS process Compatible floating gate preparation methods are the key to the development of nanocrystalline floating gate nonvolatile memory.

Contents of the invention

In view of the above defects or improvement needs of the prior art, the present invention provides a silicon quantum dot floating gate nonvolatile semiconductor memory based on SiC _x texture, the purpose of which is to improve the performance of the nonvolatile memory and realize the storage of charge Large-scale storage with high density, large capacity, fast erasing and writing speed, low operating voltage and high reliability; to achieve effective discrete storage of charges to solve the contradiction between fast erasing and writing, low operating voltage and long retention time.

The invention provides a silicon quantum dot floating gate non-volatile semiconductor memory based on _SiCx texture, comprising a silicon substrate, a source conduction region and a drain conduction region formed by doping on the silicon substrate, and a source and drain region The tunnel oxide layer, the charge _storage layer, the control _gate oxide layer and the metal gate layer are sequentially grown on the carrier channel between them; Silicon quantum dots in the structure.

Furthermore, the material of the tunnel oxide layer is one of SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ and ZrO ₂ , and the tunnel oxide layer The thickness is 2nm ~ 9nm.

Furthermore, the charge storage layer has a thickness of 4nm-15nm.

Furthermore, the silicon quantum dots have a diameter of 1nm-10nm.

Furthermore, the silicon quantum dots have a density of 1×10 ¹¹ cm ^-2 to 1×10 ¹³ cm ^-2 .

Furthermore, the material of the control gate oxide layer is one of SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ and ZrO ₂ , and the control gate oxide layer The thickness is 6nm ~ 30nm.

The present invention also provides a method for preparing the above-mentioned semiconductor memory, comprising the following steps:

S1: Form a layer of tunnel oxide layer with a thickness of 1000 Å on a clean single crystal silicon substrate;

S2: Deposit a silicon-rich SiC _x layer on the tunnel oxide layer, anneal in an argon environment and precipitate silicon quantum dots to form a charge storage layer;

S3: growing a control gate oxide layer with a thickness of 1000 Å on the charge storage layer;

S4: Perform photolithography treatment on the control gate oxide layer, the charge storage layer, and the tunnel oxide layer to form metal source electrodes, drain electrodes, and gate electrodes.

Furthermore, in step S2, the silicon-rich SiC _x layer is deposited on the tunnel oxide layer by using a plasma enhanced chemical vapor deposition process, and the thickness of the silicon-rich SiC _x layer is 4nm-15nm.

Furthermore, in step S2, the annealing treatment specifically includes: annealing at a temperature of 900° C. to 1050° C. for 10 minutes to 30 minutes.

Further, step S4 includes:

S41: sequentially etching the control gate oxide layer, the charge storage layer and the tunnel oxide layer to form a gate line pattern;

S42: Forming source conductive regions and drain conductive regions on both sides of the gate line pattern after ion implantation;

S43: growing an insulating oxide layer and forming source electrode, drain electrode and gate electrode patterns by photolithography;

S44: Evaporating a metal gate layer with a thickness greater than 100 nm;

S45: stripping off the metal between the source electrode, the drain electrode and the gate electrode and forming the metal source electrode, the drain electrode and the gate electrode.

The charge storage layer of the present invention includes a SiC _x texture and a plurality of silicon quantum dots uniformly distributed horizontally and vertically in the SiC _x texture, because it has a double-step potential barrier charge structure and utilizes the Coulomb blocking effect of quantum dots to achieve effective charge separation Storage greatly improves the charge retention time; in addition, the quantum size effect of quantum dots makes the barrier height between Si quantum dots-SiC _x texture adjustable, which is more beneficial to solve the contradiction between erasing and writing speed, operating voltage and charge retention time question.

Description of drawings

1 is a schematic cross-sectional structure diagram of a silicon quantum dot floating gate nonvolatile semiconductor memory based on a SiC _x texture provided by an embodiment of the present invention;

2 is a schematic diagram of an energy band structure of a silicon quantum dot floating gate nonvolatile semiconductor memory based on a SiC _x texture provided by an embodiment of the present invention under flat band conditions.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not constitute a conflict with each other.

Fig. 1 shows the cross-sectional structure of the silicon quantum dot floating gate nonvolatile semiconductor memory based on the SiC _x texture provided by the embodiment of the present invention, including a silicon substrate 1, and a source conductive region formed by doping on the silicon substrate 3 and the drain conductive region 2, and the tunnel oxide layer 4 sequentially grown on the carrier channel between the source and the drain, the silicon quantum dot floating gate charge storage layer based on the SiC _x texture (including the SiC _x texture 5 and Silicon quantum dots 6), control gate oxide layer 7 and metal gate layer 8, wherein the silicon quantum dot floating gate based on the SiC _x (x value is 0 to 1) texture is based on SiC as the matrix, and the silicon quantum dots are inlaid in the SiC parent matrix. Fig. 2 is a schematic diagram of the energy band structure of the memory provided by the present invention under flat-band conditions, wherein E _C and E _V are the bottom of the conduction band and the top of the valence band of the material, respectively, and _EF is the Fermi level. The memory provided by the present invention utilizes silicon quantum dots based on the _SiCx texture as a floating gate. Since the quantum dots have a Coulomb blocking effect, effective discrete storage of charges can be realized; the silicon quantum dots 6 are evenly distributed horizontally and vertically independently of each other In SiC _x texture 5, the tunneling barrier Φ ₂ between Si quantum dots and SiC _x texture (as shown in Figure 2) effectively prevents the horizontal and vertical movement of charges and charge leakage, and enhances the charge retention characteristics; In addition, the lower tunneling potential barrier Φ ₂ between Si quantum dots and SiC _x texture realizes effective discrete storage of charges, and does not need to increase the operating voltage to compensate for the influence of the barrier height on the charge erasing process, because The high electric field generated by the erasing and writing voltage makes the energy of the charge far greater than the height of the potential barrier. It can be approximated that the movement of the charge in the erasing and writing process is only affected by the barrier _Φ1 between the Si-tunneling oxide layers. In the process of charge retention, as shown in Figure 2, the discretely stored charges need to pass through the potential barriers Φ ₂ and Φ ₁ to leak back to the substrate channel, and the tunneling probability is much higher than only passing through the potential barrier Φ ₁ Reduced, thereby reducing the leakage of charges and improving the charge retention characteristics; for the double-step tunneling barrier structure, due to the existence of Si quantum dots- _SiCx texture inter-potential barrier Φ ₂ , the device can be allowed to have thinner tunneling Oxide layer 4, which is conducive to the realization of direct tunneling, greatly speeding up the erasing and writing speed of charges; therefore, the memory avoids the sacrifice of charge retention characteristics to meet the requirements of new memory for faster erasing and writing and low-voltage operation, and at the same time It is also possible to further reduce the size of the device. By adjusting the barrier height between Si quantum dots and SiC _x texture through the quantum size effect, the device performance can be further comprehensively optimized.

The tunnel oxide layer in the silicon quantum dot floating gate memory based on the SiC _x texture provided by the embodiment of the present invention can be silicon dioxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), yttrium oxide (Y ₂ O ₃ ) , lanthanum oxide (La ₂ O ₅ ), titanium dioxide (TiO ₂ ), hafnium oxide (HfO ₂ ) and zirconium dioxide (ZrO ₂ ); its thickness can be 2nm to 9nm. A thin tunneling oxide layer is beneficial to increase the tunneling probability of charges, thereby increasing the erasing and writing speed and reducing the operating voltage; however, an excessively thin tunneling oxide layer will increase the leakage probability and shorten the charge retention time. The SiO ₂ tunneling layer as thin as 2nm is used here, which greatly improves the erasing and writing speed and reduces the operating voltage under the premise of ensuring the charge retention time; the tunneling oxide layer with high dielectric constant (such as Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ and ZrO _{2 ,} etc.), the tunnel oxide layer whose actual oxide thickness is thicker than SiO ₂ can be designed to obtain the same electrical thickness (equivalent oxide layer thickness) as SiO ₂ , thus The probability of leakage of charge is greatly reduced, and the retention time of charge is effectively improved.

The silicon quantum dot charge storage layer based on the SiC _x texture in the silicon quantum dot floating gate memory based on the SiC _x texture provided by the embodiment of the present invention is firstly deposited by a plasma enhanced chemical vapor deposition (PlasmaEnhanced Chemical Vapor Deposition, PECVD) process. A layer of silicon-rich SiC _x thin film is formed by annealing (10min-30min) at high temperature (900°C-1050°C) in an argon atmosphere to precipitate silicon quantum dots. This process can generate silicon-rich SiC _x film at one time, without the need to grow multi-layer films, the process is simple and easy to control; annealing in an inert gas argon environment can avoid the introduction of other impurity elements; by controlling the annealing temperature and annealing time to Adjust the density and size of the precipitated silicon quantum dots.

The thickness of the silicon quantum dot charge storage layer based on the SiC _x texture in the silicon quantum dot floating gate memory based on the SiC _x texture provided by the embodiment of the present invention is 4nm to 15nm; the thick charge storage layer contains more silicon quantum dots , is conducive to the realization of high-density charge storage, while reducing the probability of charge leakage, but will increase the operating voltage of the gate; a thin charge storage layer is conducive to improving the erasing and writing speed and reducing the operating voltage, but it is not conducive to the discrete storage of charges, which will increase The probability of leakage of charge.

The floating gate of the silicon quantum dot floating gate memory based on the SiC _x texture provided by the embodiment of the present invention is based on the silicon quantum dots of the SiC _x texture, and the silicon quantum dots are independently distributed horizontally and vertically in the SiC _x texture , the lateral distribution can realize the discrete storage of charges, and the vertical distribution can realize the multi-layer storage of charges. The diameter of silicon quantum dots is between 1nm and 10nm; the density of silicon quantum dots is between 1×10 ¹¹ cm ^-2 and 1×10 Between ¹³ cm ^-2 . High-density, small-sized silicon quantum dots are conducive to the effective discrete storage of charges, but require a large operating voltage to achieve erasing; due to the quantum size effect, small-density, large-sized silicon quantum dots will make silicon quantum dots-SiC The reduction of the potential barrier between _{the x-} textures is beneficial to reduce the operating voltage, but it will weaken the discrete storage effect of charges and increase the leakage probability of charges. Based on the above factors, it is found that when the size and density of silicon quantum dots are within the above range, the performance of the device is the best.

The control gate oxide layer in the silicon quantum dot floating gate memory based on the SiC _x texture provided by the embodiment of the present invention can also be SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ and One of ZrO ₂ etc.; its thickness is 6nm to 30nm. The control gate oxide layer with high dielectric constant is used to design an oxide layer whose actual oxide thickness is thicker than that of SiO ₂ to obtain the same electrical thickness (equivalent oxide layer thickness) as SiO ₂ , which can effectively reduce the gate leakage of charges and enhance device reliability.

The silicon quantum dot floating gate memory based on the _SiCx texture provided by the present invention, the control gate oxide layer, the silicon quantum dot charge storage layer and the tunnel oxide layer based on the _SiCx texture constitute the control gate oxide layer- _SiCx Texture-Si quantum dots-SiC _x texture-tunnel oxide layer double-step barrier charge storage structure, because quantum dots have a quantum size effect, the relationship between silicon quantum dots and SiC _x texture can be changed by changing the size of silicon quantum dots Tunneling barrier height.

The specific preparation method of the above-mentioned silicon quantum dot floating gate memory based on SiC _x texture comprises the following steps:

(1) Form a tunneling oxide layer with a thickness of 2nm to 9nm on a clean single crystal silicon substrate. The types of tunneling oxide layer include SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ , and ZrO _{2 ,} etc., using processes such as thermal oxidation, magnetron sputtering, electron beam evaporation, and atomic layer deposition.

(2) Deposit a 4nm to 15nm silicon-rich SiC _x layer on the tunneling oxide layer by plasma enhanced chemical vapor deposition (PECVD), and then anneal at high temperature (900°C to 1050°C) for 10min to 30min in an argon atmosphere to precipitate silicon quantum dots;

(3) A control gate oxide layer with a thickness between 6nm and 30nm is grown on the charge storage layer. The types of control gate oxide layer include SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ and ZrO ₂ , etc., the process can be PECVD, magnetron sputtering, electron beam evaporation and atomic layer deposition, etc.;

(4) Photolithography forms the gate line pattern, and sequentially etches the control gate oxide layer, the silicon quantum dot floating gate charge storage layer (including SiC _x texture and silicon quantum dots) based on the SiC _x texture, and the tunnel oxide layer; Implantation, forming source conductive region and drain conductive region on both sides of the gate line; growing insulating oxide layer, photolithography, and corroding the insulating oxide layer; evaporating metal gate layer, the thickness of the metal gate layer is more than 100nm; stripping to form metal source, drain and gate electrode.

In order to further illustrate the silicon quantum dot floating gate memory based on the _SiCx texture provided by the embodiment of the present invention, the details are as follows:

A tunnel oxide layer 4 is formed on a clean single crystal silicon substrate 1, and the types of the tunnel oxide layer 4 include SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ and ZrO ₂ etc.; the adopted process may be thermal oxidation, magnetron sputtering, electron beam evaporation and atomic layer deposition, etc.; the thickness of the tunneling oxide layer 4 is between 2nm and 9nm. A silicon quantum dot floating gate charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dots 6) is formed on the tunnel oxide layer 4; A silicon-rich SiC _x layer 5 is deposited on the oxide layer 4, and then a high-temperature (900°C-1050°C) annealing (10min-30min) process is used to precipitate silicon quantum dots 6; the silicon quantum dots 6 are independently distributed horizontally and vertically on the _SiCx In the texture 5; the diameter of the silicon quantum dot 6 is between 1nm and 10nm; the density of the silicon quantum dot is between 1×10 ¹¹ cm ^-2 and 1×10 ¹³ cm ^-2 ; the silicon quantum dot based on SiC _x texture The thickness of the charge storage layer is 4nm to 15nm. Form the control gate oxide layer 7 on the silicon quantum dot charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dot 6), and the type of control gate oxide layer 7 also includes SiO ₂ , Al ₂ O ₃ , Y ₂ O ₃ , La ₂ O ₅ , TiO ₂ , HfO ₂ , and ZrO _{2 ,} etc.; the techniques used can be PECVD, magnetron sputtering, electron beam evaporation, and atomic layer deposition; the thickness of the gate oxide layer 7 is controlled at 6nm to 30nm. Then, photolithography forms the gate line pattern, and sequentially etches the control gate oxide layer 7, the silicon quantum dot floating gate charge storage layer based on the SiC _x texture (including the SiC _x texture 5 and the silicon quantum dot 6) and the tunnel oxide layer 4. Ion implantation, forming a source conductive region 3 and a drain conductive region 2 on both sides of the gate line; growing an insulating oxide layer, photolithography, and corroding the insulating oxide layer; evaporating a metal gate layer 8, the thickness of which is more than 100nm; Lifting off forms metal source, drain and gate electrodes.

The preparation method of the silicon quantum dot floating gate nonvolatile memory based on the _SiCx texture provided by the present invention is further described in detail with the help of specific implementation examples:

Example 1:

(1) Cleaning the P-type monocrystalline silicon substrate 1;

(2) A _SiO2 tunneling layer 4 with a thickness of 2nm is formed on a clean P-type single crystal silicon substrate 1 by thermal oxidation process, wherein the oxygen flow rate is 500ml/min, the temperature is 900°C, and the oxidation time is 2.5 min;

(3) Deposit a silicon-rich SiC _x layer 5 with a thickness of 4nm on the SiO ₂ tunneling layer 4 by plasma-enhanced chemical vapor deposition (PECVD) technology, in which the flow rate of CH ₄ is 20 sccm, and the volume is diluted by H ₂ The flow rate of SiH ₄ with a ratio of 10% is 50 sccm, the substrate temperature is 200°C, the RF power is 100W, and the chamber pressure is 0.8Torr;

(4) High-temperature annealing for 10 minutes in an argon environment, wherein the temperature is 900°C, the diameter of the precipitated silicon quantum dots 6 is about 1 nm, and the density is about 1×10 ¹³ cm ^-2 ;

(5) A SiO ₂ control gate oxide layer 7 with a thickness of 6 nm was deposited on the silicon quantum dot floating gate charge storage layer based on the SiC _x texture by using magnetron sputtering technology, where the sputtering target was a SiO ₂ target. The argon gas flow rate is 20 sccm, the oxygen flow rate is 10 sccm, the substrate temperature is 200°C, and the power is 120W;

(6) Photolithography, forming a gate line pattern, sequentially etching the control gate oxide layer 7, the silicon quantum dot floating gate charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dot 6) and tunneling oxide layer 4;

(7) Ion implantation, forming a source conductive region 3 and a drain conductive region 2 on both sides of the gate line; growing an insulating oxide layer, photolithography, and etching the insulating oxide layer; vapor-depositing an Al gate layer 8 with a thickness of 1 μm; Stripping to form Al source, drain and gate electrodes;

(8) Annealing in an argon atmosphere to form a good contact between the metal and the semiconductor.

Example 2:

(1) Cleaning the P-type monocrystalline silicon substrate 1;

(2) A _SiO2 tunneling layer 4 with a thickness of 2nm is formed on a clean P-type single crystal silicon substrate 1 by thermal oxidation process, wherein the oxygen flow rate is 500ml/min, the temperature is 900°C, and the oxidation time is 2.5 min;

(3) Deposit a silicon-rich SiC _x layer 5 with a thickness of 10 nm on the SiO ₂ tunneling layer 4 by plasma-enhanced chemical vapor deposition (PECVD), in which CH ₄ flow rate is 20 sccm, and the volume is diluted by H ₂ The flow rate of SiH ₄ with a ratio of 10% is 50 sccm, the substrate temperature is 200°C, the RF power is 100W, and the cavity pressure is 0.8Torr;

(4) High-temperature annealing for 20 minutes in an argon environment, wherein the temperature is 1000°C, the diameter of the precipitated silicon quantum dots 6 is about 4 nm, and the density is about 1×10 ¹² m ^-2 ;

(5) A gate oxide layer 7 made of Al ₂ O ₃ with a thickness of 12 nm was deposited on the silicon quantum dot floating gate charge storage layer based on SiC _x texture by using magnetron sputtering technology, wherein the sputtering target was an Al target, The argon flow rate is 20 sccm, the oxygen flow rate is 5 sccm, the substrate temperature is 200°C, and the power is 100W;

(6) Photolithography, forming a gate line pattern, sequentially etching the control gate oxide layer 7, the silicon quantum dot floating gate charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dot 6) and tunneling oxide layer 4;

(7) Ion implantation, forming a source conductive region 3 and a drain conductive region 2 on both sides of the gate line; growing an insulating oxide layer, photolithography, and etching the insulating oxide layer; vapor-depositing an Al gate layer 8 with a thickness of 1 μm; Stripping to form Al source, drain and gate electrodes;

(8) Annealing in an argon atmosphere to form a good contact between the metal and the semiconductor.

Example 3:

(1) Cleaning the P-type monocrystalline silicon substrate 1;

(2) A layer of Al ₂ O ₃ tunneling oxide layer 4 with a thickness of 4 nm is formed on the silicon substrate 1 by magnetron sputtering technology, wherein the sputtering target is an Al target, and the flow rate of argon gas is 20 sccm, oxygen The flow rate is 5 sccm, the substrate temperature is 200°C, and the power is 100W;

(3) Deposit a silicon-rich SiC _x layer 5 with a thickness of 15nm on the SiO ₂ tunneling layer 4 by plasma-enhanced chemical vapor deposition (PECVD), in which CH ₄ flow rate is 20 sccm, and the volume is diluted by H ₂ The flow rate of SiH ₄ with a ratio of 10% is 50 sccm, the substrate temperature is 200°C, the RF power is 100W, and the chamber pressure is 0.8Torr;

(4) High-temperature annealing for 30 minutes in an argon atmosphere, wherein the temperature is 1000°C, the diameter of the precipitated silicon quantum dots 6 is about 6 nm, and the density is about 1×10 ¹² m ^-2 ;

(5) Deposit and form an Al ₂ O ₃ control gate oxide layer 7 with a thickness of 12 nm on the silicon quantum dot floating gate charge storage layer based on SiC _x texture by atomic layer deposition (ALD);

(6) Photolithography, forming a gate line pattern, sequentially etching the control gate oxide layer 7, the silicon quantum dot floating gate charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dot 6) and tunneling Oxide layer 4.

(7) Ion implantation, forming a source conductive region 3 and a drain conductive region 2 on both sides of the gate line; growing an insulating oxide layer, photolithography, and etching the insulating oxide layer; vapor-depositing an Al gate layer 8 with a thickness of 1 μm; Al source, drain and gate electrodes are formed by stripping.

(8) Annealing in an argon atmosphere to form a good contact between the metal and the semiconductor.

Example 4:

(1) Cleaning the P-type monocrystalline silicon substrate 1;

(2) A layer of HfO ₂ tunneling oxide layer 4 with a thickness of 9nm is formed on the silicon substrate by using magnetron sputtering technology. The sputtering target is HfO ₂ target. 5sccm, RF power is 100W, substrate temperature is 200℃;

(3) Deposit a silicon-rich SiC _x layer 5 with a thickness of 15nm on the SiO ₂ tunneling layer 4 by plasma-enhanced chemical vapor deposition (PECVD), in which CH ₄ flow rate is 20 sccm, and the volume is diluted by H ₂ The flow rate of SiH ₄ with a ratio of 10% is 50 sccm, the substrate temperature is 200°C, the RF power is 100W, and the cavity pressure is 0.8Torr;

(4) High-temperature annealing for 30 minutes in an argon atmosphere, wherein the temperature is 1000°C, the diameter of the precipitated silicon quantum dots 6 is about 6 nm, and the density is about 1×10 ¹² m ^-2 ;

(5) Deposit and form an Al ₂ O ₃ control gate oxide layer 7 with a thickness of 12 nm on the silicon quantum dot floating gate charge storage layer based on SiC _x texture by atomic layer deposition (ALD);

(6) Photolithography, forming a gate line pattern, sequentially etching the control gate oxide layer 7, the silicon quantum dot floating gate charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dot 6) and tunneling Oxide layer 4.

(7) Ion implantation, forming a source conductive region 3 and a drain conductive region 2 on both sides of the gate line; growing an insulating oxide layer, photolithography, and etching the insulating oxide layer; vapor-depositing an Al gate layer 8 with a thickness of 1 μm; Al source, drain and gate electrodes are formed by stripping.

(8) Annealing in an argon atmosphere to form a good contact between the metal and the semiconductor.

Example 5:

(1) Cleaning the P-type monocrystalline silicon substrate 1;

(2) A layer of HfO ₂ tunneling oxide layer 4 with a thickness of 9nm is formed on the silicon substrate by using magnetron sputtering technology. The sputtering target is HfO ₂ target. 5sccm, RF power is 100W, substrate temperature is 200℃;

(3) Deposit a silicon-rich SiC _x layer 5 with a thickness of 15nm on the SiO ₂ tunneling layer 4 by plasma-enhanced chemical vapor deposition (PECVD), in which CH ₄ flow rate is 20 sccm, and the volume is diluted by H ₂ The flow rate of SiH ₄ with a ratio of 10% is 50 sccm, the substrate temperature is 200°C, the RF power is 100W, and the chamber pressure is 0.8Torr;

(4) High-temperature annealing for 30 minutes in an argon environment, wherein the temperature is 1050°C, the diameter of the precipitated silicon quantum dots 6 is about 10 nm, and the density is about 1×10 ¹¹ cm ^-2 ;

(5) A _HfO2 control gate oxide layer 7 with a thickness of 30nm is deposited on the silicon quantum dot floating gate charge storage layer based on the _SiCx texture by magnetron sputtering technology, where the sputtering target is an _HfO2 target, The argon gas flow rate is 15 sccm, the oxygen flow rate is 5 sccm, the radio frequency power is 100W, and the substrate temperature is 200°C;

(6) Photolithography, forming a gate line pattern, sequentially etching the control gate oxide layer 7, the silicon quantum dot floating gate charge storage layer based on SiC _x texture (including SiC _x texture 5 and silicon quantum dot 6) and tunneling Oxide layer 4.

(7) Ion implantation, forming a source conductive region 3 and a drain conductive region 2 on both sides of the gate line; growing an insulating oxide layer, photolithography, and etching the insulating oxide layer; vapor-depositing an Al gate layer 8 with a thickness of 1 μm; Al source, drain and gate electrodes are formed by stripping.

(8) Annealing in an argon atmosphere to form a good contact between the metal and the semiconductor.

The silicon quantum dot floating gate nonvolatile memory based on the SiC _x texture obtained by the above preparation method includes a silicon substrate, a source-drain conductive region doped on the silicon substrate, and a carrier channel between the source and drain The tunnel oxide layer, the SiC _x texture-based silicon quantum dot floating gate charge storage layer, the control gate oxide layer and the metal gate layer are sequentially covered; the tunneling barrier between the silicon quantum dot-SiC _x texture is effectively used, A control gate oxide layer-SiC _x texture-Si quantum dot-SiC _x texture-tunnel oxide layer double-step potential barrier charge storage structure is formed. This structure can not only realize the effective discrete storage of charges, enhance the charge retention characteristics, allow the device to have a thinner tunnel oxide layer, and accelerate the erasing and writing speed of charges to a certain extent. The structure can improve the overall performance of the memory and provide technical support for further reducing the size of the device.

Those skilled in the art can easily understand that the above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention, All should be included within the protection scope of the present invention.

Claims (10)

1. one kind based on SiC _xThe silicon quantum dot floating gate non-volatile semiconductor memory of texture, it is characterized in that, comprise silicon substrate, at source conduction region and the leakage conduction region of silicon substrate doping formation, and tunnel oxide, charge storage layer, control gate oxide layer and the metal gate layer of growing successively on the carrier channels between leak in the source; Described charge storage layer comprises SiC _xTexture and a plurality of transverse and longitudinal are uniformly distributed in SiC _xSilicon quantum dot in the texture has constituted control gate oxide layer-SiC _xTexture-Si quantum dot-SiC _xThe two ladder potential barrier charge storage structures of texture-tunnel oxide.

2. semiconductor memory as claimed in claim 1 is characterized in that, the material of described tunnel oxide is SiO ₂, Al ₂O ₃, Y ₂O ₃, La ₂O ₅, TiO ₂, HfO ₂And ZrO ₂In a kind of, the thickness of described tunnel oxide is 2nm～9nm.

3. semiconductor memory as claimed in claim 1 is characterized in that, the thickness of described charge storage layer is 4nm～15nm.

4. as claim 1 or 3 described semiconductor memories, it is characterized in that described silicon quantum dot diameter is at 1nm～10nm.

5. as claim 1 or 3 or 4 described semiconductor memories, it is characterized in that the density of described silicon quantum dot is 1 * 10 ¹¹Cm ^-21 * 10 ¹³Cm ^-2

6. semiconductor memory as claimed in claim 1 is characterized in that, the material of described control gate oxide layer is SiO ₂, Al ₂O ₃, Y ₂O ₃, La ₂O ₅, TiO ₂, HfO ₂And ZrO ₂In a kind of, described control gate thickness of oxide layer is 6nm～30nm.

7. a method for preparing each described semiconductor memory of claim 1-6 is characterized in that, comprises the steps:

S1: the monocrystalline substrate in cleaning forms one deck tunnel oxide;

S2: at tunnel oxide deposition Silicon-rich SiC _xThe layer, under ar gas environment annealing in process and separate out silicon quantum dot after form charge storage layer;

S3: in described charge storage layer growth one deck control gate oxide layer;

S4: described control gate oxide layer, described charge storage layer and described tunnel oxide are carried out photoetching treatment, form source metal electrode, drain electrode and gate electrode.

8. method as claimed in claim 7 is characterized in that, in step S2, adopts plasma reinforced chemical vapour deposition technology at the described Silicon-rich SiC of described tunnel oxide deposition _xLayer, described Silicon-rich SiC _xThe thickness of layer is 4nm～15nm.

9. method as claimed in claim 7 is characterized in that, in step S2, described annealing in process is specially: 10min～30min anneals under 900 ℃～1050 ℃ temperature.

10. method as claimed in claim 7 is characterized in that, step S4 comprises:

S41: the described control gate oxide layer of etching, described charge storage layer and described tunnel oxide and form the grid line figure successively;

S42: ion injects the back and forms the source conduction region in described grid line figure both sides and leak conduction region;

S43: growth insulating oxide and chemical wet etching form source electrode, drain electrode and gate electrode figure;

S44: evaporation thickness is greater than the metal gate layer of 100nm;

S45: peel off source electrode, drain electrode and gate electrode between any two metal and form source metal electrode, drain electrode and gate electrode.

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