CN103346168A - Silicon quantum dot floating gate nonvolatile memory and preparing method thereof based on SiCx texture - Google Patents
Silicon quantum dot floating gate nonvolatile memory and preparing method thereof based on SiCx texture Download PDFInfo
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- CN103346168A CN103346168A CN2013102485835A CN201310248583A CN103346168A CN 103346168 A CN103346168 A CN 103346168A CN 2013102485835 A CN2013102485835 A CN 2013102485835A CN 201310248583 A CN201310248583 A CN 201310248583A CN 103346168 A CN103346168 A CN 103346168A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 122
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 122
- 239000010703 silicon Substances 0.000 title claims abstract description 122
- 239000002096 quantum dot Substances 0.000 title claims abstract description 92
- 238000007667 floating Methods 0.000 title claims abstract description 37
- 230000015654 memory Effects 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 34
- 229910004012 SiCx Inorganic materials 0.000 title abstract 9
- 238000003860 storage Methods 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000005036 potential barrier Methods 0.000 claims abstract description 12
- 238000005516 engineering process Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000137 annealing Methods 0.000 claims description 19
- 230000008569 process Effects 0.000 claims description 19
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 17
- 238000000151 deposition Methods 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 16
- 229910010413 TiO 2 Inorganic materials 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000001704 evaporation Methods 0.000 claims description 9
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 230000005641 tunneling Effects 0.000 abstract description 9
- 150000003376 silicon Chemical class 0.000 abstract 2
- 239000002800 charge carrier Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 115
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 22
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 16
- 238000009825 accumulation Methods 0.000 description 15
- 239000007789 gas Substances 0.000 description 14
- 229910052786 argon Inorganic materials 0.000 description 11
- 230000014759 maintenance of location Effects 0.000 description 11
- 238000001755 magnetron sputter deposition Methods 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 239000001301 oxygen Substances 0.000 description 8
- 229910052760 oxygen Inorganic materials 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 8
- 238000005260 corrosion Methods 0.000 description 7
- 230000007797 corrosion Effects 0.000 description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 239000002159 nanocrystal Substances 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000005477 sputtering target Methods 0.000 description 6
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- 238000010790 dilution Methods 0.000 description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000008094 contradictory effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
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- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
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- 235000012239 silicon dioxide Nutrition 0.000 description 1
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Abstract
The invention discloses a silicon quantum dot floating gate nonvolatile memory and a preparing method of the silicon quantum dot floating gate nonvolatile memory based on a SiCx texture. The silicon quantum dot floating gate nonvolatile memory based on the SiCx texture comprises a silicon substrate. A source conduction region, a leak conduction region, a tunneling oxide layer, a charge storage layer, a control gate oxide layer and a metal gate layer are formed and mingled on the silicon substrate, wherein the tunneling oxide layer, the charge storage layer, the control gate oxide layer and the metal gate layer are developed sequentially on a charge carrier channel between the source conduction region and the leak conduction region. The charge storage layer comprises the SiCx texture and silicon quantum dots evenly distributed in the SiCx texture in the transverse direction and the longitudinal direction. According to the silicon quantum dot floating gate nonvolatile memory based on the SiCx texture, tunneling potential barriers among the silicon quantum dots and the SiCx texture are effectively used, so that a control gate oxide layer- SiCx texture-Si quantum dot-SiCx texture- tunneling oxide layer double-step potential barrier charge storage structure is formed; charges can be effectively stored in a separated mode, the maintaining character of the charges is enhanced, a device is provided with the thinner tunneling oxide layer, the erasing speed of the charges is accelerated, the comprehensive performance of the memory is improved overall, and technical support is offered for further reduction of the size of the device.
Description
Technical field
The invention belongs to microelectronics technology, more specifically, relate to a kind of based on SiC
xSilicon quantum dot floating gate non-volatile semiconductor memory of texture and preparation method thereof.
Background technology
Development along with information industry and semiconductor integrated circuit, one of core technology that becomes the information age is stored and obtained to highly effective and safe to bulk information, the integrated of extensive nonvolatile memory is the core technology that supports electronics and information industry development such as national network communication, high-performance calculation and digital application, consumer electronics, is one of critical bottleneck of the comprehensively quick balanced growth of whole information industry.How to realize that the extensive storage that capacity is big, read or write speed is fast, operating voltage is low and reliability is high is the critical problem of novel nonvolatile memory.
Traditional floating-gate memory is because the thickness problem of self tunneling medium layer, along with size reduces to be faced with great challenge gradually.On the one hand, realize faster read or write speed, low-work voltage more, need tunneling medium layer thin as far as possible; On the other hand, realize high reliability, high-durability, need the tunnelling medium thick as far as possible again, both are bad to take into account.Along with the continuous appearance with new material, new construction of developing rapidly of the deepening continuously of research, nanometer technology, be to improve the semiconductor memory performance, big capacity, high density storage are had both in development, at a high speed, the nonvolatile memory of low-power consumption provides good opportunity.The nanocrystalline nonvolatile storage of novel silicon can be realized the discrete storage of electric charge, takes into account high read or write speed, low-work voltage and high data retention characteristics, can solve above contradiction.The silicon nanocrystal memory is compared with traditional floating-gate memory has better data retention characteristics; In addition, because the tunnel oxide of silicon nanocrystal memory can be thinner (＜5nm), so more be conducive to realize low operating voltage.But, the silicon nanocrystal nonvolatile memory still falls flat at present, its main cause be independent silicon nanocrystal for the discrete storage effect of electric charge inadequately obvious and thinner tunnel oxide easily cause electric charge to leak, cause memory retention performance variation.Therefore, how research improves the discrete storage effect to electric charge, and the electric charge that reduces tunnel oxide leaks, and promotes charge retention time, realizes high read or write speed, low voltage operating again simultaneously, and is significant to the development of novel nonvolatile storage.
The preparation method of nano-crystal floating gate charge storage structure mainly is the layer-by-layer growing method at present, the nano-crystal floating gate that adopts the method to obtain is also not obvious for the discrete storage effect of electric charge, and preparation section is loaded down with trivial details, with traditional cmos process compatible ability mutually.Therefore, along with deepening continuously of scientific research, realization is to electric charge discrete storage and design new charge storage structure and obtain the high retention performance of electric charge and fast reading and writing up hill and dale, satisfy the requirement that device feature size constantly dwindles, seek with traditional cmos process mutually compatible floating boom preparation method be the key that develops the nano-crystal floating gate nonvolatile memory.
Summary of the invention
Above defective or improvement demand at prior art the invention provides a kind of based on SiC
xThe silicon quantum dot floating gate non-volatile semiconductor memory of texture, its purpose is to improve the performance of nonvolatile memory, realizes stored charge density height, big, the erasable speed of capacity is fast, operating voltage low and the high extensive storage of reliability; Solve erasable, low-work voltage and the contradictory problems between the long retention time fast with the effective discrete storage that realizes electric charge.
The invention provides a kind of based on SiC
xThe silicon quantum dot floating gate non-volatile semiconductor memory of texture, comprise silicon substrate, at source conduction region and the leakage conduction region of silicon substrate doping formation, and tunnel oxide, charge storage layer, control gate oxide layer and the metal gate layer of growing successively on the carrier channels between leak in the source; Described charge storage layer comprises SiC
xTexture and a plurality of transverse and longitudinal are uniformly distributed in SiC
xSilicon quantum dot in the texture.
Further, the material of described tunnel oxide is SiO
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2In a kind of, the thickness of described tunnel oxide is 2nm～9nm.
Further, the thickness of described charge storage layer is 4nm～15nm.
Further, described silicon quantum dot diameter is at 1nm～10nm.
Further, the density of described silicon quantum dot is 1 * 10
11Cm
-2～1 * 10
13Cm
-2
Further, the material of described control gate oxide layer is SiO
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2In a kind of, described control gate thickness of oxide layer is 6nm～30nm.
The present invention also provides a kind of method for preparing above-mentioned semiconductor memory, comprises the steps:
S1: the monocrystalline substrate in cleaning forms the tunnel oxide that a layer thickness is;
S2: at tunnel oxide deposition Silicon-rich SiC
xThe layer, under ar gas environment annealing in process and separate out silicon quantum dot after form charge storage layer;
S3: described charge storage layer growth one layer thickness the control gate oxide layer;
S4: described control gate oxide layer, described charge storage layer and described tunnel oxide are carried out photoetching treatment, form source metal electrode, drain electrode and gate electrode.
Further, in step S2, adopt plasma reinforced chemical vapour deposition technology at the described Silicon-rich SiC of described tunnel oxide deposition
xLayer, described Silicon-rich SiC
xThe thickness of layer is 4nm～15nm.
Further, in step S2, described annealing in process is specially: 10min～30min anneals under 900 ℃～1050 ℃ temperature.
Further, step S4 comprises:
S41: the described control gate oxide layer of etching, described charge storage layer and described tunnel oxide and form the grid line figure successively;
S42: ion injects the back and forms the source conduction region in described grid line figure both sides and leak conduction region;
S43: growth insulating oxide and chemical wet etching form source electrode, drain electrode and gate electrode figure;
S44: evaporation thickness is greater than the metal gate layer of 100nm;
S45: peel off source electrode, drain electrode and gate electrode between any two metal and form source metal electrode, drain electrode and gate electrode.
Charge storage layer of the present invention comprises SiC
xTexture and a plurality of transverse and longitudinal are uniformly distributed in SiC
xSilicon quantum dot in the texture because it has two ladder potential barrier charge structures and utilizes the coulomb blockade effect of quantum dot to realize the effective discrete storage of electric charge, has promoted charge retention time greatly; In addition, the quantum size effect of quantum dot makes Si quantum dot-SiC
xBarrier height is adjustable between texture, more is of value to the contradictory problems that solves between erasable speed, operating voltage and charge retention time.
Description of drawings
Fig. 1 be the embodiment of the invention provide based on SiC
xThe cross-sectional view of the silicon quantum dot floating gate non-volatile semiconductor memory of texture;
Fig. 2 be the embodiment of the invention provide based on SiC
xThe band structure schematic diagram of silicon quantum dot floating gate non-volatile semiconductor memory under the flat rubber belting condition of texture.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.In addition, below in each execution mode of described the present invention involved technical characterictic just can not make up mutually as long as constitute conflict each other.
Fig. 1 show that the embodiment of the invention provides based on SiC
xThe cross-section structure of the silicon quantum dot floating gate non-volatile semiconductor memory of texture, comprise silicon substrate 1, the source conduction region 3 that mix to form at silicon substrate and leak conduction region 2, and in the source and between leaking on the carrier channels successively the tunnel oxide 4 of growth, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture 5 and silicon quantum dot 6), control gate oxide layer 7 and metal gate layer 8, wherein based on SiC
xThe silicon quantum dot floating boom of (the x value is 0～1) texture is to be parent matrix with SiC, and silicon quantum dot is embedded among the SiC parent matrix.Fig. 2 is the band structure schematic diagram of memory provided by the invention under the flat rubber belting condition, wherein E
CAnd E
VBe respectively at the bottom of the conduction band of material and top of valence band, E
FBe Fermi level.Memory utilization provided by the invention is based on SiC
xThe silicon quantum dot of texture is as floating boom, because quantum dot has the coulomb blockade effect, so can realize the effective discrete storage to electric charge; Silicon quantum dot 6 be mutually independent ground transverse and longitudinal be evenly distributed on SiC
xIn the texture 5, be present in Si quantum dot-SiC
xTunneling barrier Φ between texture
2(as shown in Figure 2) effectively stop the transverse and longitudinal of electric charge to move and the electric charge leakage, strengthened charge-retention property; In addition, Si quantum dot-SiC
xLower tunneling barrier Φ between texture
2When realizing the effective discrete storage of electric charge, also do not need to increase operating voltage and remedy this barrier height to the influence of the erasable process of electric charge, because the high electric field that erasable voltage produces makes the energy of electric charge be far longer than the height of this potential barrier, can be similar to and think that the motion of electric charge only is subjected to Si-tunnel oxide interlayer potential barrier Φ in erasable process
1Influence.In electric charge maintenance process, as shown in Figure 2, discrete charge stored will be leaked back substrate channel need pass potential barrier Φ
2And Φ
1, and only pass potential barrier Φ
1Compare, its tunnelling probability reduces greatly, thereby has reduced the leakage of electric charge, has improved charge-retention property; For two ladder tunneling barrier structures, because Si quantum dot-SiC
xPotential barrier Φ between texture
2Existence, can allow device to have thinner tunnel oxide 4, thereby be conducive to realize direct tunnelling, accelerated the erasable speed of electric charge greatly; So it is that cost satisfies novel memory to the requirement of quicker erasable and low voltage operating that this memory has been avoided to sacrifice charge-retention property, simultaneously size of devices is further dwindled.Regulate Si quantum dot-SiC by quantum size effect
xBarrier height between texture, further complex optimum device performance.
The embodiment of the invention provide based on SiC
xTunnel oxide can be silicon dioxide (SiO in the silicon quantum dot floating-gate memory of texture
2), aluminium oxide (Al
2O
3), yittrium oxide (Y
2O
3), lanthana (La
2O
5), titanium dioxide (TiO
2), hafnium oxide (HfO
2) and zirconium dioxide (ZrO
2) wait wherein a kind of; Its thickness can arrive 9nm for 2nm.Thin tunnel oxide is conducive to improve the tunnelling probability of electric charge, and then improves erasable speed and reduce operating voltage; But thin excessively tunnel oxide can increase the electric leakage probability, shortens charge retention time.Here adopt the SiO that is as thin as 2nm
2Tunnel layer under the prerequisite that has guaranteed charge retention time, has improved erasable speed greatly and has reduced operating voltage; Adopt the tunnel oxide of high-k (as Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2Deng), can design actual oxidated layer thickness than SiO
2Thick tunnel oxide obtains and SiO
2Identical electrical thickness (equivalent oxide thickness), thus greatly reduce the leakage probability of electric charge, the retention time of effectively having improved electric charge.
The embodiment of the invention provide based on SiC
xIn the silicon quantum dot floating-gate memory of texture based on SiC
xThe silicon quantum dot charge storage layer of texture is to adopt plasma reinforced chemical vapour deposition technology (Plasma Enhanced Chemical Vapor Deposition, the PECVD) SiC of process deposits one deck Silicon-rich earlier
xFilm, (10min～30min) separates out that silicon quantum dot forms in high temperature (900 ℃～1050 ℃) annealing under the ar gas environment then.This technology can disposable generation Silicon-rich SiC
xFilm does not need the plural layers of growing, and technology is simple, easily control; In the inert gas ar gas environment, anneal, can avoid introducing other impurity element; By controlling density and the size that annealing temperature and annealing time are regulated the silicon quantum dot of separating out.
The embodiment of the invention provide based on SiC
xIn the silicon quantum dot floating-gate memory of texture based on SiC
xThe thickness of the silicon quantum dot charge storage layer of texture is that 4nm is to 15nm; Thick charge storage layer comprises more silicon quantum dot, is conducive to realize the High Density Charge storage, reduces the leakage probability of electric charge simultaneously, but can increase the operating voltage of grid; Thin charge storage layer is conducive to improve erasable speed, reduces operating voltage, but is unfavorable for the discrete storage of electric charge, can increase the leakage probability of electric charge.
The embodiment of the invention provide based on SiC
xThe floating boom of the silicon quantum dot floating-gate memory of texture is based on SiC
xThe silicon quantum dot of texture, and silicon quantum dot be mutually independent ground transverse and longitudinal be evenly distributed on SiC
xIn the texture, cross direction profiles can realize the discrete storage to electric charge, and vertically distribution can realize the multilayer storage to electric charge, the silicon quantum dot diameter at 1nm between the 10nm; The density of silicon quantum dot is 1 * 10
11Cm
-2To 1 * 10
13Cm
-2Between.High density, undersized silicon quantum dot are conducive to realize the effective discrete storage of electric charge, but need bigger operating voltage to realize erasable; Because quantum size effect, little density, large-sized silicon quantum dot can make silicon quantum dot-SiC
xPotential barrier between texture reduces, and is conducive to reduce operating voltage, but can weakens the discrete storage effect of electric charge, increases the leakage probability of electric charge.Comprehensive above each side influencing factor is found silicon quantum dot size and density when above scope, the every performance the best of device.
The embodiment of the invention provide based on SiC
xThe control gate oxide layer can be SiO equally in the silicon quantum dot floating-gate memory of texture
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2Deng wherein a kind of; Its thickness is that 6nm is to 30nm.Adopt the control gate oxide layer of high-k to design actual oxidated layer thickness than SiO
2Thick oxide layer obtains and SiO
2Identical electrical thickness (equivalent oxide thickness) can effectively reduce the gate leakage of electric charge, the reliability of enhance device.
Provided by the invention based on SiC
xThe silicon quantum dot floating-gate memory of texture, described control gate oxide layer, based on SiC
xSilicon quantum dot charge storage layer and the tunnel oxide of texture have constituted control gate oxide layer-SiC
xTexture-Si quantum dot-SiC
xThe two ladder potential barrier charge storage structures of texture-tunnel oxide because quantum dot has quantum size effect, can change silicon quantum dot and SiC by changing the silicon quantum dot size
xTunneling barrier height between texture.
Above-mentioned based on SiC
xThe concrete preparation method of the silicon quantum dot floating-gate memory of texture comprises the steps:
(1) the monocrystalline substrate of cleaning form a layer thickness be 2nm to the tunnel oxide of 9nm, the kind of tunnel oxide comprises SiO
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2Deng, adopting process can be thermal oxidation, magnetron sputtering, electron beam evaporation and ald etc.
(2) adopt plasma reinforced chemical vapour deposition (PECVD) technology at the Silicon-rich SiC of tunnel oxide deposition 4nm to 15nm
xLayer, high temperature (900 ℃～1050 ℃) annealing 10min separates out silicon quantum dot to 30min under ar gas environment then;
(3) on the charge storage layer growth one layer thickness at 6nm to the control gate oxide layer between the 30nm, the kind of control gate oxide layer comprises SiO
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2Deng, adopting process can be PECVD, magnetron sputtering, electron beam evaporation and ald etc.;
(4) photoetching forms the grid line figure, successively etching control gate oxide layer, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture and silicon quantum dot) and tunnel oxide; Ion injects, and forms the source conduction region in the grid line both sides and leaks conduction region; The growth insulating oxide, photoetching, corrosion insulating oxide; Evaporation metal grid layer, the metal gate layer thickness is more than 100nm; Peel off and form source metal, leakage and gate electrode.
For illustrate further that the embodiment of the invention provides based on SiC
xThe silicon quantum dot floating-gate memory of texture, it is existing that details are as follows:
Now further describe provided by the invention based on SiC by concrete embodiment
xThe preparation method of the silicon quantum dot floating gate non-volatile memory of texture:
Embodiment 1:
(1) cleans p type single crystal silicon substrate 1;
(2) adopting thermal oxidation technology is the SiO of 2nm at p type single crystal silicon substrate 1 formation one layer thickness of cleaning
2Tunnel layer 4, wherein oxygen flow is 500ml/min, and temperature is 900 ℃, and oxidization time is 2.5min;
(3) pass through plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2Deposition one layer thickness is the Silicon-rich SiC of 4nm on the tunnel layer 4
x Layer 5 wherein feeds CH
4Flow is 20sccm, by H
2The dilution volume ratio is 10% SiH
4Flow is 50sccm, and substrate temperature is 200 ℃, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 10min under ar gas environment, wherein temperature is 900 ℃, and the diameter of separating out silicon quantum dot 6 is about 1nm, and density is about 1 * 10
13Cm
-2
(5) adopt magnetron sputtering technique based on SiC
xDeposition formation thickness is the SiO of 6nm on the silicon quantum dot floating gate charge accumulation layer of texture
2Control gate oxide layer 7, wherein sputtering target material is SiO
2Target, the feeding argon flow amount is 20sccm, and oxygen flow is 10sccm, and substrate temperature is 200 ℃, and power is 120W;
(6) photoetching forms the grid line figure, successively etching control gate oxide layer 7, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture 5 and silicon quantum dot 6) and tunnel oxide 4;
(7) ion injects, and forms source conduction region 3 in the grid line both sides and leaks conduction region 2; The growth insulating oxide, photoetching, corrosion insulating oxide; Evaporating Al grid layer 8, Al grid layer 8 thickness are 1 μ m; Peel off and form Al source, leakage and gate electrode;
(8) annealing in process in argon gas atmosphere makes to form between metal and semiconductor well to contact.
Embodiment 2:
(1) cleans p type single crystal silicon substrate 1;
(2) adopting thermal oxidation technology is the SiO of 2nm at p type single crystal silicon substrate 1 formation one layer thickness of cleaning
2Tunnel layer 4, wherein oxygen flow is 500ml/min, and temperature is 900 ℃, and oxidization time is 2.5min;
(3) pass through plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2Deposition one layer thickness is the Silicon-rich SiC of 10nm on the tunnel layer 4
x Layer 5 wherein feeds CH
4Flow is 20sccm, by H
2The dilution volume ratio is 10% SiH
4Flow is 50sccm, and substrate temperature is 200 ℃, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 20min under ar gas environment, wherein temperature is 1000 ℃, and the diameter of separating out silicon quantum dot 6 is about 4nm, and density is about 1 * 10
12m
-2
(5) adopt magnetron sputtering technique based on SiC
xDeposition formation thickness is the Al of 12nm on the silicon quantum dot floating gate charge accumulation layer of texture
2O
3Gate oxide 7 processed, wherein sputtering target material is the Al target, and the feeding argon flow amount is 20sccm, and oxygen flow is 5sccm, and substrate temperature is 200 ℃, power is 100W;
(6) photoetching forms the grid line figure, successively etching control gate oxide layer 7, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture 5 and silicon quantum dot 6) and tunnel oxide 4;
(7) ion injects, and forms source conduction region 3 in the grid line both sides and leaks conduction region 2; The growth insulating oxide, photoetching, corrosion insulating oxide; Evaporating Al grid layer 8, Al grid layer 8 thickness are 1 μ m; Peel off and form Al source, leakage and gate electrode;
(8) annealing in process in argon gas atmosphere makes to form between metal and semiconductor well to contact.
Embodiment 3:
(1) cleans p type single crystal silicon substrate 1;
(2) adopting magnetron sputtering technique to form a layer thickness at silicon substrate 1 is the Al of 4nm
2O
3Tunnel oxide 4, wherein sputtering target material is the Al target, and the feeding argon flow amount is 20sccm, and oxygen flow is 5sccm, and substrate temperature is 200 ℃, power is 100W;
(3) pass through plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2Deposition one layer thickness is the Silicon-rich SiC of 15nm on the tunnel layer 4
x Layer 5 wherein feeds CH
4Flow is 20sccm, by H
2The dilution volume ratio is 10% SiH
4Flow is 50sccm, and substrate temperature is 200 ℃, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 30min under ar gas environment, wherein temperature is 1000 ℃, and the diameter of separating out silicon quantum dot 6 is about 6nm, and density is about 1 * 10
12m
-2
(5) adopt ald (ALD) technology based on SiC
xDeposition formation thickness is the Al of 12nm on the silicon quantum dot floating gate charge accumulation layer of texture
2O
3Control gate oxide layer 7;
(6) photoetching forms the grid line figure, successively etching control gate oxide layer 7, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture 5 and silicon quantum dot 6) and tunnel oxide 4.
(7) ion injects, and forms source conduction region 3 in the grid line both sides and leaks conduction region 2; The growth insulating oxide, photoetching, corrosion insulating oxide; Evaporating Al grid layer 8, Al grid layer 8 thickness are 1 μ m; Peel off and form Al source, leakage and gate electrode.
(8) annealing in process in argon gas atmosphere makes to form between metal and semiconductor well to contact.
Embodiment 4:
(1) cleans p type single crystal silicon substrate 1;
(2) adopting magnetron sputtering technique to form a layer thickness at silicon substrate is the HfO of 9nm
2Tunnel oxide 4, wherein sputtering target material is HfO
2Target, the feeding argon flow amount is 15sccm, and oxygen flow is 5sccm, and radio-frequency power is 100W, and substrate temperature is 200 ℃;
(3) pass through plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2Deposition one layer thickness is the Silicon-rich SiC of 15nm on the tunnel layer 4
x Layer 5 wherein feeds CH
4Flow is 20sccm, by H
2The dilution volume ratio is 10% SiH
4Flow is 50sccm, and substrate temperature is 200 ℃, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 30min under ar gas environment, wherein temperature is 1000 ℃, and the diameter of separating out silicon quantum dot 6 is about 6nm, and density is about 1 * 10
12m
-2
(5) adopt ald (ALD) technology based on SiC
xDeposition formation thickness is the Al of 12nm on the silicon quantum dot floating gate charge accumulation layer of texture
2O
3Control gate oxide layer 7;
(6) photoetching forms the grid line figure, successively etching control gate oxide layer 7, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture 5 and silicon quantum dot 6) and tunnel oxide 4.
(7) ion injects, and forms source conduction region 3 in the grid line both sides and leaks conduction region 2; The growth insulating oxide, photoetching, corrosion insulating oxide; Evaporating Al grid layer 8, Al grid layer 8 thickness are 1 μ m; Peel off and form Al source, leakage and gate electrode.
(8) annealing in process in argon gas atmosphere makes to form between metal and semiconductor well to contact.
Embodiment 5:
(1) cleans p type single crystal silicon substrate 1;
(2) adopting magnetron sputtering technique to form a layer thickness at silicon substrate is the HfO of 9nm
2Tunnel oxide 4, wherein sputtering target material is HfO
2Target, the feeding argon flow amount is 15sccm, and oxygen flow is 5sccm, and radio-frequency power is 100W, and substrate temperature is 200 ℃;
(3) pass through plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2Deposition one layer thickness is the Silicon-rich SiC of 15nm on the tunnel layer 4
x Layer 5 wherein feeds CH
4Flow is 20sccm, by H
2The dilution volume ratio is 10% SiH
4Flow is 50sccm, and substrate temperature is 200 ℃, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 30min under ar gas environment, wherein temperature is 1050 ℃, and the diameter of separating out silicon quantum dot 6 is about 10nm, and density is about 1 * 10
11Cm
-2
(5) adopt magnetron sputtering technique based on SiC
xDeposition formation thickness is the HfO of 30nm on the silicon quantum dot floating gate charge accumulation layer of texture
2Control gate oxide layer 7,, wherein sputtering target material is HfO
2Target, the feeding argon flow amount is 15sccm, and oxygen flow is 5sccm, and radio-frequency power is 100W, and substrate temperature is 200 ℃;
(6) photoetching forms the grid line figure, successively etching control gate oxide layer 7, based on SiC
xThe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xTexture 5 and silicon quantum dot 6) and tunnel oxide 4.
(7) ion injects, and forms source conduction region 3 in the grid line both sides and leaks conduction region 2; The growth insulating oxide, photoetching, corrosion insulating oxide; Evaporating Al grid layer 8, Al grid layer 8 thickness are 1 μ m; Peel off and form Al source, leakage and gate electrode.
(8) annealing in process in argon gas atmosphere makes to form between metal and semiconductor well to contact.
By above-mentioned preparation method obtain based on SiC
xThe silicon quantum dot floating gate non-volatile memory of texture comprises silicon substrate, leaks conduction region in source that silicon substrate mixes, and the tunnel oxide that between leak in the source, covers successively above the carrier channels, based on SiC
xSilicon quantum dot floating gate charge accumulation layer, control gate oxide layer and the metal gate layer of texture; Effectively utilize silicon quantum dot-SiC
xTunneling barrier between texture has constituted control gate oxide layer-SiC
xTexture-Si quantum dot-SiC
xThe two ladder potential barrier charge storage structures of texture-tunnel oxide.This structure not only can realize the effective discrete storage of electric charge, strengthens charge-retention property, allows device to have thinner tunnel oxide, has accelerated the erasable speed of electric charge to a certain extent.This structure can make the combination property of memory be promoted comprehensively, and further dwindles for size of devices technical support is provided.
Those skilled in the art will readily understand; the above only is preferred embodiment of the present invention; not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. one kind based on SiC
xThe silicon quantum dot floating gate non-volatile semiconductor memory of texture, it is characterized in that, comprise silicon substrate, at source conduction region and the leakage conduction region of silicon substrate doping formation, and tunnel oxide, charge storage layer, control gate oxide layer and the metal gate layer of growing successively on the carrier channels between leak in the source; Described charge storage layer comprises SiC
xTexture and a plurality of transverse and longitudinal are uniformly distributed in SiC
xSilicon quantum dot in the texture has constituted control gate oxide layer-SiC
xTexture-Si quantum dot-SiC
xThe two ladder potential barrier charge storage structures of texture-tunnel oxide.
2. semiconductor memory as claimed in claim 1 is characterized in that, the material of described tunnel oxide is SiO
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2In a kind of, the thickness of described tunnel oxide is 2nm～9nm.
3. semiconductor memory as claimed in claim 1 is characterized in that, the thickness of described charge storage layer is 4nm～15nm.
4. as claim 1 or 3 described semiconductor memories, it is characterized in that described silicon quantum dot diameter is at 1nm～10nm.
5. as claim 1 or 3 or 4 described semiconductor memories, it is characterized in that the density of described silicon quantum dot is 1 * 10
11Cm
-21 * 10
13Cm
-2
6. semiconductor memory as claimed in claim 1 is characterized in that, the material of described control gate oxide layer is SiO
2, Al
2O
3, Y
2O
3, La
2O
5, TiO
2, HfO
2And ZrO
2In a kind of, described control gate thickness of oxide layer is 6nm～30nm.
7. a method for preparing each described semiconductor memory of claim 1-6 is characterized in that, comprises the steps:
S1: the monocrystalline substrate in cleaning forms one deck tunnel oxide;
S2: at tunnel oxide deposition Silicon-rich SiC
xThe layer, under ar gas environment annealing in process and separate out silicon quantum dot after form charge storage layer;
S3: in described charge storage layer growth one deck control gate oxide layer;
S4: described control gate oxide layer, described charge storage layer and described tunnel oxide are carried out photoetching treatment, form source metal electrode, drain electrode and gate electrode.
8. method as claimed in claim 7 is characterized in that, in step S2, adopts plasma reinforced chemical vapour deposition technology at the described Silicon-rich SiC of described tunnel oxide deposition
xLayer, described Silicon-rich SiC
xThe thickness of layer is 4nm～15nm.
9. method as claimed in claim 7 is characterized in that, in step S2, described annealing in process is specially: 10min～30min anneals under 900 ℃～1050 ℃ temperature.
10. method as claimed in claim 7 is characterized in that, step S4 comprises:
S41: the described control gate oxide layer of etching, described charge storage layer and described tunnel oxide and form the grid line figure successively;
S42: ion injects the back and forms the source conduction region in described grid line figure both sides and leak conduction region;
S43: growth insulating oxide and chemical wet etching form source electrode, drain electrode and gate electrode figure;
S44: evaporation thickness is greater than the metal gate layer of 100nm;
S45: peel off source electrode, drain electrode and gate electrode between any two metal and form source metal electrode, drain electrode and gate electrode.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187544A (en) * | 1997-09-12 | 1999-03-30 | Hiroshima Univ | Semiconductor memory device provided with quantum structure |
| US20120313097A1 (en) * | 2005-04-26 | 2012-12-13 | Micron Technology, Inc. | Flash memory device having a graded composition, high dielectric constant gate insulator |
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2013
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1187544A (en) * | 1997-09-12 | 1999-03-30 | Hiroshima Univ | Semiconductor memory device provided with quantum structure |
| US20120313097A1 (en) * | 2005-04-26 | 2012-12-13 | Micron Technology, Inc. | Flash memory device having a graded composition, high dielectric constant gate insulator |
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