CN103346168B - Based on SiC xsilicon quantum dot floating gate non-volatile memory of texture and preparation method thereof - Google Patents
Based on SiC xsilicon quantum dot floating gate non-volatile memory of texture and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a kind of based on SiC
xsilicon quantum dot floating gate non-volatile semiconductor memory of texture and preparation method thereof, comprise silicon substrate, adulterate the conduction region, source that formed and leak conduction region and tunnel oxide, charge storage layer, control gate oxide layer and Metal gate layer that carrier channels between source and drain grows successively on a silicon substrate; Described charge storage layer comprises SiC
xtexture and transverse and longitudinal are uniformly distributed in SiC
xsilicon quantum dot in texture.The present invention effectively utilizes silicon quantum dot-SiC
xtunneling barrier between texture, constitutes control gate oxide layer-SiC
xtexture-Si quantum dot-SiC
xthe two Step hyperbolic crosses charge storage structure of texture-tunnel oxide; Not only can realize the effective discrete storage of electric charge, strengthen charge-retention property, also allow device to have thinner tunnel oxide, accelerate the erasable speed of electric charge, make the combination property of memory obtain General Promotion, and provide technical support for the size of device reduces further.
Description
Technical field
The invention belongs to microelectronics technology, more specifically, relate to a kind of based on SiC
xsilicon quantum dot floating gate non-volatile semiconductor memory of texture and preparation method thereof.
Background technology
Along with the development of information industry and semiconductor integrated circuit, the highly effective and safe of bulk information is stored and obtains one of core technology becoming the information age, extensive nonvolatile memory integrated is the core technology supporting national network communication, high-performance calculation and the Electronic Development of Information Industry such as digital application, consumer electronics, is one of critical bottleneck of the comprehensive Fast-Balance development of whole information industry.How to realize the critical problem that capacity is large, read or write speed is fast, operating voltage is low and reliability is high Mass storage is novel nonvolatile memory.
Traditional floating-gate memory due to the thickness problem of self tunneling medium layer, along with size reduces to be faced with huge challenge gradually.On the one hand, faster read or write speed, more low-work voltage be realized, need tunneling medium layer as far as possible thin; On the other hand, realize high reliability, high-durability, need again Tunnel dielectric as far as possible thick, both are bad takes into account.Along with the deepening continuously of research, nanometer technology develop the continuous appearance with new material, new construction rapidly, be improve semiconductor memory performance, Large Copacity, high-density city are had both in development, and at a high speed, the nonvolatile memory of low-power consumption provides good opportunity.The nanocrystalline nonvolatile storage of novel silicon can realize the discrete storage of electric charge, takes into account high read or write speed, low-work voltage and high data retention characteristics, can solve above contradiction.Silicon nanocrystalline memory has better data retention characteristics compared with conventional floating gate memories; In addition, because the tunnel oxide of silicon nanocrystalline memory can thinner (<5nm), so be more conducive to realizing low operating voltage.But, current silicon nanocrystal nonvolatile memory not yet produces a desired effect, its main cause is that independent silicon nanocrystal easily causes charge leakage for the tunnel oxide that the discrete storage effect of electric charge is obvious and thinner not, causes memory retention performance to be deteriorated.Therefore, study the discrete storage effect how improved electric charge, reduce the charge leakage of tunnel oxide, promote charge retention time, realize again high read or write speed, low voltage operating simultaneously, significant to the development of novel nonvolatile storage.
Preparation method's mainly layer-by-layer growing method of current nano-crystal floating gate charge storage structure, the nano-crystal floating gate that adopts the method to obtain is not obvious for the discrete storage effect of electric charge, and preparation section is loaded down with trivial details, the ability compatible mutually with traditional cmos process.Therefore, along with deepening continuously of scientific research, realize electric charge discrete storage and design new charge storage structure to obtain electric charge height retention performance and fast reading and writing up hill and dale, meet the requirement that device feature size constantly reduces, finding the floating boom preparation method compatible mutually with traditional cmos process is the key developing nano-crystal floating gate nonvolatile memory.
Summary of the invention
For above defect or the Improvement requirement of prior art, the invention provides a kind of based on SiC
xthe silicon quantum dot floating gate non-volatile semiconductor memory of texture, its object is to the performance improving nonvolatile memory, realizes the Mass storage that stored charge density is high, capacity is large, erasable speed is fast, operating voltage is low and reliability is high; Flash, contradictory problems between low-work voltage and long retention time is solved with the effective discrete storage realizing electric charge.
The invention provides a kind of based on SiC
xthe silicon quantum dot floating gate non-volatile semiconductor memory of texture, comprise silicon substrate, adulterate the conduction region, source that formed and leak conduction region and tunnel oxide, charge storage layer, control gate oxide layer and Metal gate layer that carrier channels between source and drain grows successively on a silicon substrate; Described charge storage layer comprises SiC
xtexture and multiple transverse and longitudinal are uniformly distributed in SiC
xsilicon quantum dot in texture.
Further, the material of described tunnel oxide is SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2in one, the thickness of described tunnel oxide is 2nm ~ 9nm.
Further, the thickness of described charge storage layer is 4nm ~ 15nm.
Further, described silicon quantum dot diameter is at 1nm ~ 10nm.
Further, the density of described silicon quantum dot is 1 × 10
11cm
-2~ 1 × 10
13cm
-2.
Further, the material of described control gate oxide layer is SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2in one, the thickness of described control gate oxide layer is 6nm ~ 30nm.
Present invention also offers a kind of method preparing above-mentioned semiconductor memory, comprise the steps:
S1: form the tunnel oxide that a layer thickness is in the monocrystalline substrate of cleaning;
S2: deposit Silicon-rich SiC on tunnel oxide
xlayer, annealing in process under ar gas environment also forms charge storage layer after separating out silicon quantum dot;
S3: grow on described charge storage layer a layer thickness control gate oxide layer;
S4: carry out photoetching treatment to described control gate oxide layer, described charge storage layer and described tunnel oxide, forms metal source, drain electrode and gate electrode.
Further, in step s 2, adopt plasma reinforced chemical vapour deposition technique on described tunnel oxide, deposit described Silicon-rich SiC
xlayer, described Silicon-rich SiC
xthe thickness of layer is 4nm ~ 15nm.
Further, in step s 2, described annealing in process is specially: anneal 10min ~ 30min at the temperature of 900 DEG C ~ 1050 DEG C.
Further, step S4 comprises:
S41: etch described control gate oxide layer, described charge storage layer and described tunnel oxide successively and form grid line figure;
S42: in conduction region, formation source, described grid line figure both sides and leakage conduction region after ion implantation;
S43: grow insulating oxide and chemical wet etching formation source electrode, drain electrode and gate electrode figure;
S44: evaporation thickness is greater than the Metal gate layer of 100nm;
S45: peel off source electrode, drain electrode and gate electrode metal between any two and form metal source, drain electrode and gate electrode.
Charge storage layer of the present invention comprises SiC
xtexture and multiple transverse and longitudinal are uniformly distributed in SiC
xsilicon quantum dot in texture, has two Step hyperbolic crosses charge structure due to it and utilizes the coulomb blockade effect of quantum dot to achieve the effective discrete storage of electric charge, greatly improving charge retention time; In addition, the quantum size effect of quantum dot makes Si quantum dot-SiC
xbetween texture, barrier height is adjustable, is more of value to and solves erasable speed, contradictory problems between operating voltage and charge retention time.
Accompanying drawing explanation
Fig. 1 be the embodiment of the present invention provide based on SiC
xthe cross-sectional view of the silicon quantum dot floating gate non-volatile semiconductor memory of texture;
Fig. 2 be the embodiment of the present invention provide based on SiC
xthe band structure schematic diagram of silicon quantum dot floating gate non-volatile semiconductor memory under flatband conditions of texture.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.In addition, if below in described each execution mode of the present invention involved technical characteristic do not form conflict each other and just can mutually combine.
Fig. 1 show that the embodiment of the present invention provides based on SiC
xthe cross-section structure of the silicon quantum dot floating gate non-volatile semiconductor memory of texture, comprise silicon substrate 1, to adulterate on a silicon substrate the conduction region, source 3 that formed and leak conduction region 2, and at source and the tunnel oxide 4 carrier channels grown successively between leaking, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6), control gate oxide layer 7 and Metal gate layer 8, wherein based on SiC
xthe silicon quantum dot floating boom of (x value is 0 ~ 1) texture take SiC as matrix, and silicon quantum dot is embedded among SiC matrix.Fig. 2 is the band structure schematic diagram of memory provided by the invention under flatband conditions, wherein E
cand E
vbe respectively at the bottom of the conduction band of material and top of valence band, E
ffor Fermi level.Memory provided by the invention utilizes based on SiC
xthe silicon quantum dot of texture as floating boom, because quantum dot has coulomb blockade effect, so the effective discrete storage to electric charge can be realized; Silicon quantum dot 6 be mutually independent ground transverse and longitudinal be evenly distributed on SiC
xin texture 5, be present in Si quantum dot-SiC
xtunneling barrier Φ between texture
2(as shown in Figure 2) effectively prevent the transverse and longitudinal of electric charge to move and charge leakage, enhance charge-retention property; In addition, Si quantum dot-SiC
xtunneling barrier Φ lower between texture
2while realizing the effective discrete storage of electric charge, also do not need to increase operating voltage to make up the impact of this barrier height on the erasable process of electric charge, because the high electric field that erasable voltage produces makes the energy of electric charge be far longer than the height of this potential barrier, can be similar to and think that the motion of electric charge is only subject to Si-tunnel oxide interlayer potential barrier Φ in erasable process
1impact.In electric charge keep-process, as shown in Figure 2, the electric charge of discrete storage will leak back to substrate channel needs through potential barrier Φ
2and Φ
1, and only through potential barrier Φ
1compare, its tunnelling probability reduces greatly, thus reduces the leakage of electric charge, improves charge-retention property; For two ladder tunneling barrier structure, due to Si quantum dot-SiC
xpotential barrier Φ between texture
2existence, device can be allowed to have thinner tunnel oxide 4, thus be conducive to realizing direct tunnelling, greatly accelerate the erasable speed of electric charge; So this memory avoids to sacrifice charge-retention property for cost is to meet the requirement of novel memory devices to more flash and low voltage operating, the size of device can also be made to reduce further simultaneously.Si quantum dot-SiC is regulated by quantum size effect
xbarrier height between texture, can complex optimum device performance further.
The embodiment of the present invention provide based on SiC
xin the silicon quantum dot floating-gate memory of texture, tunnel oxide can be silicon dioxide (SiO
2), aluminium oxide (Al
2o
3), yittrium oxide (Y
2o
3), lanthana (La
2o
5), titanium dioxide (TiO
2), hafnium oxide (HfO
2) and zirconium dioxide (ZrO
2) etc. one wherein; Its thickness can be 2nm to 9nm.Thin tunnel oxide is conducive to the tunnelling probability improving electric charge, and then improves erasable speed and reduce operating voltage; But excessively thin tunnel oxide can increase electric leakage probability, shorten charge retention time.Here the SiO being as thin as 2nm is adopted
2tunnel layer, under the prerequisite that ensure that charge retention time, substantially increases erasable speed and reduces operating voltage; Adopt the tunnel oxide of high-k (as Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2deng), actual oxidated layer thickness comparatively SiO can be designed
2thick tunnel oxide obtains and SiO
2identical electrical thickness (equivalent oxide thickness), thus greatly reduce the Leakage probability of electric charge, effectively improve the retention time of electric charge.
The embodiment of the present invention provide based on SiC
xbased on SiC in the silicon quantum dot floating-gate memory of texture
xthe silicon quantum dot charge storage layer of texture is the SiC first adopting PECVD (PlasmaEnhancedChemicalVaporDeposition, PECVD) process deposits one deck Silicon-rich
xfilm, then under ar gas environment high temperature (900 DEG C ~ 1050 DEG C) annealing (10min ~ 30min) separate out silicon quantum dot formed.This technique can the SiC of disposable generation Silicon-rich
xfilm, do not need to grow plural layers, technique is simple, easily controls; Anneal in inert gas ar gas environment, can avoid introducing other impurity element; Density and the size of the silicon quantum dot of precipitation is regulated by control annealing temperature and annealing time.
The embodiment of the present invention provide based on SiC
xbased on SiC in the silicon quantum dot floating-gate memory of texture
xthe thickness of the silicon quantum dot charge storage layer of texture is 4nm to 15nm; Thick charge storage layer comprises more silicon quantum dot, is conducive to realizing High Density Charge and stores, reduce the Leakage probability of electric charge simultaneously, but can increase the operating voltage of grid; Thin charge storage layer is conducive to improving erasable speed, reduces operating voltage, but is unfavorable for the discrete storage of electric charge, can increase the Leakage probability of electric charge.
The embodiment of the present invention provide based on SiC
xthe floating boom of the silicon quantum dot floating-gate memory of texture is based on SiC
xthe silicon quantum dot of texture, and silicon quantum dot is mutually independent, ground transverse and longitudinal is evenly distributed on SiC
xin texture, cross direction profiles can realize the discrete storage to electric charge, and genesis analysis can realize the multilayered memory to electric charge, and silicon quantum dot diameter is between 1nm to 10nm; The density of silicon quantum dot is 1 × 10
11cm
-2to 1 × 10
13cm
-2between.High density, undersized silicon quantum dot are conducive to realizing the effective discrete storage of electric charge, but need larger operating voltage to realize erasable; Due to quantum size effect, little density, large-sized silicon quantum dot can make silicon quantum dot-SiC
xpotential barrier between texture reduces, and is conducive to reducing operating voltage, but can weaken the discrete storage effect of electric charge, increases the Leakage probability of electric charge.Comprehensive above each side influencing factor, find that silicon quantum dot size and density are when above scope, device properties is best.
The embodiment of the present invention provide based on SiC
xin the silicon quantum dot floating-gate memory of texture, control gate oxide layer can be SiO equally
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2deng wherein a kind of; Its thickness is 6nm to 30nm.The control gate oxide layer of high-k is adopted to design actual oxidated layer thickness comparatively SiO
2thick oxide layer, obtains and SiO
2identical electrical thickness (equivalent oxide thickness), effectively can reduce the gate leakage of electric charge, the reliability of enhance device.
Provided by the invention based on SiC
xthe silicon quantum dot floating-gate memory of texture, described control gate oxide layer, based on SiC
xthe silicon quantum dot charge storage layer of texture and tunnel oxide constitute control gate oxide layer-SiC
xtexture-Si quantum dot-SiC
xthe two Step hyperbolic crosses charge storage structure of texture-tunnel oxide, because quantum dot has quantum size effect, changes silicon quantum dot and SiC by changing silicon quantum dot size
xtunneling barrier height between texture.
Above-mentioned based on SiC
xthe concrete preparation method of the silicon quantum dot floating-gate memory of texture comprises the steps:
(1) in the monocrystalline substrate of cleaning, form the tunnel oxide that a layer thickness is 2nm to 9nm, the kind of tunnel oxide comprises SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2deng, adopt technique can be thermal oxidation, magnetron sputtering, electron beam evaporation and ald etc.
(2) adopt plasma reinforced chemical vapour deposition (PECVD) technology on tunnel oxide, deposit the Silicon-rich SiC of 4nm to 15nm
xlayer, then under ar gas environment, high temperature (900 DEG C ~ 1050 DEG C) annealing 10min to 30min separates out silicon quantum dot;
(3) charge storage layer grows the control gate oxide layer of a layer thickness between 6nm to 30nm, the kind of control gate oxide layer comprises SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2deng, adopt technique can be PECVD, magnetron sputtering, electron beam evaporation and ald etc.;
(4) photoetching forms grid line figure, etches control gate oxide layer successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture and silicon quantum dot) and tunnel oxide; Ion implantation, in conduction region, formation source, grid line both sides and leakage conduction region; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporation metal gate layer, Metal gate layer thickness is at more than 100nm; Peel off and form source metal, leakage and gate electrode.
In order to the further description embodiment of the present invention provide based on SiC
xthe silicon quantum dot floating-gate memory of texture, it is existing that details are as follows:
The monocrystalline substrate 1 of cleaning forms tunnel oxide 4, and the kind of tunnel oxide 4 comprises SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2deng; Adopt technique can be thermal oxidation, magnetron sputtering, electron beam evaporation and ald etc.; The thickness of tunnel oxide 4 is between 2nm to 9nm.Tunnel oxide 4 is formed based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6); Using plasma strengthens the SiC that chemical vapour deposition (CVD) (PECVD) technology deposits Silicon-rich on tunnel oxide 4
xlayer 5, then adopts high temperature (900 DEG C ~ 1050 DEG C) annealing (10min ~ 30min) technique to separate out silicon quantum dot 6; Silicon quantum dot 6 independently of one another transverse and longitudinal is evenly distributed on SiC
xin texture 5; Silicon quantum dot 6 diameter is between 1nm to 10nm; The density of silicon quantum dot is 1 × 10
11cm
-2to 1 × 10
13cm
-2between; Based on SiC
xthe silicon quantum dot charge storage layer thickness of texture is 4nm to 15nm.Based on SiC
xthe silicon quantum dot charge storage layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) upper formation control gate oxide 7, the kind of control gate oxide layer 7 comprises SiO equally
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2deng; Adopt technique can be PECVD, magnetron sputtering, electron beam evaporation and ald etc.; The thickness of control gate oxide layer 7 is between 6nm to 30nm.Then, photoetching forms grid line figure, etches control gate oxide layer 7 successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) and tunnel oxide 4; Ion implantation, in conduction region, formation source, grid line both sides 3 and leakage conduction region 2; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporation metal gate layer 8, Metal gate layer 8 thickness is at more than 100nm; Peel off and form source metal, leakage and gate electrode.
Now further describe provided by the invention based on SiC by concrete embodiment
xthe preparation method of the silicon quantum dot floating gate non-volatile memory of texture:
Embodiment 1:
(1) p type single crystal silicon substrate 1 is cleaned;
(2) thermal oxidation technology is adopted to form the SiO that a layer thickness is 2nm on the p type single crystal silicon substrate 1 of cleaning
2tunnel layer 4, wherein oxygen flow is 500ml/min, and temperature is 900 DEG C, and oxidization time is 2.5min;
(3) by plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2tunnel layer 4 deposits the Silicon-rich SiC that a layer thickness is 4nm
xlayer 5, wherein passes into CH
4flow is 20sccm, by H
2dilution volume ratio is the SiH of 10%
4flow is 50sccm, and substrate temperature is 200 DEG C, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 10min under ar gas environment, wherein temperature is 900 DEG C, and the diameter of separating out silicon quantum dot 6 is about 1nm, and density is about 1 × 10
13cm
-2;
(5) adopt magnetron sputtering technique based on SiC
xin the silicon quantum dot floating gate charge accumulation layer of texture, deposition forms thickness is the SiO of 6nm
2control gate oxide layer 7, wherein sputtering target material is SiO
2target, passing into argon flow amount is 20sccm, and oxygen flow is 10sccm, and substrate temperature is 200 DEG C, and power is 120W;
(6) photoetching, forms grid line figure, etches control gate oxide layer 7 successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) and tunnel oxide 4;
(7) ion implantation, in conduction region, formation source, grid line both sides 3 and leakage conduction region 2; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporating Al gate layer 8, Al gate layer 8 thickness is 1 μm; Peel off and form Al source, leakage and gate electrode;
(8) annealing in process in argon gas atmosphere, makes to form good contact between metal and semiconductor.
Embodiment 2:
(1) p type single crystal silicon substrate 1 is cleaned;
(2) thermal oxidation technology is adopted to form the SiO that a layer thickness is 2nm on the p type single crystal silicon substrate 1 of cleaning
2tunnel layer 4, wherein oxygen flow is 500ml/min, and temperature is 900 DEG C, and oxidization time is 2.5min;
(3) by plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2tunnel layer 4 deposits the Silicon-rich SiC that a layer thickness is 10nm
xlayer 5, wherein passes into CH
4flow is 20sccm, by H
2dilution volume ratio is the SiH of 10%
4flow is 50sccm, and substrate temperature is 200 DEG C, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 20min under ar gas environment, wherein temperature is 1000 DEG C, and the diameter of separating out silicon quantum dot 6 is about 4nm, and density is about 1 × 10
12m
-2;
(5) adopt magnetron sputtering technique based on SiC
xin the silicon quantum dot floating gate charge accumulation layer of texture, deposition forms thickness is the Al of 12nm
2o
3gate oxide 7 processed, wherein sputtering target material is Al target, and passing into argon flow amount is 20sccm, and oxygen flow is 5sccm, and substrate temperature is 200 DEG C, and power is 100W;
(6) photoetching, forms grid line figure, etches control gate oxide layer 7 successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) and tunnel oxide 4;
(7) ion implantation, in conduction region, formation source, grid line both sides 3 and leakage conduction region 2; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporating Al gate layer 8, Al gate layer 8 thickness is 1 μm; Peel off and form Al source, leakage and gate electrode;
(8) annealing in process in argon gas atmosphere, makes to form good contact between metal and semiconductor.
Embodiment 3:
(1) p type single crystal silicon substrate 1 is cleaned;
(2) adopt magnetron sputtering technique on silicon substrate 1, form the Al that a layer thickness is 4nm
2o
3tunnel oxide 4, wherein sputtering target material is Al target, and passing into argon flow amount is 20sccm, and oxygen flow is 5sccm, and substrate temperature is 200 DEG C, and power is 100W;
(3) by plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2tunnel layer 4 deposits the Silicon-rich SiC that a layer thickness is 15nm
xlayer 5, wherein passes into CH
4flow is 20sccm, by H
2dilution volume ratio is the SiH of 10%
4flow is 50sccm, and substrate temperature is 200 DEG C, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 30min under ar gas environment, wherein temperature is 1000 DEG C, and the diameter of separating out silicon quantum dot 6 is about 6nm, and density is about 1 × 10
12m
-2;
(5) adopt ald (ALD) technology based on SiC
xin the silicon quantum dot floating gate charge accumulation layer of texture, deposition forms thickness is the Al of 12nm
2o
3control gate oxide layer 7;
(6) photoetching, forms grid line figure, etches control gate oxide layer 7 successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) and tunnel oxide 4.
(7) ion implantation, in conduction region, formation source, grid line both sides 3 and leakage conduction region 2; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporating Al gate layer 8, Al gate layer 8 thickness is 1 μm; Peel off and form Al source, leakage and gate electrode.
(8) annealing in process in argon gas atmosphere, makes to form good contact between metal and semiconductor.
Embodiment 4:
(1) p type single crystal silicon substrate 1 is cleaned;
(2) magnetron sputtering technique is adopted to form the HfO that a layer thickness is 9nm on a silicon substrate
2tunnel oxide 4, wherein sputtering target material is HfO
2target, passing into argon flow amount is 15sccm, and oxygen flow is 5sccm, and radio-frequency power is 100W, and substrate temperature is 200 DEG C;
(3) by plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2tunnel layer 4 deposits the Silicon-rich SiC that a layer thickness is 15nm
xlayer 5, wherein passes into CH
4flow is 20sccm, by H
2dilution volume ratio is the SiH of 10%
4flow is 50sccm, and substrate temperature is 200 DEG C, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 30min under ar gas environment, wherein temperature is 1000 DEG C, and the diameter of separating out silicon quantum dot 6 is about 6nm, and density is about 1 × 10
12m
-2;
(5) adopt ald (ALD) technology based on SiC
xin the silicon quantum dot floating gate charge accumulation layer of texture, deposition forms thickness is the Al of 12nm
2o
3control gate oxide layer 7;
(6) photoetching, forms grid line figure, etches control gate oxide layer 7 successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) and tunnel oxide 4.
(7) ion implantation, in conduction region, formation source, grid line both sides 3 and leakage conduction region 2; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporating Al gate layer 8, Al gate layer 8 thickness is 1 μm; Peel off and form Al source, leakage and gate electrode.
(8) annealing in process in argon gas atmosphere, makes to form good contact between metal and semiconductor.
Embodiment 5:
(1) p type single crystal silicon substrate 1 is cleaned;
(2) magnetron sputtering technique is adopted to form the HfO that a layer thickness is 9nm on a silicon substrate
2tunnel oxide 4, wherein sputtering target material is HfO
2target, passing into argon flow amount is 15sccm, and oxygen flow is 5sccm, and radio-frequency power is 100W, and substrate temperature is 200 DEG C;
(3) by plasma enhanced chemical vapor deposition (PECVD) technology at SiO
2tunnel layer 4 deposits the Silicon-rich SiC that a layer thickness is 15nm
xlayer 5, wherein passes into CH
4flow is 20sccm, by H
2dilution volume ratio is the SiH of 10%
4flow is 50sccm, and substrate temperature is 200 DEG C, and radio-frequency power is 100W, and cavity air pressure is 0.8Torr;
(4) high annealing 30min under ar gas environment, wherein temperature is 1050 DEG C, and the diameter of separating out silicon quantum dot 6 is about 10nm, and density is about 1 × 10
11cm
-2;
(5) adopt magnetron sputtering technique based on SiC
xin the silicon quantum dot floating gate charge accumulation layer of texture, deposition forms thickness is the HfO of 30nm
2control gate oxide layer 7, wherein sputtering target material is HfO
2target, passing into argon flow amount is 15sccm, and oxygen flow is 5sccm, and radio-frequency power is 100W, and substrate temperature is 200 DEG C;
(6) photoetching, forms grid line figure, etches control gate oxide layer 7 successively, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture (comprises SiC
xtexture 5 and silicon quantum dot 6) and tunnel oxide 4.
(7) ion implantation, in conduction region, formation source, grid line both sides 3 and leakage conduction region 2; Growth insulating oxide, photoetching, etching insulative oxide layer; Evaporating Al gate layer 8, Al gate layer 8 thickness is 1 μm; Peel off and form Al source, leakage and gate electrode.
(8) annealing in process in argon gas atmosphere, makes to form good contact between metal and semiconductor.
By above-mentioned preparation method obtain based on SiC
xthe silicon quantum dot floating gate non-volatile memory of texture comprises silicon substrate, the source and drain conduction region of adulterating on a silicon substrate, and the tunnel oxide covered successively above carrier channels between source and drain, based on SiC
xthe silicon quantum dot floating gate charge accumulation layer of texture, control gate oxide layer and Metal gate layer; Effectively utilize silicon quantum dot-SiC
xtunneling barrier between texture, constitutes control gate oxide layer-SiC
xtexture-Si quantum dot-SiC
xthe two Step hyperbolic crosses charge storage structure of texture-tunnel oxide.This structure not only can realize the effective discrete storage of electric charge, strengthens charge-retention property, allows device to have thinner tunnel oxide, accelerates the erasable speed of electric charge to a certain extent.This structure can make the combination property of memory obtain General Promotion, and provides technical support for the size of device reduces further.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present invention; not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. one kind based on SiC
xthe silicon quantum dot floating gate non-volatile semiconductor memory of texture, it is characterized in that, comprise silicon substrate, adulterate the conduction region, source that formed and leak conduction region and tunnel oxide, charge storage layer, control gate oxide layer and Metal gate layer that carrier channels between source and drain grows successively on a silicon substrate; Described charge storage layer comprises SiC
xtexture and multiple transverse and longitudinal are uniformly distributed in SiC
xsilicon quantum dot in texture, constitutes control gate oxide layer-SiC
xtexture-Si quantum dot-SiC
xthe two Step hyperbolic crosses charge storage structure of texture-tunnel oxide;
The material of described tunnel oxide is SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2in one, the thickness of described tunnel oxide is 2nm ~ 9nm;
The material of described control gate oxide layer is SiO
2, Al
2o
3, Y
2o
3, La
2o
5, TiO
2, HfO
2and ZrO
2in one, the thickness of described control gate oxide layer is 6nm ~ 30nm.
2. semiconductor memory as claimed in claim 1, it is characterized in that, the thickness of described charge storage layer is 4nm ~ 15nm.
3. semiconductor memory as claimed in claim 1, it is characterized in that, described silicon quantum dot diameter is at 1nm ~ 10nm.
4. semiconductor memory as claimed in claim 1, it is characterized in that, the density of described silicon quantum dot is 1 × 10
11cm
-2~ 1 × 10
13cm
-2.
5. prepare a method for the semiconductor memory described in any one of claim 1-4, it is characterized in that, comprise the steps:
S1: form one deck tunnel oxide in the monocrystalline substrate of cleaning;
S2: deposit Silicon-rich SiC on tunnel oxide
xlayer, annealing in process under ar gas environment also forms charge storage layer after separating out silicon quantum dot;
S3: grow one deck control gate oxide layer on described charge storage layer;
S4: carry out photoetching treatment to described control gate oxide layer, described charge storage layer and described tunnel oxide, forms metal source, drain electrode and gate electrode.
6. method as claimed in claim 5, is characterized in that, in step s 2, adopts plasma reinforced chemical vapour deposition technique on described tunnel oxide, deposit described Silicon-rich SiC
xlayer, described Silicon-rich SiC
xthe thickness of layer is 4nm ~ 15nm.
7. method as claimed in claim 5, it is characterized in that, in step s 2, described annealing in process is specially: anneal 10min ~ 30min at the temperature of 900 DEG C ~ 1050 DEG C.
8. method as claimed in claim 5, it is characterized in that, step S4 comprises:
S41: etch described control gate oxide layer, described charge storage layer and described tunnel oxide successively and form grid line figure;
S42: in conduction region, formation source, described grid line figure both sides and leakage conduction region after ion implantation;
S43: grow insulating oxide and chemical wet etching formation source electrode, drain electrode and gate electrode figure;
S44: evaporation thickness is greater than the Metal gate layer of 100nm;
S45: peel off source electrode, drain electrode and gate electrode metal between any two and form metal source, drain electrode and gate electrode.
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| Publication number | Priority date | Publication date | Assignee | Title |
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