CN103346159A - Array substrate, manufacturing method thereof and display device thereof - Google Patents
Array substrate, manufacturing method thereof and display device thereof Download PDFInfo
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- CN103346159A CN103346159A CN2013102693221A CN201310269322A CN103346159A CN 103346159 A CN103346159 A CN 103346159A CN 2013102693221 A CN2013102693221 A CN 2013102693221A CN 201310269322 A CN201310269322 A CN 201310269322A CN 103346159 A CN103346159 A CN 103346159A
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- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 238000002161 passivation Methods 0.000 claims abstract description 55
- 238000005516 engineering process Methods 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 23
- 239000012212 insulator Substances 0.000 claims description 19
- 239000000203 mixture Substances 0.000 claims description 18
- 230000005540 biological transmission Effects 0.000 claims description 14
- 239000010409 thin film Substances 0.000 claims description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 25
- 239000010410 layer Substances 0.000 description 65
- 238000005530 etching Methods 0.000 description 16
- 239000004973 liquid crystal related substance Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010849 ion bombardment Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 230000003760 hair shine Effects 0.000 description 3
- 210000001503 joint Anatomy 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical group 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- Thin Film Transistor (AREA)
Abstract
The invention discloses an array substrate, a manufacturing method of the array substrate and a display device of the array substrate, and relates to the technical field of display. The array substrate is used for avoiding the light leakage phenomenon of a display panel, therefore, the quality of the display panel is improved, and the display effect is improved. The array substrate comprises a transparent substrate and a TFT located on the transparent substrate. A first passivation layer covers the TFT. A first transparent electrode is located on the surface of the first passivation layer. The first transparent electrode is connected with a drain electrode of the TFT through a via hole. A light resistance structure used for preventing light from transmitting is arranged at the position of the via hole.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of array base palte and manufacture method thereof, display unit.
Background technology
Develop rapidly along with Display Technique, TFT-LCD (Thin Film Transistor Liquid Crystal Display, Thin Film Transistor-LCD) as a kind of panel display apparatus, because it has characteristics such as little, low in energy consumption, the radiationless and cost of manufacture of volume is relatively low, and be applied to more and more in the middle of the high-performance demonstration field.
The manufacturing process of TFT-LCD display floater comprises: manufacturing array (Array) substrate and color film (Color Filter) substrate, and then array base palte carried out contraposition with color membrane substrates, becomes box (Cell).As shown in Figure 1, typical tft array substrate comprises transparency carrier 11 and is positioned at grid 120, gate insulator 13, the active layer 14 of TFT on the transparency carrier surface, the drain electrode 121 of TFT that is positioned at active layer 14 both sides and the source class 122 of TFT, second transparency electrode 18 that is positioned at active layer 14, TFT drain electrode 121 and TFT source class 122 lip-deep first passivation layers 15, is positioned at the first planar transparency electrode 16 of first passivation layer surface and is formed at first transparency electrode, 16 lip-deep second passivation layers 17 and narrow slit structure successively successively.
For with drain electrode 121 conductings of first transparency electrode 16 with thin-film transistor, can be provided with via hole on the surface of first passivation layer 15 usually, and consider the factor of pixel aperture ratio, can this via hole be set to half lap scarf joint via hole 30 as shown in Figure 1.The part of first transparency electrode 16 on these half lap scarf joint via hole 30 surfaces is overlapped on the surface of drain electrode 121 of TFT, and another part is overlapped on the surface of via hole 30 bottom grid insulating barriers 13, adopts a kind of like this via hole can increase pixel aperture ratio.Yet, because first transparency electrode, 16 printing opacities, so at half lap scarf joint via hole 21 places, when the light that sends when backlight shines the drain electrode 121 unlapped parts of TFT, will produce light leakage phenomena.In addition, also the reason owing to foozle can cause the bore of this via hole bigger than normal in design load, perhaps when array base palte and color membrane substrates carry out contraposition and become box, because the restriction of aligning accuracy, be easy to skew occur, cause via hole not cover fully, thereby the phenomenon of light leak takes place, this light leakage phenomena has seriously restricted the quality of liquid crystal panel, and has reduced the display effect of liquid crystal display device.
Summary of the invention
Embodiments of the invention provide a kind of array base palte and manufacture method thereof, display unit, in order to avoiding the light leakage phenomena of display floater, thereby improve the quality of display floater, promote display effect.
For achieving the above object, embodiments of the invention adopt following technical scheme:
The one side of the embodiment of the invention, a kind of array base palte is provided, comprise: transparency carrier and be positioned at thin-film transistor TFT on the described transparency carrier, first passivation layer covers described TFT, first transparency electrode is positioned at the surface of described first passivation layer, described first transparency electrode is connected with the drain electrode of described TFT by via hole, and described via hole place has be used to the light resistance structure that prevents the light transmission.
The embodiment of the invention provides a kind of display unit on the other hand, comprises the array base palte of as above telling.
The another aspect of the embodiment of the invention provides a kind of manufacture method of array base palte, comprising:
Form the pattern of first passivation layer at the substrate surface that is formed with thin-film transistor TFT;
At the pattern of the substrate surface that is formed with above-mentioned pattern by composition technology formation via hole, first transparency electrode is connected with the drain electrode of described TFT by described via hole;
Be formed for preventing the light resistance structure of light transmission in described via hole position.
The embodiment of the invention provides a kind of array base palte and manufacture method thereof, display unit, this array base palte comprises: transparency carrier and be positioned at thin-film transistor TFT on the transparency carrier, first passivation layer covers TFT, first transparency electrode is positioned at the surface of first passivation layer, this first transparency electrode is connected with the drain electrode of TFT by via hole, and this via hole place has be used to the light resistance structure that prevents the light transmission.So, can avoid the light leakage phenomena of display floater by this light resistance structure, thereby improve the quality of display floater, promote display effect.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is array base-plate structure schematic diagram of the prior art;
A kind of array base-plate structure schematic diagram that Fig. 2 provides for the embodiment of the invention;
The another kind of array base-plate structure schematic diagram that Fig. 3 provides for the embodiment of the invention;
The another kind of array base-plate structure schematic diagram that Fig. 4 provides for the embodiment of the invention;
Another array base-plate structure schematic diagram that Fig. 5 provides for the embodiment of the invention.
Another array base-plate structure schematic diagram that Fig. 6 provides for the embodiment of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
A kind of array base palte, as shown in Figure 2, can comprise: transparency carrier 11 and be positioned at thin-film transistor TFT12 on the transparency carrier 11, first passivation layer 15 covers this TFT12, first transparency electrode 16 is positioned at the surface of first passivation layer 15, first transparency electrode 16 is connected with the drain electrode 121 of TFT by via hole 20, and via hole 20 places have be used to the light resistance structure 21 that prevents the light transmission.
The embodiment of the invention provides a kind of array base palte, by make being used for preventing the light resistance structure of light transmission in the via hole position, thereby can effectively avoid in the prior art via hole owing to not covering the light leakage phenomena that produces fully.So, significantly improve the quality of display floater, promoted the display effect of display unit.
Further, as shown in Figure 2, light resistance structure 21 is specifically as follows continuous a plurality of inclined-planes or the micro-structural of curved surface.
Need to prove that above-mentioned continuous a plurality of inclined-planes or the micro-structural of curved surface are specifically as follows zigzag or rough irregularly shaped etc.Wherein, the embodiment of the invention all be with jagged irregularly shaped be the explanation that example is carried out.
So, when the light that sends when backlight shines the drain electrode 121 unlapped parts of this via hole 20 TFT of place, having jagged erose light resistance structure 21 by the surface is scattered incident ray, reduced the light that sees through these via hole 20 places, thereby avoided the light leakage phenomena of display device, improved the display effect of display device.
Further, as shown in Figure 2, first passivation layer 15 that is positioned at via hole 20 places has this micro-structural, and the surface of first passivation layer 15 forms first transparency electrode 16 with this micro-structural.Concrete, the jagged irregularly shaped of composition technology formation passed through on the surface that is positioned at first passivation layer 15 at via hole 20 places.For example, adopt mask exposure technology, again etching is carried out on the surface of first passivation layer 15 at via hole 20 places, the control etching depth, first passivation layer that keeps a part, make first transparency electrode 16 at the substrate that forms above structure then, form the surface and have jagged erose light resistance structure 21.So this light resistance structure 21 can play the effect that prevents ray cast, avoids the light leakage phenomena of display floater, thereby improves the quality of display floater, promotes display effect.
Further, as shown in Figure 3, the drain electrode 121 that is positioned at the TFT at via hole 20 places has this micro-structural, and the surface of the drain electrode 121 of TFT forms first transparency electrode 16 with this micro-structural.Concrete, be positioned at via hole 20 places TFT drain electrode 121 the surface by composition technology form jagged irregularly shaped.For example, adopt mask exposure technology, again etching is carried out on the surface of the drain electrode 121 of the TFT at via hole 20 places, the control etching depth, keep the drain electrode 121 of a part of TFT, make first transparency electrode 16 at the substrate that forms above structure then, form the surface and have jagged erose light resistance structure 21.So this light resistance structure 21 can play the effect that prevents ray cast, avoids the light leakage phenomena of display floater, thereby improves the quality of display floater, promotes display effect.
Further, as shown in Figure 4, have this micro-structural at first passivation layer 15 at via hole 20 places and the gate insulator 13 between the transparency carrier 11, the surface of gate insulator 13 forms first transparency electrode 16 with this micro-structural.Concrete, the jagged irregularly shaped of composition technology formation passed through on the surface that is positioned at the gate insulator 13 at via hole 20 places.For example, adopt mask exposure technology, again etching is carried out on the surface of the gate insulator 13 at via hole 20 places, the control etching depth, keep a part of gate insulator 13, make first transparency electrode 16 at the substrate that forms above structure then, form the surface and have jagged erose light resistance structure 21.So this light resistance structure 21 can play the effect that prevents ray cast, avoids the light leakage phenomena of display floater, thereby improves the quality of display floater, promotes display effect.
Certainly; above-mentioned only is that to be example with Fig. 2, Fig. 3, Fig. 4 be described the pattern of light resistance structure; other patterns that are formed for preventing the light resistance structure 21 of light transmission in via hole 20 positions are here given unnecessary details no longer one by one, but all should belong to protection scope of the present invention.
Need to prove, be formed at second passivation layer 17 on first transparency electrode, 16 surfaces.
The surface of second passivation layer 17 is formed with second transparency electrode 18.
Concrete, first transparency electrode 16 can be planar structure, second transparency electrode 18 can be the narrow slit structure of space; Or first transparency electrode 16 can be the narrow slit structure of space, and second transparency electrode 18 can be planar structure; Or first transparency electrode 16 and second transparency electrode 18 all can be narrow slit structure.
For example, the array base palte that the embodiment of the invention provides goes for FFS (Fringe Field Switching, fringe field switching) type or AD-SDS (Advanced-Super Dimensional Switching, abbreviate ADS as, senior super dimension field switch) production of the liquid crystal indicator of type such as type.The electrode that is the narrow slit structure that arranges at interval with first transparency electrode 16 and second transparency electrode 18 is example, a kind of like this array base palte of structure is often used as the production of ADS type liquid crystal indicator, the longitudinal electric field that the parallel electric field that the ADS technology produces by pixel electrode edge in the same plane and pixel electrode layer and public electrode interlayer produce forms multi-dimensional electric field, make between the interior pixel electrode of liquid crystal cell, all aligned liquid-crystal molecules can both produce the rotation conversion directly over the electrode, compare with the display unit of other types, ADS type liquid crystal indicator has further improved planar orientation to be the liquid crystal operating efficiency and to have increased light transmission efficiency.
Need to prove that in embodiments of the present invention, first transparency electrode 16 can be pixel electrode, second transparency electrode 18 can be public electrode; Perhaps first transparency electrode 16 can be public electrode, and second transparency electrode 18 can be pixel electrode.The present invention is not restricted this.
Need to prove that in the present invention, composition technology can include only photoetching process, or, comprising photoetching process and etch step, other are used to form the technology of predetermined pattern can also to comprise printing, ink-jet etc. simultaneously; Photoetching process refers to that utilize photoresist, mask plate, the exposure machine etc. that comprise technical processs such as film forming, exposure, development form the technology of figure.The corresponding composition technology of formed structure choice in can be according to the present invention.For example, can carry out ion bombardment etching to the substrate that is formed with via hole 20, carry out ashing photoresist and ion bombardment etching again, can obtain surface, via hole 20 place and have erose light resistance structure 21, maybe can be with its surface roughening.
Adopt above-mentioned a kind of like this array base palte, light resistance structure 21 specifically is the light reflection structure that is formed by first passivation layer 15 and first transparency electrode 16, so, by changing the design that shape that the existing layer level structure is positioned at via hole 20 places can realize light resistance structure, thereby need not additionally to arrange new level, effectively guaranteed the thickness of display unit.
Further, light resistance structure 21 comprises light shield layer 22:
As shown in Figure 5, light shield layer 22 is between first transparency electrode 16 and second passivation layer 17.
Further, as shown in Figure 6, via hole 20 places had not only had the surface for erose light resistance structure 21 but also had had light shield layer 22 between first transparency electrode and first passivation layer, so can better play and prevent that light from seeing through the effect of this via hole, thereby the more effective light leakage phenomena of avoiding display floater has improved the display effect of display device.Need to prove; here only be that to be example with Fig. 6 have the explanation that the structure of jagged light resistance structure and light shield layer is carried out simultaneously to via hole 20 places; other is here given unnecessary details no longer one by one in the structure that via hole 20 places have jagged light resistance structure and light shield layer simultaneously, but all should belong within the protection range of the embodiment of the invention.
Embodiments of the invention provide a kind of display unit, comprise aforesaid any one array base palte.This display unit is specifically as follows any liquid crystal display product or parts with Presentation Function such as LCD, LCD TV, DPF, mobile phone, panel computer.
The embodiment of the invention provides a kind of display unit, this display unit comprises array base palte, this array base palte comprises: transparency carrier and be positioned at thin-film transistor TFT on the transparency carrier, first passivation layer covers TFT, first transparency electrode is positioned at the surface of first passivation layer, this first transparency electrode is connected with the drain electrode of TFT by via hole, and this via hole place has be used to the light resistance structure that prevents the light transmission.So, can avoid the light leakage phenomena of display floater by this light resistance structure, thereby improve the quality of display floater, promote display effect.
The embodiment of the invention provides a kind of manufacture method of array base palte, as shown in Figure 2, comprising:
S101, form the pattern of first passivation layer 15 at the substrate surface that is formed with thin-film transistor TFT12.
S102, form the pattern of via hole 20 at the substrate surface that is formed with above-mentioned pattern by composition technology, first transparency electrode 16 is connected with the drain electrode 121 of TFT by this via hole 20.
S103, be formed for preventing the light resistance structure 21 of light transmission in via hole 20 positions.
The embodiment of the invention provides a kind of manufacture method of array base palte, this array base palte comprises: transparency carrier and be positioned at thin-film transistor TFT on the transparency carrier, first passivation layer covers TFT, first transparency electrode is positioned at the surface of first passivation layer, this first transparency electrode is connected with the drain electrode of TFT by via hole, and this via hole place has be used to the light resistance structure that prevents the light transmission.So, can avoid the light leakage phenomena of display floater by this light resistance structure, thereby improve the quality of display floater, promote display effect.
Further, as shown in Figure 2, the manufacture method of light resistance structure 21 comprises:
S201, on the substrate that is formed with via hole 20, form first passivation layer 15 and first transparency electrode 16 successively.
Wherein, this via hole place forms the light resistance structure 21 that the surface has the micro-structural of continuous a plurality of inclined-planes or curved surface by composition technology.
Need to prove that above-mentioned continuous a plurality of inclined-planes or the micro-structural of curved surface are specifically as follows zigzag or rough irregularly shaped etc.Wherein, the embodiment of the invention all be with jagged irregularly shaped be the explanation that example is carried out.
So, when the light that sends when backlight shines the drain electrode 121 unlapped parts of this via hole 20 TFT of place, the light resistance structure 21 that has this micro-structural by the surface is scattered incident ray, reduced the light that sees through these via hole 20 places, thereby avoided the light leakage phenomena of display device, improved the display effect of display device.
Further, as shown in Figure 2, first passivation layer 15 that is positioned at via hole 20 places has this micro-structural, and the surface of first passivation layer 15 forms first transparency electrode 16 with this micro-structural.Concrete, the jagged irregularly shaped of composition technology formation passed through on the surface that is positioned at first passivation layer 15 at via hole 20 places.For example, adopt mask exposure technology, again etching is carried out on the surface of first passivation layer 15 at via hole 20 places, the control etching depth, first passivation layer that keeps a part, make first transparency electrode 16 at the substrate that forms above structure then, form the surface and have jagged erose light resistance structure 21.So this light resistance structure 21 can play the effect that prevents ray cast, avoids the light leakage phenomena of display floater, thereby improves the quality of display floater, promotes display effect.
Further, as shown in Figure 3, the drain electrode 121 that is positioned at the TFT at via hole 20 places has this micro-structural, and the surface of the drain electrode 121 of TFT forms first transparency electrode 16 with this micro-structural.Concrete, be positioned at via hole 20 places TFT drain electrode 121 the surface by composition technology form jagged irregularly shaped.For example, adopt mask exposure technology, again etching is carried out on the surface of the drain electrode 121 of the TFT at via hole 20 places, the control etching depth, keep the drain electrode 121 of a part of TFT, make first transparency electrode 16 at the substrate that forms above structure then, form the surface and have jagged erose light resistance structure 21.So this light resistance structure 21 can play the effect that prevents ray cast, avoids the light leakage phenomena of display floater, thereby improves the quality of display floater, promotes display effect.
Further, as shown in Figure 4, have this micro-structural at first passivation layer 15 at via hole 20 places and the gate insulator 13 between the transparency carrier 11, the surface of gate insulator 13 forms first transparency electrode 16 with this micro-structural.Concrete, the jagged irregularly shaped of composition technology formation passed through on the surface that is positioned at the gate insulator 13 at via hole 20 places.For example, adopt mask exposure technology, again etching is carried out on the surface of the gate insulator 13 at via hole 20 places, the control etching depth, keep a part of gate insulator 13, make first transparency electrode 16 at the substrate that forms above structure then, form the surface and have jagged erose light resistance structure 21.So this light resistance structure 21 can play the effect that prevents ray cast, avoids the light leakage phenomena of display floater, thereby improves the quality of display floater, promotes display effect.
Certainly; above-mentioned only is that to be example with Fig. 2, Fig. 3, Fig. 4 be described the manufacture method of light resistance structure; other manufacture methods that are formed for preventing the light resistance structure 21 of light transmission in via hole 20 positions are here given unnecessary details no longer one by one, but all should belong to protection scope of the present invention.
Further, described light resistance structure 21 can comprise:
As shown in Figure 5, form light shield layer 22 at the substrate that is formed with first transparency electrode 16.
Further, as shown in Figure 6, via hole 20 places not only had been formed with the surface for erose light resistance structure 21 but also had been formed with light shield layer 22 between first transparency electrode and first passivation layer, so can better play and prevent that light from seeing through the effect of this via hole, thereby the more effective light leakage phenomena of avoiding display floater has improved the display effect of display device.Need to prove; here only be that to be example with Fig. 6 have the explanation that the structure of jagged light resistance structure and light shield layer is carried out simultaneously to via hole 20 places; other is here given unnecessary details no longer one by one in the structure that via hole 20 places have jagged light resistance structure and light shield layer simultaneously, but all should belong within the protection range of the embodiment of the invention.
Concrete, be example with Fig. 2, the manufacturing process of array base palte with light resistance structure 21 is described in detail:
S301, form the pattern of the grid 120 of TFT by composition technology on the surface of transparency carrier 11.
S302, at the surface coverage gate insulator 13 of the grid 120 of TFT.
S303, adopt isolation technology (lift-out) to form semiconductor active layer 14 in the raceway groove position of the surperficial corresponding TFT12 of gate insulator 13, this semiconductor active layer is metal oxide (IGZO).
S304, form the source electrode 122 of TFT on the surface of semiconductor active layer 14 and drain 121, this step has been finished the making to thin-film transistor TFT12 after finishing.
S305, form the pattern of first passivation layer 15 at the substrate surface that is formed with TFT12.
S306, utilize the mask plate of particular design at the substrate surface that is formed with above-mentioned pattern, obtain jagged via hole 20 under the photoresist of different exposure correspondences by composition technology.
S307, carry out ion bombardment etching to finishing the via hole 20 that above-mentioned steps forms, carry out ashing photoresist and ion bombardment etching again, it is jagged irregularly shaped to make that via hole 20 places substrate forms, or with its surface roughening.
S308, form first transparency electrode 16 at the substrate surface that is formed with above-mentioned pattern, so just be formed for preventing the light resistance structure 21 of light transmission in via hole 20 positions, this first transparency electrode 16 is connected with the drain electrode 121 of TFT by this via hole 20.
S309, form second passivation layer 17 at the substrate surface that is formed with first transparency electrode 16.
S310, form second transparency electrode 18 at the substrate surface that is formed with second passivation layer 17.
Adopt above-mentioned a kind of like this array base palte, light resistance structure 21 specifically is the light reflection structure that is formed by first passivation layer 15 and first transparency electrode 16, so, by changing the design that shape that the existing layer level structure is positioned at via hole 20 places can realize light resistance structure, thereby need not additionally to arrange new level, effectively guaranteed the thickness of display unit.
Perhaps, be example with Fig. 5, the manufacturing process of array base palte with light resistance structure (light shield layer 22) is described in detail:
S401, form the pattern of the grid 120 of TFT by composition technology on the surface of transparency carrier 11.
S402, at the surface coverage gate insulator 13 of the grid 120 of TFT.
S403, adopt isolation technology (lift-out) to form semiconductor active layer 14 in the raceway groove position of the surperficial corresponding TFT12 of gate insulator 13, this semiconductor active layer is metal oxide (IGZO).
S404, form the source electrode 122 of TFT on the surface of semiconductor active layer 14 and drain 121, this step has been finished the making to thin-film transistor TFT12 after finishing.
S405, form the pattern of first passivation layer 15 at the substrate surface that is formed with TFT12.
S406, form the pattern of via hole 20 by composition technology at the substrate surface that is formed with above-mentioned pattern.
S407, form first transparency electrode, 16, the first transparency electrodes 16 at the substrate surface that is formed with above-mentioned pattern and be connected with the drain electrode 121 of TFT by this via hole 20.
S408, make light shield layer 22 in the relevant position that is formed with above-mentioned via hole 20 by composition technology.
S409, form second passivation layer 17 at the substrate surface that is formed with said structure.
S410, form second transparency electrode 18 at the substrate surface that is formed with second passivation layer 17.
Need to prove, more than only be that manufacturing process to Fig. 2 and array base palte shown in Figure 5 is illustrated, other manufacturing process with array base palte of light resistance structure 21 are here given unnecessary details no longer one by one, but all should belong to protection scope of the present invention.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (13)
1. array base palte, comprise: transparency carrier and be positioned at thin-film transistor TFT on the described transparency carrier, first passivation layer covers described TFT, first transparency electrode is positioned at the surface of described first passivation layer, described first transparency electrode is connected with the drain electrode of described TFT by via hole, it is characterized in that described via hole place has be used to the light resistance structure that prevents the light transmission.
2. array base palte according to claim 1 is characterized in that, described light resistance structure comprises continuous a plurality of inclined-planes or the micro-structural of curved surface.
3. array base palte according to claim 2 is characterized in that, described first passivation layer that is positioned at described via hole place has described micro-structural, and the surface of described first passivation layer forms described first transparency electrode with described micro-structural.
4. array base palte according to claim 2 is characterized in that, the drain electrode that is positioned at the described TFT at described via hole place has described micro-structural, and the surface of the drain electrode of described TFT forms described first transparency electrode with described micro-structural.
5. array base palte according to claim 2, it is characterized in that, have described micro-structural at described first passivation layer at described via hole place and the gate insulator between the described transparency carrier, the surface of described gate insulator forms first transparency electrode with described micro-structural.
6. array base palte according to claim 1 and 2 is characterized in that, described light resistance structure comprises light shield layer:
Described light shield layer is between described first transparency electrode and described second passivation layer.
7. a display unit is characterized in that, comprises arbitrary described array base palte as claim 1-6.
8. the manufacture method of an array base palte is characterized in that, comprising:
Form the pattern of first passivation layer at the substrate surface that is formed with thin-film transistor TFT;
At the pattern of the substrate surface that is formed with above-mentioned pattern by composition technology formation via hole, first transparency electrode is connected with the drain electrode of described TFT by described via hole;
Be formed for preventing the light resistance structure of light transmission in described via hole position.
9. method according to claim 8 is characterized in that, the manufacture method of described light resistance structure comprises:
Form described first passivation layer and described first transparency electrode on the substrate of described via hole successively being formed with;
Wherein, described via hole place forms the light resistance structure that the surface has the micro-structural of continuous a plurality of inclined-planes or curved surface by composition technology.
10. method according to claim 9 is characterized in that, described first passivation layer that is positioned at described via hole place has described micro-structural, and the surface of described first passivation layer forms described first transparency electrode with described micro-structural.
11. method according to claim 9 is characterized in that, the drain electrode that is positioned at the described TFT at described via hole place has described micro-structural, and the surface of the drain electrode of described TFT forms described first transparency electrode with described micro-structural.
12. method according to claim 9, it is characterized in that, have described micro-structural at described first passivation layer at described via hole place and the gate insulator between the described transparency carrier, the surface of described gate insulator forms first transparency electrode with described micro-structural.
13. according to Claim 8 or 9 described methods, it is characterized in that described light resistance structure comprises:
Form described light shield layer at the substrate that is formed with described first transparency electrode.
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| CN201310269322.1A CN103346159B (en) | 2013-06-28 | 2013-06-28 | A kind of array base palte and manufacture method, display device |
| PCT/CN2013/087419 WO2014205987A1 (en) | 2013-06-28 | 2013-11-19 | Array substrate and manufacturing method therefor, and display device |
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| CN201310269322.1A CN103346159B (en) | 2013-06-28 | 2013-06-28 | A kind of array base palte and manufacture method, display device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103985717A (en) * | 2014-05-13 | 2014-08-13 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, and display device |
| WO2014205987A1 (en) * | 2013-06-28 | 2014-12-31 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method therefor, and display device |
| CN104777650A (en) * | 2015-04-22 | 2015-07-15 | 京东方科技集团股份有限公司 | TFT (thin film transistor) array base plate, manufacturing method of TFT array base plate, liquid crystal display panel and display device |
| CN105321955A (en) * | 2014-06-06 | 2016-02-10 | 群创光电股份有限公司 | Thin film transistor substrate |
| CN105655391A (en) * | 2016-01-28 | 2016-06-08 | 武汉华星光电技术有限公司 | TFT array substrate and manufacturing method thereof |
| CN110438472A (en) * | 2019-06-27 | 2019-11-12 | 惠科股份有限公司 | Production method, thin film transistor (TFT) and the display panel of indium gallium zinc oxide film |
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| CN103346159B (en) * | 2013-06-28 | 2016-08-31 | 北京京东方光电科技有限公司 | A kind of array base palte and manufacture method, display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2014205987A1 (en) * | 2013-06-28 | 2014-12-31 | 北京京东方光电科技有限公司 | Array substrate and manufacturing method therefor, and display device |
| US9543331B2 (en) | 2014-05-13 | 2017-01-10 | Boe Technology Group Co., Ltd. | Array substrate and manufacturing method thereof, display device |
| WO2015172492A1 (en) * | 2014-05-13 | 2015-11-19 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method therefor, and display device |
| CN103985717A (en) * | 2014-05-13 | 2014-08-13 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate, and display device |
| CN105321955A (en) * | 2014-06-06 | 2016-02-10 | 群创光电股份有限公司 | Thin film transistor substrate |
| CN105321955B (en) * | 2014-06-06 | 2019-01-18 | 群创光电股份有限公司 | Thin film transistor substrate |
| CN109585458A (en) * | 2014-06-06 | 2019-04-05 | 群创光电股份有限公司 | Thin film transistor base plate |
| CN109585458B (en) * | 2014-06-06 | 2021-06-22 | 群创光电股份有限公司 | Thin film transistor substrate |
| CN104777650A (en) * | 2015-04-22 | 2015-07-15 | 京东方科技集团股份有限公司 | TFT (thin film transistor) array base plate, manufacturing method of TFT array base plate, liquid crystal display panel and display device |
| CN105655391A (en) * | 2016-01-28 | 2016-06-08 | 武汉华星光电技术有限公司 | TFT array substrate and manufacturing method thereof |
| CN105655391B (en) * | 2016-01-28 | 2018-10-26 | 武汉华星光电技术有限公司 | Tft array substrate and preparation method thereof |
| CN110438472A (en) * | 2019-06-27 | 2019-11-12 | 惠科股份有限公司 | Production method, thin film transistor (TFT) and the display panel of indium gallium zinc oxide film |
| CN110438472B (en) * | 2019-06-27 | 2021-08-31 | 惠科股份有限公司 | Manufacturing method of indium gallium zinc oxide thin film, thin film transistor and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103346159B (en) | 2016-08-31 |
| WO2014205987A1 (en) | 2014-12-31 |
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