CN103346150B - A kind of eight layers of stack type chip packaging structure and manufacturing process thereof - Google Patents
A kind of eight layers of stack type chip packaging structure and manufacturing process thereof Download PDFInfo
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- CN103346150B CN103346150B CN201310260733.4A CN201310260733A CN103346150B CN 103346150 B CN103346150 B CN 103346150B CN 201310260733 A CN201310260733 A CN 201310260733A CN 103346150 B CN103346150 B CN 103346150B
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- chip
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 241000218202 Coptis Species 0.000 claims abstract description 34
- 235000002991 Coptis groenlandica Nutrition 0.000 claims abstract description 34
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 239000002390 adhesive tape Substances 0.000 claims description 13
- 238000003466 welding Methods 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 6
- 229910003460 diamond Inorganic materials 0.000 claims description 5
- 239000010432 diamond Substances 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- 239000011435 rock Substances 0.000 claims description 5
- 241000196324 Embryophyta Species 0.000 claims description 3
- 230000009471 action Effects 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 238000001179 sorption measurement Methods 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 230000007246 mechanism Effects 0.000 abstract description 2
- 238000010009 beating Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
Landscapes
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The invention discloses a kind of eight layers of stack type chip packaging structure and manufacturing process thereof, it is characterized in that, comprising: a substrate that there is a relative end face and a bottom surface; Eight chips, stack arrangement is on the end face of described substrate, and wherein two chips are one group, and four core assembly sheets are stacking in intersection ladder shape; Multiple conducting wires, is electrically connected between chip and chip and between chip and substrate; The insulating resin of filling in the encapsulated space of encapsulating structure.Manufacturing process of the present invention adopts hyperfine abrasive technology, gold thread keyed section formula technology, and encapsulation matched moulds technology has captured the difficult problem that multilayer encapsulation mechanism manufactures, the encapsulating structure stable performance manufactured by manufacturing process of the present invention, yields is high, the number of plies compared with high, chip capacity is large.
Description
Technical field
The invention belongs to semiconductor memory encapsulation technology field, be specifically related to a kind of eight layers of stack type chip packaging structure and manufacturing process thereof.
Background technology
1 ~ 4 layer of chip is generally in existing encapsulating products, chip is thicker, the packaged chip number of plies is lower, chip capacity is little, and for encapsulating structures more than 4 layers of chip, due to the restriction of packaging technology ability, there is more problem, as chip grinding technique, gold thread keyed section formula technology need Special controlling, the requirement of multilayer encapsulation structure fabrication process just can be reached.
Summary of the invention
The object of this invention is to provide a kind of eight layers of stack type chip packaging structure and manufacturing process thereof.
For achieving the above object, present invention employs following technical scheme:
A kind of eight layers of stack type chip packaging structure, is characterized in that, comprising:
One substrate, has a relative end face and a bottom surface;
Eight chips, stack arrangement is on the end face of described substrate, and wherein two chips are one group, and four core assembly sheets are stacking in intersection ladder shape;
Multiple conducting wires, is electrically connected between chip and chip and between chip and substrate;
The insulating resin of filling in the encapsulated space of encapsulating structure.
Further, described eight chips are followed successively by the first chip, the second chip, the 3rd chip, the 4th chip, the 5th chip, the 6th chip, the 7th chip, the 8th chip from lower to upper; Wherein, the 8th chip is electrically connected to the 7th chip by routing combination technology; 7th chip is electrically connected to substrate by routing combination technology; 6th chip is electrically connected to the 5th chip by routing combination technology; 5th chip is electrically connected to substrate by routing combination technology; 4th chip is electrically connected to the 3rd chip by routing combination technology; 3rd chip is electrically connected to substrate by routing combination technology; Second chip is electrically connected to the first chip by routing combination technology; First chip is electrically connected to substrate by routing combination technology.
Further, the thickness of described first chip and the 5th chip is 75um, and the thickness of described second chip, the 3rd chip, the 4th chip, the 6th chip, the 7th chip and the 8th chip is 55um.
Further, described chip and chip, chip and substrate adhesive tape bonding, tape thickness is 10um.
Further, the multiple tin ball for being welded in pcb board of this bottom surface configuration of described substrate.
The manufacturing process of eight layers of stack type chip packaging structure as above, is characterized in that, comprise the steps:
The grinding of step 1 chip and cutting: the abrasive wheel using fine diamond particle, and coordinate abrasive wheel when spindle revolutions is 1400RPM and chip feed speed is 0.2mm/s, turn down vacuum and the blow gas pressure of each parts of transfer equipment, the thickness grinding the second chip, the 3rd chip, the 4th chip, the 6th chip, the 7th chip and the 8th chip is 55um; The thickness grinding the first chip and the 5th chip is 75um; And whole wafer is cut into single independently little chip; Because chip is thin, need slow mill and fine grinding, in slow speed situation, constantly incremental process ensures that chip can not be broken.
Step 2 paster: use the thick adhesive tape of 10um chip with chip, chip together with substrate sticking, technological parameter is that sorption power is greater than 70Kpa, weld force is 10N, every layers of chips carries out the baking that temperature is 145 ~ 155 DEG C, the time is 30 ~ 60 minutes, to ensure the bonding force between chip and adhesive tape;
Step 3 gold thread bonding: the mode of being good for conjunction by gold thread connects chip and chip, circuit between chip and substrate; Technological parameter is that the Bonding pressure of employing two sections exports: less initial pressure is 15-15g, chip is destroyed to prevent from rocking during capillary contact chip surface, after chip rocks and tends towards stability, then to apply slightly large pressure be 20 ~ 30g, to help the associativity of welding gold thread;
Step 4 plastic packaging: by chip, gold thread, adhesive tape, use resin-encapsulate above substrate in plastic-sealed body, when plastic packaging closes film, need to vacuumize, conjunction film pressure is 35 ~ 50t; Close after film, carry out the high-temperature baking of 160 ~ 180 DEG C, 5 hours, can the combination of fortified resin guide gas to discharge whole cavity smoothly;
Step 5 plants ball: implant tin ball in the bottom of substrate, so that element can be welded in PCB circuit version smoothly;
Step 6 is cut: each substrate, according to the size of different product, contains tens greatly to a hundreds of grain chip, by cutting action, forms several independent entry devices, so that client uses.
The present invention adopts 8 layers of chip-stacked mode, for 2-2 structure, welding gold thread is complicated, requires 2 ~ 4 simultaneously, 6 ~ 8 layers of chip thickness are 55um, 1st, 5 layers of chip thickness are 75um(usual more than 100um in the past), need to use special grinding and polishing technology to reach so thin thickness, so use the abrasive wheel of fine diamond particle, and coordinate low spindle revolutions and feed speed, in equipment transmission, the vacuum and the blow gas pressure that need to turn down each parts coordinate.In order to coordinate the use of thin chip, the adhesive tape (usual 20-25um) needing 10um thin, and after every 2 layers of chips welding, all want high pressure to toast, guarantee bonding force between chip.In order to reduce gold thread tilt phenomenon, in structural design, the special adjustment in the position of longer gold thread in wire bonding, special adjustment refers to control camber, is located at when the punching press of plastic packaging matched moulds, is positioned at stressed less place, as consistent with mould flow path direction in made it, thus reduce its distortion.Compared with tradition 1 ~ 4 layer of stacked chips product, chip is thinner, and chip is then more frangible.During welding gold thread, use " surface is submitted to " function, ultrasonic energy and welding pressure are carried out slow output of falling by it, can guarantee that capillary is when contact chip, face of weld can keep stable height, can not teetertotter because chip crosses thin, the Bonding pressure of 2 sections is adopted to export in addition: rocking and destroying chip when less initial pressure (10 to 15g) prevents capillary contact chip surperficial, after chip rocks and tends towards stability, apply a suitable pressure (20 to 30g) to help to weld the associativity of gold thread.In addition, during plastic packaging matched moulds, the distance above top chip and packaging body is reduced to conventional limit value 200um, (be less than this value, Conventional conduction formula plastic packaging is in bottleneck technically, needs another powder spray-type to encapsulate matched moulds, but needs to drop into substantial contribution.) so, when this is in plastic packaging matched moulds, need vacuum suction to coordinate, control matched moulds parameter in addition, be mainly to accelerate resin flowing velocity in early stage, extend the matched moulds bag pressure time, guide gas can discharge smoothly within whole cavity.
Invention advantage:
Eight layers of stack type chip packaging structure of the present invention have the advantage that the number of plies is higher, chip capacity is large compared to prior art, and manufacturing process of the present invention has captured the difficult problem that multilayer encapsulation mechanism manufactures, and the encapsulating structure stable performance of manufacture, yields is high.
Accompanying drawing explanation
Fig. 1 is the profile of the present invention's eight layers of stack type chip packaging structure; .
Wherein, the 1, first chip; 2, the second chip; 3, the 3rd chip; 4, the 4th chip; 5, the 5th chip; 6, the 6th chip; 7, the 7th chip; 8, the 9th chip; 9, substrate; 10, gold thread; 11, insulating resin; 12, tin ball.
Embodiment
Below in conjunction with accompanying drawing and a preferred embodiment, technical scheme of the present invention is further described.
Embodiment:
As shown in Figure 1: a kind of eight layers of stack type chip packaging structure, comprising:
One substrate 9, has a relative end face and a bottom surface;
Eight chips, stack arrangement is on the end face of described substrate 9, and wherein two chips are one group, and four core assembly sheets are stacking in intersection ladder shape;
Multiple conducting wires, is electrically connected between chip and chip and between chip and substrate 9, wire adopts gold thread 10;
The insulating resin 11 of filling in the encapsulated space of encapsulating structure.
Further, described eight chips are followed successively by the first chip 1, second chip 2, the 3rd chip 3, the 4th chip 4, the 5th chip 5, the 6th chip 6, the 7th chip 7, the 8th chip 8 from lower to upper; Wherein, the 8th chip 8 is electrically connected to the 7th chip 7 by beating gold thread; 7th chip 7 is electrically connected to substrate 9 by beating gold thread; 6th chip 6 is electrically connected to the 5th chip 5 by beating gold thread; 5th chip 5 is electrically connected to substrate 9 by beating gold thread; 4th chip 4 is electrically connected to the 3rd chip 3 by beating gold thread; 3rd chip 3 is connected to substrate 9 by beating gold thread; Second chip 2 is electrically connected to the first chip 1 by beating gold thread; First chip 1 is electrically connected to substrate 9 by beating gold thread.
The thickness of described first chip 1 and the 5th chip 5 is 75um, and the thickness of described second chip 2, the 3rd chip 3, the 4th chip 4, the 6th chip 6, the 7th chip 7 and the 8th chip 8 is 55um.
Described chip and chip, chip and substrate 9 adhesive tape bonding, tape thickness is 10um.
The multiple tin ball 12 for being welded in pcb board of this bottom surface configuration of described substrate.
The manufacturing process of eight layers of stack type chip packaging structure as above, comprises the steps:
The grinding of step 1 chip and cutting: the abrasive wheel using fine diamond particle, and coordinate abrasive wheel when spindle revolutions is 1400RPM and chip feed speed is 0.2mm/s, turn down vacuum and the blow gas pressure of each parts of transfer equipment, the thickness grinding the second chip, the 3rd chip, the 4th chip, the 6th chip, the 7th chip and the 8th chip is 55um; The thickness grinding the first chip and the 5th chip is 75um; And whole wafer is cut into single independently little chip; Because chip is thin, need slow mill and fine grinding, in slow speed situation, constantly incremental process ensures that chip can not be broken.
Step 2 paster: use the thick adhesive tape of 10um chip with chip, chip together with substrate sticking, technological parameter is that sorption power is greater than 70Kpa, weld force is 10N, every layers of chips carries out the baking that temperature is 145 ~ 155 DEG C, the time is 30 ~ 60 minutes, to ensure the bonding force between chip and adhesive tape;
Step 3 gold thread bonding: the mode of being good for conjunction by gold thread connects chip and chip, circuit between chip and substrate; Technological parameter is that the Bonding pressure of employing two sections exports: less initial pressure is 15-15g, chip is destroyed to prevent from rocking during capillary contact chip surface, after chip rocks and tends towards stability, then to apply slightly large pressure be 20 ~ 30g, to help the associativity of welding gold thread;
Step 4 plastic packaging: by chip, gold thread, adhesive tape, use resin-encapsulate above substrate in plastic-sealed body, when plastic packaging closes film, need to vacuumize, conjunction film pressure is 35 ~ 50t; Close after film, carry out the high-temperature baking of 160 ~ 180 DEG C, 5 hours, can the combination of fortified resin guide gas to discharge whole cavity smoothly;
Step 5 plants ball: implant tin ball in the bottom of substrate, so that element can be welded in PCB circuit version smoothly;
Step 6 is cut: each substrate, according to the size of different product, contains tens greatly to a hundreds of grain chip, by cutting action, forms several independent entry devices, so that client uses.
The present invention adopts 8 layers of chip-stacked mode, for 2-2 structure, welding gold thread is complicated, requires 2 ~ 4 simultaneously, 6 ~ 8 layers of chip thickness are 55um, 1st, 5 layers of chip thickness are 75um(usual more than 100um in the past), need to use special grinding and polishing technology to reach so thin thickness, so use the abrasive wheel of fine diamond particle, and coordinate low spindle revolutions and feed speed, in equipment transmission, the vacuum and the blow gas pressure that need to turn down each parts coordinate.In order to coordinate the use of thin chip, the adhesive tape (usual 20-25um) needing 10um thin, and after every 2 layers of chips welding, all want high pressure to toast, guarantee bonding force between chip.In order to reduce gold thread tilt phenomenon, in structural design, in wire bonding, the special adjustment of special adjustment of the position of longer gold thread refers to control camber, be located at when the punching press of plastic packaging matched moulds, be positioned at stressed less place, as consistent with mould flow path direction in made it, thus reduce its distortion.Compared with tradition 1 ~ 4 layer of stacked chips product, chip is thinner, and chip is then more frangible.During welding gold thread, use " surface is submitted to " function, ultrasonic energy and welding pressure are carried out slow output of falling by it, can guarantee that capillary is when contact chip, face of weld can keep stable height, can not teetertotter because chip crosses thin, the Bonding pressure of 2 sections is adopted to export in addition: rocking and destroying chip when less initial pressure (10 to 15g) prevents capillary contact chip surperficial, after chip rocks and tends towards stability, apply a suitable pressure (20 to 30g) to help to weld the associativity of gold thread.In addition, during plastic packaging matched moulds, the distance above top chip and packaging body is reduced to conventional limit value 200um, (be less than this value, Conventional conduction formula plastic packaging is in bottleneck technically, needs another powder spray-type to encapsulate matched moulds, but needs to drop into substantial contribution.) so, when this is in plastic packaging matched moulds, need vacuum suction to coordinate, control matched moulds parameter in addition, be mainly to accelerate resin flowing velocity in early stage, extend the matched moulds bag pressure time, guide gas can discharge smoothly within whole cavity.
It is to be noted; as described above is only the preferred embodiment explaining the present invention; not attempt does any restriction in form to the present invention according to this; be with; all any modification or changes having the relevant the present invention that does under identical invention spirit, all must be included in the category that the invention is intended to protection.
Claims (1)
1. a manufacturing process for eight layers of stack type chip packaging structure, is characterized in that, comprises the steps:
The grinding of step 1 chip and cutting: the abrasive wheel using fine diamond particle, and coordinate abrasive wheel when spindle revolutions is 1400RPM and chip feed speed is 0.2mm/s, turn down vacuum and the blow gas pressure of each parts of transfer equipment, the thickness grinding the second chip, the 3rd chip, the 4th chip, the 6th chip, the 7th chip and the 8th chip is 55 μm; The thickness grinding the first chip and the 5th chip is 75 μm; And whole wafer is cut into single independently little chip;
Step 2 paster: use 10 μm of thick adhesive tapes chip with chip, chip together with substrate sticking, technological parameter is that sorption power is greater than 70Kpa, weld force is 10N, every layers of chips carries out the baking that temperature is 145 ~ 155 DEG C, the time is 30 ~ 60 minutes, to ensure the bonding force between chip and adhesive tape;
Step 3 gold thread bonding: connect chip and chip by the mode of gold thread bonding, circuit between chip and substrate; Technological parameter is that the Bonding pressure of employing two sections exports: less initial pressure is 10-15g, chip is destroyed to prevent from rocking during capillary contact chip surface, after chip rocks and tends towards stability, then to apply slightly large pressure be 20 ~ 30g, to help the associativity of welding gold thread;
Step 4 plastic packaging: by chip, gold thread, adhesive tape, use resin-encapsulate above substrate in plastic-sealed body, when plastic packaging closes film, need to vacuumize, conjunction film pressure is 35 ~ 50t; Close after film, carry out the high-temperature baking of 160 ~ 180 DEG C, 5 hours, can the combination of fortified resin guide gas to discharge whole cavity smoothly;
Step 5 plants ball: implant tin ball in the bottom of substrate, so that element can be welded in PCB smoothly;
Step 6 is cut: each substrate, according to the size of different product, contains tens greatly to a hundreds of grain chip, by cutting action, forms several independent entry devices, so that client uses.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310260733.4A CN103346150B (en) | 2013-06-26 | 2013-06-26 | A kind of eight layers of stack type chip packaging structure and manufacturing process thereof |
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| CN201310260733.4A CN103346150B (en) | 2013-06-26 | 2013-06-26 | A kind of eight layers of stack type chip packaging structure and manufacturing process thereof |
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| CN103346150A CN103346150A (en) | 2013-10-09 |
| CN103346150B true CN103346150B (en) | 2015-12-02 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567364A (en) * | 2008-04-21 | 2009-10-28 | 力成科技股份有限公司 | Multichip package structure capable of arranging chips on pins |
| CN102769009A (en) * | 2011-05-04 | 2012-11-07 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging piece |
| CN203339150U (en) * | 2013-06-26 | 2013-12-11 | 力成科技（苏州）有限公司 | Eight-layer stack-type chip packaging structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100056247A (en) * | 2008-11-19 | 2010-05-27 | 삼성전자주식회사 | Semiconductor package having adhesive layer |
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- 2013-06-26 CN CN201310260733.4A patent/CN103346150B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101567364A (en) * | 2008-04-21 | 2009-10-28 | 力成科技股份有限公司 | Multichip package structure capable of arranging chips on pins |
| CN102769009A (en) * | 2011-05-04 | 2012-11-07 | 三星半导体(中国)研究开发有限公司 | Semiconductor packaging piece |
| CN203339150U (en) * | 2013-06-26 | 2013-12-11 | 力成科技（苏州）有限公司 | Eight-layer stack-type chip packaging structure |
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