CN103325702A - Chip binding method and chip binding structure - Google Patents
Chip binding method and chip binding structure Download PDFInfo
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- CN103325702A CN103325702A CN2013102792621A CN201310279262A CN103325702A CN 103325702 A CN103325702 A CN 103325702A CN 2013102792621 A CN2013102792621 A CN 2013102792621A CN 201310279262 A CN201310279262 A CN 201310279262A CN 103325702 A CN103325702 A CN 103325702A
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- endergonic structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The embodiment of the invention discloses a chip binding method and a chip binding structure, relating to the field of manufacturing processes of liquid crystal display equipment. A chip and a substrate can be prevented from warping. The chip binding method comprises the following steps: setting an energy absorption structure on a substrate, wherein the energy absorption structure is positioned beside a reserved area on the substrate, and the reserved area is used for accommodating the chip; and binding the chip in the reserved area on the substrate. The chip binding structure comprises a substrate and a chip arranged on the substrate, wherein energy absorption structures are arranged on two sides of the substrate; the energy absorption structure is positioned on the outer side of the reserved area of the substrate; the chip is arranged in the reserved area.
Description
Technical field
The present invention relates to the manufacture craft field of liquid crystal indicator, relate in particular to a kind of binding method and chip bonding structure of chip.
Background technology
In order better to reduce cost, the small size liquid crystal display product adopts chip (the Chip On Glass that is fixed on the substrate substantially at present, abbreviation COG) chip bonding process drives display panels, be specially after bare chip forms salient point, on substrate, directly be connected with the lead-in wire of LCDs.
In COG binding technical process, to lead when pressing, the pressure head of high temperature touches first chip, conducts heat to anisotropy conductiving glue and substrate by chip, and at this moment, the temperature contrast of substrate and place platform is larger, causes that dilation dimension is variant between the two.After anisotropy conductiving glue solidified, the relative position between chip and the substrate just was fixed up, after main pressure finishes, chip and substrate cool down, the size that chip shrinks is larger than substrate, so that the two ends of chip produce the larger stress to substrate, so just causes chip and substrate to produce warpage.And chip and substrate produce that warpage can cause that chip is peeled off, chip fracture, the unequal adverse consequences of display effect light and shade.
The problem that solves chip and substrate warp at present mainly adopts low temperature anisotropy conductiving glue product, but present this valuable product, and also technology is immature.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of binding method and chip bonding structure of chip, can prevent chip and substrate generation warpage.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
The invention provides a kind of binding method of chip, comprising:
At substrate endergonic structure is set, described endergonic structure is positioned at by the reserved area of described substrate, and described reserved area is used for chip placement;
In the described reserved area of described chip bonding on described substrate.
Described endergonic structure is positioned at other the comprising of reserved area of described substrate:
Described endergonic structure symmetry is positioned at described reserved area both sides.
Described endergonic structure comprises groove or through hole.
Describedly at substrate endergonic structure is set and comprises: by described substrate is carried out etching, at described substrate endergonic structure is set.
Described with before in the described reserved area of described chip bonding on described substrate, also comprise: be coated with anisotropy conductiving glue in described reserved area.
The present invention also provides a kind of chip bonding structure, comprises substrate and is arranged at chip on the substrate, and the both sides of this substrate are provided with endergonic structure, and this endergonic structure is positioned at the reserved area outside of described substrate, and this chip is set on the described reserved area.
Further, described endergonic structure symmetry is positioned at described reserved area both sides.Groove or the through hole of described endergonic structure for arranging at substrate.Be coated with anisotropy conductiving glue in described reserved area, this chip is arranged on the anisotropy conductiving glue, by anisotropy conductiving glue so that the metal wire conducting that arranges on chip and the reserved area.In the technical scheme of the embodiment of the invention, by be positioned at the other endergonic structure of reserved area of chip placement substrate setting, endergonic structure can absorb the stress that chip produces substrate in cooling procedure, so that cooling finishes rear chip and substrate is all comparatively smooth, prevent that chip and substrate from producing warpage, and then prevent the generation of chip glass, chip fracture, the unequal adverse consequences of display effect light and shade.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the binding method schematic flow sheet of the chip in the embodiment of the invention;
Fig. 2 is the board structure schematic diagram one in the embodiment of the invention;
Fig. 3 is the board structure schematic diagram two in the embodiment of the invention;
Fig. 4 is the board structure schematic diagram three in the embodiment of the invention;
Fig. 5 is the board structure schematic diagram four in the embodiment of the invention;
Fig. 6 is the board structure schematic diagram five in the embodiment of the invention.
Description of reference numerals:
1-substrate; 2-endergonic structure; 3-reserved area;
4-chip; 5-anisotropy conductiving glue; 6-pressure head.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
The embodiment of the invention provides a kind of binding method of chip, and as shown in Figure 1, the binding method of this chip comprises:
Step S101, at substrate endergonic structure is set, described endergonic structure is positioned at by the reserved area of described substrate, and described reserved area is used for chip placement.
As shown in Figure 2, be provided with endergonic structure 2 on the substrate 1, for so that endergonic structure 2 can fully absorb the two ends of chip to the stress of substrate 1, it is other that endergonic structure 2 need be placed on the reserved area 3 that substrate 1 reserves out for chip placement.
Step S102, with in the described reserved area of described chip bonding on described substrate.
Wherein, before the described reserved area 3 that described chip 4 is bundled on the described substrate 1, also need to be coated with anisotropy conductiving glues 5 in described reserved area 3.
Usually, the reserved area of substrate 1 is positioned at two adjacent edge sides of substrate 1, model according to different substrate 1, width and the distance between anisotropy conductiving glue 5 and substrate 1 edge of the anisotropy conductiving glue 5 that applies are all different, the about substrate 1 of 64 cun rectangle for example, the width of anisotropy conductiving glue 5 is 1.0mm, is 0.5mm apart from substrate 1 edge; The thickness of the anisotropy conductiving glue 5 that applies is about 0.3mm～0.5mm.
Anisotropy conductiving glue 5 mainly comprises resin adhesive agent, conducting particles two large divisions, the function of resin adhesive agent except blocks moisture, stick together, the heat-resisting and insulation function, be mainly used in chip 4 is bundled on the substrate 1, the relative position of fixed chip 4 and 1 electrode of substrate, and provide compressing strength to keep the contact area between electrode and conducting particles.
Afterwards, at binding chip 4 in the process of the reserved area 3 of substrate 1, lead when pressing, the pressure head 6 of high temperature touches first chip 4, conduct heat to anisotropy conductiving glue 5 and substrate 1 by chip 4, at this moment, be subject to materials limitations, the ductility of substrate 1 does not have chip 4 good, causes between substrate 1 and the chip 4 dilation dimension variant.After anisotropy conductiving glue 5 solidifies, relative position between chip 4 and the substrate 1 just is fixed up, after main pressure finishes, chip 4 and substrate 1 cool down, the size that chip 4 shrinks is larger than substrate 1, so that the two ends of chip 4 produce the larger stress to substrate 1, and the endergonic structure 2 on the substrate 1 can absorb the stress that 4 pairs of substrates of chip 1 produce, prevent that chip 4 and substrate 1 from producing warpage, and then prevent that chip 4 from peeling off, chip 4 ruptures, the generation of the unequal adverse consequences of display effect light and shade.
In the technical scheme of the present embodiment, a kind of binding method of chip is provided, by be positioned at the other endergonic structure of reserved area of chip placement substrate setting, endergonic structure can absorb the stress that chip produces substrate in cooling procedure, so that cooling finishes rear chip and substrate is all comparatively smooth, prevent that chip and substrate from producing warpage, and then prevent the generation of chip glass, chip fracture, the unequal adverse consequences of display effect light and shade.
Further, usually the stress of 4 pairs of substrates 1 of chip is positioned at the two ends of chip 4, and for so that endergonic structure 2 can absorb the stress of 4 pairs of substrates 1 of chip better, preferred, shown in Fig. 1 or 2, endergonic structure 2 symmetries are positioned at described reserved area 3 both sides.
Preferably, shown in Fig. 4 or 5, endergonic structure 2 can be set to groove, and for example the cross section is trapezoidal groove, and the cross section of groove also can be set to rectangle, semicircle etc., and the size of described groove, shape etc. all can be according to the actual conditions settings.
In addition, as shown in Figure 6, endergonic structure 2 also can be through hole or other structures, the through hole of circle or rectangle for example, and the embodiment of the invention does not limit this.
When endergonic structure 2 is groove or through hole, can by described substrate 1 is carried out etching, at described substrate 1 suitable endergonic structure 2 be set.
In embodiments of the present invention, substrate 1 can be glass substrate, quartz base plate etc.
The present invention also provides a kind of chip bonding structure, comprises substrate 1 and is arranged at chip 4 on the substrate, and the both sides of this substrate 1 are provided with endergonic structure 2, and this endergonic structure 2 is positioned at reserved area 3 outsides of described substrate, and this chip 4 is set on the described reserved area 3.
Further, described endergonic structure 2 symmetries are positioned at described reserved area 3 both sides.Described endergonic structure 2 is groove or the through hole that arranges at substrate 1.Be coated with anisotropy conductiving glue 5 in described reserved area 3, this chip 4 is arranged on the anisotropy conductiving glue 5, by anisotropy conductiving glue 5 so that the metal wire conducting that arranges on chip 4 and the reserved area 3.
The above; be the specific embodiment of the present invention only, but protection scope of the present invention is not limited to this, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (9)
1. the binding method of a chip is characterized in that, comprising:
At substrate endergonic structure is set, described endergonic structure is positioned at by the reserved area of described substrate, and described reserved area is used for arranging chip;
In the described reserved area of described chip bonding on described substrate.
2. the binding method of chip according to claim 1 is characterized in that, described endergonic structure is positioned at other the comprising of reserved area of described substrate:
Described endergonic structure symmetry is positioned at described reserved area both sides.
3. the binding method of chip according to claim 1 is characterized in that,
Described endergonic structure is groove or through hole.
4. the binding method of chip according to claim 3 is characterized in that, describedly at substrate endergonic structure is set and comprises:
By described substrate is carried out etching, at described substrate endergonic structure is set.
5. the binding method of chip according to claim 1 is characterized in that, and is described with before in the described reserved area of described chip bonding on described substrate, also comprises:
Be coated with anisotropy conductiving glue in described reserved area.
6. a chip bonding structure is characterized in that, comprises substrate and is arranged at chip on the substrate, and the both sides of this substrate are provided with endergonic structure, and this endergonic structure is positioned at the reserved area outside of described substrate, and this chip is set on the described reserved area.
7. chip bonding structure according to claim 6 is characterized in that, described endergonic structure symmetry is positioned at described reserved area both sides.
8. chip bonding structure according to claim 6 is characterized in that, groove or the through hole of described endergonic structure for arranging at substrate.
9. arbitrary described chip bonding structure according to claim 6-8, it is characterized in that, be coated with anisotropy conductiving glue in described reserved area, described chip is arranged on the anisotropy conductiving glue, by anisotropy conductiving glue so that the metal wire conducting that arranges on chip and the reserved area.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102792621A CN103325702A (en) | 2013-07-04 | 2013-07-04 | Chip binding method and chip binding structure |
| PCT/CN2013/087438 WO2015000248A1 (en) | 2013-07-04 | 2013-11-19 | Chip on glass bonding method and structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102792621A CN103325702A (en) | 2013-07-04 | 2013-07-04 | Chip binding method and chip binding structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103325702A true CN103325702A (en) | 2013-09-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013102792621A Pending CN103325702A (en) | 2013-07-04 | 2013-07-04 | Chip binding method and chip binding structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103325702A (en) |
| WO (1) | WO2015000248A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015000248A1 (en) * | 2013-07-04 | 2015-01-08 | 北京京东方光电科技有限公司 | Chip on glass bonding method and structure |
| CN105829996A (en) * | 2016-03-23 | 2016-08-03 | 深圳信炜科技有限公司 | Electronic device |
| WO2019029044A1 (en) * | 2017-08-10 | 2019-02-14 | 武汉华星光电技术有限公司 | Flexible display panel and substrate pi layer structure thereof, and preparation method therefor |
| CN110265373A (en) * | 2019-04-29 | 2019-09-20 | 京东方科技集团股份有限公司 | The binding method of display device and driving chip |
| CN110544655A (en) * | 2019-09-03 | 2019-12-06 | 云谷（固安）科技有限公司 | Binding device and binding method |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000082868A (en) * | 1998-09-07 | 2000-03-21 | Sony Corp | Flexible printed wiring board, flexible printed circuit board, and their manufacture |
| CN1253468A (en) * | 1998-11-03 | 2000-05-17 | 国际商业机器公司 | Control of thermal distortion of chip mount |
| JP2004266016A (en) * | 2003-02-28 | 2004-09-24 | Seiko Epson Corp | Semiconductor device, its manufacturing method and semiconductor substrate |
| JP2004317982A (en) * | 2003-04-18 | 2004-11-11 | Nippon Sheet Glass Co Ltd | Glass substrate body for multiple formation of liquid crystal display element, and manufacturing method of glass substrate body for multiple formation of liquid crystal display element |
| CN202102196U (en) * | 2011-06-06 | 2012-01-04 | 深圳市华星光电技术有限公司 | Upper chip structure of soft plate for liquid crystal display panel |
| CN202549824U (en) * | 2012-02-22 | 2012-11-21 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure |
| CN103151323A (en) * | 2011-12-06 | 2013-06-12 | 北京大学深圳研究生院 | Flip packaging structure based on anisotropy conductive glue |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4100213B2 (en) * | 2003-03-25 | 2008-06-11 | 松下電器産業株式会社 | Electronic component mounting board and electronic component mounting method |
| CN101578695B (en) * | 2006-12-26 | 2012-06-13 | 松下电器产业株式会社 | Semiconductor element mounting structure and semiconductor element mounting method |
| CN103325702A (en) * | 2013-07-04 | 2013-09-25 | 北京京东方光电科技有限公司 | Chip binding method and chip binding structure |
-
2013
- 2013-07-04 CN CN2013102792621A patent/CN103325702A/en active Pending
- 2013-11-19 WO PCT/CN2013/087438 patent/WO2015000248A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000082868A (en) * | 1998-09-07 | 2000-03-21 | Sony Corp | Flexible printed wiring board, flexible printed circuit board, and their manufacture |
| CN1253468A (en) * | 1998-11-03 | 2000-05-17 | 国际商业机器公司 | Control of thermal distortion of chip mount |
| JP2004266016A (en) * | 2003-02-28 | 2004-09-24 | Seiko Epson Corp | Semiconductor device, its manufacturing method and semiconductor substrate |
| JP2004317982A (en) * | 2003-04-18 | 2004-11-11 | Nippon Sheet Glass Co Ltd | Glass substrate body for multiple formation of liquid crystal display element, and manufacturing method of glass substrate body for multiple formation of liquid crystal display element |
| CN202102196U (en) * | 2011-06-06 | 2012-01-04 | 深圳市华星光电技术有限公司 | Upper chip structure of soft plate for liquid crystal display panel |
| CN103151323A (en) * | 2011-12-06 | 2013-06-12 | 北京大学深圳研究生院 | Flip packaging structure based on anisotropy conductive glue |
| CN202549824U (en) * | 2012-02-22 | 2012-11-21 | 苏州晶方半导体科技股份有限公司 | Chip packaging structure |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015000248A1 (en) * | 2013-07-04 | 2015-01-08 | 北京京东方光电科技有限公司 | Chip on glass bonding method and structure |
| CN105829996A (en) * | 2016-03-23 | 2016-08-03 | 深圳信炜科技有限公司 | Electronic device |
| WO2019029044A1 (en) * | 2017-08-10 | 2019-02-14 | 武汉华星光电技术有限公司 | Flexible display panel and substrate pi layer structure thereof, and preparation method therefor |
| CN110265373A (en) * | 2019-04-29 | 2019-09-20 | 京东方科技集团股份有限公司 | The binding method of display device and driving chip |
| CN110544655A (en) * | 2019-09-03 | 2019-12-06 | 云谷（固安）科技有限公司 | Binding device and binding method |
| CN110544655B (en) * | 2019-09-03 | 2021-09-14 | 云谷（固安）科技有限公司 | Binding device and binding method |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2015000248A1 (en) | 2015-01-08 |
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Application publication date: 20130925 |