CN103325423B - The automatic compare test circuit of data of non-volatility memorizer - Google Patents
The automatic compare test circuit of data of non-volatility memorizer Download PDFInfo
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- CN103325423B CN103325423B CN201210073811.5A CN201210073811A CN103325423B CN 103325423 B CN103325423 B CN 103325423B CN 201210073811 A CN201210073811 A CN 201210073811A CN 103325423 B CN103325423 B CN 103325423B
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Abstract
The invention discloses a kind of automatic compare test circuit of data of non-volatility memorizer, comprising: address accumulator, address maps selector switch, system controller, address boundary controller.Address accumulator is for completing the plus-minus of test circuit address.Address maps selector switch realizes the mapping between test circuit address and non-volatility memorizer address, and produces non-volatility memorizer address.Address boundary controller is made up of sector address generation module and sector address computing module, for non-volatility memorizer is divided into multiple data segment, and calculates the address boundary of each data segment and produces the stop condition that compares of segmentation.The present invention can reduce use, the minimizing circuit area of adding circuit, and the segmentation that can realize address is flexibly and effectively compared, and the data that can realize not isotopic number compare flexibly.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly relate to a kind of automatic compare test circuit of data of non-volatility memorizer.
Background technology
In prior art, non-volatility memorizer (NVM) generally needs the build-in self-test (BIST) passed through to test.Because the distribution of the row address (Ca) of the non-volatility memorizer of different model, column address (Ra) and block address (Ba) is different, namely there is certain difference non-volatility memorizer Ca, Ra, Ba address of different series, generally cumulative by what all arrange to each non-volatility memorizer that a totalizer realizes the address of each non-volatility memorizer in existing BIST circuit, can cause like this in BIST circuit and produce N number of totalizer and compare for the automaticdata completing N kind different modes, circuit area is large.
Although there is the division of identical Ca, Ra, Ba with a series of non-volatility memorizer, because each non-volatility memorizer is as the difference of the capacity of Flash, address may go out the situation of current address discontented (not namely being 1 entirely).Set maximum block address border in existing BIST circuit, when arriving block boundary, address returns, but this mode still can not solve the discontented situation of column address, and to need when address is compared etc. to be comparedly just to stop to maximum address, the dirigibility that data compare automatically is low.
The fixing bit wide of the automatic comparator circuit of the data supported data in existing BIST circuit compares, and the data of namely only carrying out 32-bit when the bit wide exporting data is 32-bit compare, and can not control the bit wide compared flexibly.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of automatic compare test circuit of data of non-volatility memorizer, the use of adding circuit can be reduced, reduce circuit area, the segmentation that can realize address is flexibly and effectively compared, and the data that can realize not isotopic number compare flexibly.
For solving the problems of the technologies described above, the invention provides a kind of automatic compare test circuit of data of non-volatility memorizer, the automatic compare test circuit of data comprises: address accumulator, address maps selector switch, system controller, address boundary controller.
Described system controller is described address accumulator, described address maps selector switch and described address boundary controller provide control signal.
Described address accumulator is made up of n bit address register, for completing the plus-minus of the test circuit address of the automatic compare test circuit of data.
Described address maps selector switch is under the control of the control signal of described system controller, realize the mapping between the described test circuit address in described address accumulator and the non-volatility memorizer address in non-volatility memorizer, and produce described non-volatility memorizer address according to mapping relations.
Described address boundary controller is made up of sector address generation module and sector address computing module.Described sector address generation module is used for described non-volatility memorizer to be divided into multiple data segment, and the number of described data segment is determined by described system controller.Described sector address computing module, according to the division of described data segment, calculates the address boundary of each described data segment and produces the stop condition that compares of segmentation.
Further improvement is, described non-volatility memorizer address comprises row address, column address and block address, the bit wide n of described address accumulator be the width of the described row address of described non-volatility memorizer address, described column address and described block address and.
Further improvement is, mapping relations between described test circuit address and described non-volatility memorizer address have six kinds, are respectively: 8 bit data row compare mapping, 16 bit data row compare mapping, 32 bit data row compare mapping, 8 bit data row compare mapping, 16 bit data row compare mapping, 32 bit data row compare mapping.
Further improvement is, described sector address generation module comprises data segment sized registers, is arranged the size of described data segment by the value of setting data section sized registers; Described sector address generation module comprises a data segment number register, is arranged the number of the described data segment needing to compare test by the value of a setting data section number register; Described sector address computing module comprises segment boundary register, sets the address boundary value of each described data segment in this segment boundary register, and the address boundary value of each described data segment is the maximum address value of the described test circuit address that each described data segment is corresponding; Described sector address computing module calculates according to the value of the value of described data segment sized registers, a described data segment number register and the address boundary value of each described data segment the stop condition that segmentation compares.
Further improvement is, the automatic compare test circuit of described data also comprises manner of comparison selector switch, and for setting manner of comparison, manner of comparison has four kinds, is respectively: row adds, row subtracts, Lie Jia and row subtract.
Further improvement is, the automatic compare test circuit of described data also comprises maximum number of digits selector switch, and for setting the bit wide for the data compared, the bit wide of data has 3 kinds, is respectively: 8,16 and 32.
The present invention has following beneficial effect:
1, achieve the unified continuous print computing of address, achieved the conversion of test circuit address and NVM Flash address by the mapping relations of address, decrease the use of adding circuit, what reduce circuit realizes area.
2, by adding selection and the control of the address of data segment, NVM storage space segmentation that can be right, and set the data segment scope automatically compared, produce the stop signal that segmentation is compared, the segmentation realizing data is flexibly and effectively compared.
3, compare amount register can realize 8,16, the comparing flexibly of 32 bit data by arranging.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the circuit structure diagram of the embodiment of the present invention;
Fig. 2 is the structural representation of the non-volatile type storer of the embodiment of the present invention;
Fig. 3 is the data segment structural representation of the embodiment of the present invention.
Embodiment
As shown in Figure 1, it is the circuit structure diagram of the embodiment of the present invention, the automatic compare test circuit of data of embodiment of the present invention non-volatility memorizer comprises: address accumulator 1, address maps selector switch 2, system controller 3, address boundary controller 4, for carrying out the automatic compare test of data to non-volatility memorizer (NVM FLASH) 5.Non-volatility memorizer 5 comprises the block address (Ba) of the row address (Ca) of z position, the column address (Ra) of y position and x position.
Described system controller 3 is described address accumulator 1, described address maps selector switch 2 and described address boundary controller 4 provide control signal.Described system controller 3 is connected with external testing machine by interface interface.
Described address accumulator 1 is made up of n bit address register, for completing the plus-minus of the test circuit address of the automatic compare test circuit of data.The test circuit address of the n position of described address accumulator 1 is respectively A
n-1~ A
0, this test circuit address is arranged by described system controller 3.Described address accumulator 1 can realize { A
n-1, A
n-2a
0the computing of +/-1.The bit wide n=x+y+z of described address accumulator 1.
Described address maps selector switch 2 is under the control of the control signal comp_type of described system controller 3, realize the mapping between the described test circuit address in described address accumulator 1 and the non-volatility memorizer address in non-volatility memorizer, described test circuit address is produced described non-volatility memorizer address according to mapping relations, and this control signal comp_type comprises manner of comparison selector switch and maximum number of digits selector switch etc.I.e. test circuit address { A
n-1, A
n-2a
0after mapping by described address maps selector switch 2, non-volatility memorizer address { Ba, Ra, Ca} can be produced.
Mapping relations between described test circuit address and described non-volatility memorizer address have six kinds, are respectively: 8 bit data row compare mapping, 16 bit data row compare mapping, 32 bit data row compare mapping, 8 bit data row compare mapping, 16 bit data row compare mapping, 32 bit data row compare mapping.Above-mentioned six kinds concrete mapping relations as shown in Table 1.
Table one
| Ba[z-1:0] | Ra[y-1:0] | Ca[x-1:2] | Ca[1] | Ca[0] | |
| 8-bit is capable to be compared | A x+y+z-1…A x+y | A x+y-1…A x | A x-1…A 2 | A 1 | A 0 |
| 16-bit is capable to be compared | A x+y+z-2…A x+y-1 | A x+y-2…A x-1 | A x-2…A 1 | A 0 | 0 |
| 32-bit is capable to be compared | A x+y+z-3…A x+y-2 | A x+y-3…A x-2 | A x-3…A 0 | 0 | 0 |
| 8-bit row compare | A y+z-1…A y | A y-1…A 0 | A x+y+z-1…A y+z+2 | A y+z+1 | A y+z |
| 16-bit row compare | A y+z-1…A y | A y-1…A 0 | A x+y+z-2…A y+z+1 | A y+z | 0 |
| 32-bit row compare | A y+z-1…A y | A y-1…A 0 | A x+y+z-3…A y+z | 0 | 0 |
Described address boundary controller 4 is made up of sector address generation module and sector address computing module, described system controller 3 realizes the control to described address boundary controller 4 by control signal sector_sel, and this control signal sector_sel comprises the setting value of the value i of data segment sized registers, the value j of a data segment number register and segment boundary register B [i-1:0] three parameters.Described sector address generation module is used for described non-volatility memorizer to be divided into multiple data segment, and the number of described data segment is determined by described system controller 3.Described sector address computing module, according to the division of described data segment, calculates the address boundary of each described data segment and produces the stop condition that compares of segmentation.The stop condition signal stop_sig obtained is sent to described system controller by described address boundary controller 4.
Described sector address generation module arranges the size of described data segment by the value i of setting data section sized registers, and namely the size i of described data segment is expressed as: 2
ibyte.Described sector address generation module arranges the number of the described data segment needing to compare test by the value j of a setting data section number register; Namely, from current data section, need to compare j data segment and terminate.Such as, as NVM FLASH to be divided into the data segment of 1Kbyte and the data segment compared is 5 time, then can to arrange i be 10 the size of data segment (represent are 1024byte), and j is 5.
The address boundary value of each described data segment that described sector address computing module sets according to the value i of described data segment sized registers and segment boundary register B [i-1:0] calculates the address boundary of each described data segment.The address boundary value of each described data segment is the described test circuit address { A that each described data segment is corresponding
i-1, A
i-2a
0maximum address value, the address boundary value of each described data segment is stored in segment boundary register B [i-1:0].When the value of the address of test circuit described in test process is added to the address boundary value of the storage of segment boundary register B [i-1:0], the figure place carry that described test circuit address is corresponding or borrow.The address boundary value of each described data segment of the setting in described segment boundary register B [i-1:0] determines the border needing in each described data segment to carry out detecting, this border specifically can be divided into two kinds of situations: when the first is full address situation, data segment as design partition is 1024byte, and comparison range is when being the whole 1024byte data in data segment, the now address boundary value of each described data segment and the maximum address of each described data segment.The second situation is that the address that will test is when being discontented with, as shown in Figure 3, data segment as design partition is 1024byte, and when comparison range is the whole 512byte data in data segment, now the address boundary value of each described data segment is less than the maximum address of each described data segment.
Described sector address computing module calculates according to the value j of the value i of described data segment sized registers, a described data segment number register stop condition that segmentation compares.
As shown in Figure 2, be the structural representation of non-volatile type storer of the embodiment of the present invention.Non-volatility memorizer 5 divide into P-1 section, is respectively sector 0, sector 1 ..., sectorp-1.Each section all comprises coordinate and the { coordinate of Ba, Ra} address of Ca address.
Fig. 3 is the data segment structural representation of the embodiment of the present invention.The data of non-volatile type storer divide into q-1 section at the storage space of non-volatility memorizer, i.e. section 0, section 1 ..., section q-1.The horizontal ordinate scope of each section comprises A
i-1-D~ A
0, ordinate scope comprises A
n-1~ A
i-1-D.D is the bit wide of data, and the bit wide of data has 3 kinds, is respectively: 8,16 and 32, and corresponding D value is respectively 0,1,2.D value sets in maximum number of digits selector switch D [1:0], for setting the bit wide for the data compared.Part in Fig. 3 indicated by y is for comparing data segment.Start address is wherein obtained for arranging in described address accumulator 1 by described system controller 3, and the value in conjunction with the address boundary value of the storage of start address, i, j and segment boundary register B [i-1:0] can obtain end address.When each data segment compares, when the value of described test circuit address is added to the address boundary value of the storage of segment boundary register B [i-1:0], the figure place carry that described test circuit address is corresponding or borrow.When comparing described end address, described address boundary controller 4 will produce stop condition signal stop_sig and send to described system controller, and test is terminated.
The automatic compare test circuit of described data also comprises manner of comparison selector switch C [1:0], and for setting manner of comparison, manner of comparison has four kinds, is respectively: row adds, row subtracts, Lie Jia and row subtract.When manner of comparison for row adds or arranges the added-time, start address is set to the described lowest address comparing data segment; When manner of comparison for row subtract or arrange subtract time, start address is set to the described maximum address comparing data segment.
The method of work of the data automatic compare test circuit of embodiment of the present invention non-volatility memorizer is as follows:
The value i of described data segment sized registers, value j, the manner of comparison selector switch C [1:0] of a described data segment number register, the value of maximum number of digits selector switch D [1:0] and segment boundary register B [i-1:0] are set by external testing unit, and the value of the described test circuit address arranging described address accumulator 1 is initial address.
According to i and j value, described address boundary controller 4 carries out segmentation to described non-volatility memorizer 5, and calculates the stop condition that segmentation compares.
Described test circuit address in described address accumulator 1 is mapped to non-volatility memorizer address by described address maps selector switch, and compares test to the data in the non-volatility memorizer corresponding to described test circuit address; The accumulating operation of +/-1 is carried out in described test circuit address, then by the described test circuit address maps after computing to non-volatility memorizer address, and test is compared to the data in the non-volatility memorizer corresponding to described test circuit address; Repeat above-mentioned compare test process, until when described test circuit address is end address, compare test terminates.
At the end of compare test, described address boundary controller 4 will produce stop condition signal stop_sig and send to described system controller, and test is terminated.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. the automatic compare test circuit of the data of non-volatility memorizer, is characterized in that, the automatic compare test circuit of data comprises: address accumulator, address maps selector switch, system controller, address boundary controller;
Described system controller is described address accumulator, described address maps selector switch and described address boundary controller provide control signal;
Described address accumulator is made up of n bit address register, for completing the plus-minus of the test circuit address of the automatic compare test circuit of data;
Described address maps selector switch is under the control of the control signal of described system controller, realize the mapping between the described test circuit address in described address accumulator and the non-volatility memorizer address in non-volatility memorizer, and produce described non-volatility memorizer address according to mapping relations;
Described address boundary controller is made up of sector address generation module and sector address computing module;
Described sector address generation module is used for described non-volatility memorizer to be divided into multiple data segment, and the number of described data segment is determined by described system controller;
Described sector address computing module, according to the division of described data segment, calculates the address boundary of each described data segment and produces the stop condition that compares of segmentation; When each described data segment compares, when the value of described test circuit address is added to the address boundary value of the storage of segment boundary register, the figure place carry that described test circuit address is corresponding or borrow; When comparing end address, described address boundary controller will produce stop condition signal and send to described system controller, and test is terminated.
2. the automatic compare test circuit of data of non-volatility memorizer as claimed in claim 1, it is characterized in that: described non-volatility memorizer address comprises row address, column address and block address, the bit wide n of described address accumulator be the width of the described row address of described non-volatility memorizer address, described column address and described block address and.
3. the automatic compare test circuit of data of non-volatility memorizer as claimed in claim 1 or 2, it is characterized in that: the mapping relations between described test circuit address and described non-volatility memorizer address have six kinds, are respectively: 8 bit data row compare mapping, 16 bit data row compare mapping, 32 bit data row compare mapping, 8 bit data row compare mapping, 16 bit data row compare mapping, 32 bit data row compare mapping.
4. the automatic compare test circuit of data of non-volatility memorizer as claimed in claim 1, is characterized in that:
Described sector address generation module comprises data segment sized registers, is arranged the size of described data segment by the value of setting data section sized registers;
Described sector address generation module comprises a data segment number register, is arranged the number of the described data segment needing to compare test by the value of a setting data section number register;
Described sector address computing module comprises segment boundary register, sets the address boundary value of each described data segment in this segment boundary register, and the address boundary value of each described data segment is the maximum address value of the described test circuit address that each described data segment is corresponding;
Described sector address computing module calculates according to the value of the value of described data segment sized registers, a described data segment number register and the address boundary value of each described data segment the stop condition that segmentation compares.
5. the automatic compare test circuit of data of non-volatility memorizer as claimed in claim 1, it is characterized in that: the automatic compare test circuit of described data also comprises manner of comparison selector switch, for setting manner of comparison, manner of comparison has four kinds, is respectively: row adds, row subtracts, Lie Jia and row subtract.
6. the automatic compare test circuit of data of non-volatility memorizer as claimed in claim 1, it is characterized in that: the automatic compare test circuit of described data also comprises maximum number of digits selector switch, for setting the bit wide for the data compared, the bit wide of data has 3 kinds, is respectively: 8,16 and 32.
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| CN110751978B (en) * | 2019-10-16 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Test calibration method and test calibration circuit for non-volatile memory |
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