CN103325423A - Data automatically-comparing test circuit of non-volatile memory - Google Patents
Data automatically-comparing test circuit of non-volatile memory Download PDFInfo
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- CN103325423A CN103325423A CN2012100738115A CN201210073811A CN103325423A CN 103325423 A CN103325423 A CN 103325423A CN 2012100738115 A CN2012100738115 A CN 2012100738115A CN 201210073811 A CN201210073811 A CN 201210073811A CN 103325423 A CN103325423 A CN 103325423A
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Abstract
The invention discloses a data automatically-comparing test circuit of a non-volatile memory, comprises an address accumulator, an address mapping selector, a system controller and an address boundary controller. The address accumulator is used for completing addition and subtraction of the test circuit. The address mapping selector is used for implementing mapping between a test circuit address and a non-volatile memory address, and for generating the non-volatile memory address. The address boundary controller is composed of a segment address generation module and a segment address calculation module, and is used for dividing the non-volatile memory into a plurality of data segments, calculating address boundary of each data segment, and generating a stop condition of segment comparison. The data automatically-comparing test circuit of a non-volatile memory can reduce usage of addition, can reduce a circuit area, can flexibly and effectively implement the segment comparison of the address, and can implement flexible comparison data with different bits.
Description
Technical field
The present invention relates to a kind of SIC (semiconductor integrated circuit), particularly relate to a kind of automatic compare test circuit of data of non-volatility memorizer.
Background technology
In the prior art, the build-in self-test (BIST) that non-volatility memorizer (NVM) generally need to pass through is tested.Because the distribution of row address (Ca), column address (Ra) and the block address (Ba) of the non-volatility memorizer of different model is different, there is certain difference non-volatility memorizer Ca, the Ra, the Ba address that are different series, generally be to realize cumulative to the address of each non-volatility memorizer by each non-volatility memorizer all being arranged a totalizer in the existing BIST circuit, can cause like this to produce N totalizer in the BIST circuit for the automaticdata of finishing N kind different modes relatively, circuit area is large.
Although the division of identical Ca, Ra, Ba is arranged with a series of non-volatility memorizer, because the difference of the capacity of each non-volatility memorizer such as Flash, the address may go out the situation of current address discontented (namely not being 1 entirely).To set maximum block address border in the existing BIST circuit, the address is returned when arriving block boundary, but this mode still can not solve the discontented situation of column address, and the address needs relatively the time etc. to be comparedly just can to stop to maximum address, and the dirigibility that data compare automatically is low.
The fixedly bit wide of the automatic comparator circuit of the data supported data in the existing BIST circuit is relatively namely only carried out the data of 32-bit relatively, flexibly control ratio bit wide when the bit wide of output data is 32-bit.
Summary of the invention
Technical matters to be solved by this invention provides a kind of automatic compare test circuit of data of non-volatility memorizer, can reduce use, the minimizing circuit area of adding circuit, can realize flexibly and effectively the segmentation of address relatively, can realize that the data of isotopic number do not compare flexibly.
For solving the problems of the technologies described above, the invention provides a kind of automatic compare test circuit of data of non-volatility memorizer, the automatic compare test circuit of data comprises: address accumulator, address mapping selector switch, system controller, address boundary controller.
Described system controller provides control signal for described address accumulator, described address mapping selector switch and described address boundary controller.
Described address accumulator is comprised of n bit address register, for the plus-minus of the test circuit address of finishing the automatic compare test circuit of data.
Described address mapping selector switch is under the control of the control signal of described system controller, realize described test circuit address in the described address accumulator and the mapping between the non-volatility memorizer address in the non-volatility memorizer, and produce described non-volatility memorizer address according to mapping relations.
Described address boundary controller is comprised of sector address generation module and sector address computing module.Described sector address generation module is used for described non-volatility memorizer is divided into a plurality of data segments, and the number of described data segment is determined by described system controller.Described sector address computing module calculates the address boundary of each described data segment and produces segmentation stop condition relatively according to the division of described data segment.
Further improve and be, described non-volatility memorizer address comprises row address, column address and block address, the bit wide n of described address accumulator be the described row address of described non-volatility memorizer address, described column address and described block address width and.
Further improve and be, mapping relations between described test circuit address and the described non-volatility memorizer address have six kinds, are respectively: 8 bit data row relatively shine upon, 16 bit data row relatively shine upon, 32 bit data row relatively shine upon, 8 bit data row relatively shine upon, 16 bit data row relatively shine upon, the relatively mapping of 32 bit data row.
Further improvement is, comprises the data segment sized registers in the described sector address generation module, and the size of described data segment is set by the value that the data segment sized registers is set; Comprise a data segment number register in the described sector address generation module, need to compare the number of the described data segment of test by the value setting that a data segment number register is set; Comprise the segment boundary register in the described sector address computing module, set the address boundary value of each described data segment in this segment boundary register, the address boundary value of each described data segment is the maximum address value of described test circuit address corresponding to each described data segment; Described sector address computing module calculates segmentation stop condition relatively according to the value of the value of described data segment sized registers, a described data segment number register and the address boundary value of each described data segment.
Further improve and be, the automatic compare test circuit of described data also comprises the manner of comparison selector switch, is used for setting manner of comparison, and manner of comparison has four kinds, is respectively: row adds, row subtracts, Lie Jia and row subtract.
Further improvement is, the automatic compare test circuit of described data also comprises the maximum number of digits selector switch, is used for setting the bit wide that is used for data relatively, and the bit wide of data has 3 kinds, is respectively: 8,16 and 32.
The present invention has following beneficial effect:
1, realizes the continuous computing of unification of address, realized the conversion of test circuit address and NVM Flash address by the mapping relations of address, reduced the use of adding circuit, reduced the realization area of circuit.
2, pass through selection and the control of the address of adding data segment, NVM storage space segmentation that can be right, and set the data segment scope that automatically compares, the stop signal that the generation segmentation is compared realizes the segmentation of data relatively flexibly and effectively.
3, by being set, comparison figure place register can realize 8,16, the flexible comparison of 32 bit data.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments:
Fig. 1 is the circuit structure diagram of the embodiment of the invention;
Fig. 2 is the structural representation of the non-volatile type storer of the embodiment of the invention;
Fig. 3 is the data segment structural representation of the embodiment of the invention.
Embodiment
As shown in Figure 1, it is the circuit structure diagram of the embodiment of the invention, the automatic compare test circuit of the data of embodiment of the invention non-volatility memorizer comprises: address accumulator 1, address mapping selector switch 2, system controller 3, address boundary controller 4 are used for non-volatility memorizer (NVM FLASH) 5 is carried out the automatic compare test of data.Non-volatility memorizer 5 comprises the row address (Ca) of z position, the column address (Ra) of y position and the block address (Ba) of x position.
Described system controller 3 provides control signal for described address accumulator 1, described address mapping selector switch 2 and described address boundary controller 4.Described system controller 3 is connected with the external testing machine by interface interface.
Described address accumulator 1 is comprised of n bit address register, for the plus-minus of the test circuit address of finishing the automatic compare test circuit of data.The test circuit address of the n position of described address accumulator 1 is respectively A
N-1～A
0, this test circuit address can arrange by described system controller 3.Described address accumulator 1 can realize { A
N-1, A
N-2A
0The computing of }+/-1.The bit wide n=x+y+z of described address accumulator 1.
Described address mapping selector switch 2 is under the control of the control signal comp_type of described system controller 3, realize described test circuit address in the described address accumulator 1 and the mapping between the non-volatility memorizer address in the non-volatility memorizer, described test circuit address is produced described non-volatility memorizer address according to mapping relations, and this control signal comp_type comprises manner of comparison selector switch and maximum number of digits selector switch etc.Be test circuit address { A
N-1, A
N-2A
0After the mapping by described address mapping selector switch 2, can produce non-volatility memorizer address { Ba, Ra, Ca}.
Mapping relations between described test circuit address and the described non-volatility memorizer address have six kinds, are respectively: 8 bit data row relatively shine upon, 16 bit data row relatively shine upon, 32 bit data row relatively shine upon, 8 bit data row relatively shine upon, 16 bit data row relatively shine upon, the relatively mapping of 32 bit data row.Six kinds of above-mentioned concrete mapping relations as shown in Table 1.
Table one
| Ba[z-1:0] | Ra[y-1:0] | Ca[x-1:2] | Ca[1] | Ca[0] | |
| 8-bit is capable relatively | A x+y+z-1…A x+y | A x+y-1…A x | A x-1…A 2 | A 1 | A 0 |
| 16-bit is capable relatively | A x+y+z-2…A x+y-1 | A x+y-2…A x-1 | A x-2…A 1 | A 0 | 0 |
| 32-bit is capable relatively | A x+y+z-3…A x+y-2 | A x+y-3…A x-2 | A x-3…A 0 | 0 | 0 |
| 8-bit is listed as relatively | A y+z-1…A y | A y-1…A 0 | A x+y+z-1…A y+z+2 | A y+z+1 | A y+z |
| 16-bit is listed as relatively | A y+z-1…A y | A y-1…A 0 | A x+y+z-2…A y+z+1 | A y+z | 0 |
| 32-bit is listed as relatively | A y+z-1…A y | A y-1…A 0 | A x+y+z-3…A y+z | 0 | 0 |
Described address boundary controller 4 is comprised of sector address generation module and sector address computing module, described system controller 3 is realized control to described address boundary controller 4 by control signal sector_sel, and this control signal sector_sel comprises the value i of data segment sized registers, value j and the segment boundary register B[i-1:0 of a data segment number register] setting value of three parameters.Described sector address generation module is used for described non-volatility memorizer is divided into a plurality of data segments, and the number of described data segment is determined by described system controller 3.Described sector address computing module calculates the address boundary of each described data segment and produces segmentation stop condition relatively according to the division of described data segment.Described address boundary controller 4 sends to described system controller with the stop condition signal stop_sig that obtains.
Described sector address generation module arranges the size of described data segment by the value i that the data segment sized registers is set, namely the size of described data segment is expressed as with i: 2
iByte.Described sector address generation module arranges the number of the described data segment that need to compare test by the value j that a data segment number register is set; Namely from the current data section, needing relatively, j data segment finishes.For example, when being 5 such as the data segment of the data segment that NVM FLASH will be divided into 1Kbyte and comparison, it is 10 (size of expression data segment is 1024byte) that i then can be set, and j is 5.
Described sector address computing module is according to value i and the segment boundary register B[i-1:0 of described data segment sized registers] the address boundary value of each described data segment of setting calculates the address boundary of each described data segment.The address boundary value of each described data segment is described test circuit address { A corresponding to each described data segment
I-1, A
I-2A
0The maximum address value, the address boundary value of each described data segment is stored in segment boundary register B[i-1:0] in.Value when the address of test circuit described in the test process is added to segment boundary register B[i-1:0] the address boundary value of storage the time, figure place carry or borrow that described test circuit address is corresponding.Described segment boundary register B[i-1:0] in the address boundary value of each described data segment of setting need in each described data segment to have determined the border detected, this border specifically can be divided into two kinds of situations: when the first is full address situation, data segment such as design partition is 1024byte, and comparison range is when being whole 1024byte data in the data segment, this moment each described data segment the address boundary value and the maximum address of each described data segment.The second situation is that the address that will test is when discontented, as shown in Figure 3, data segment such as design partition is 1024byte, and comparison range is when being whole 512byte data in the data segment, this moment each described data segment the address boundary value less than the maximum address of each described data segment.
Described sector address computing module calculates segmentation stop condition relatively according to the value j of the value i of described data segment sized registers, a described data segment number register.
As shown in Figure 2, be the structural representation of the non-volatile type storer of the embodiment of the invention.Non-volatility memorizer 5 has been divided into P-1 section, is respectively sector 0, and sector 1 ..., sectorp-1.Each section all comprises coordinate and { Ba, the coordinate of Ra} address of Ca address.
Fig. 3 is the data segment structural representation of the embodiment of the invention.The data of non-volatile type storer have been divided into q-1 section at the storage space of non-volatility memorizer, i.e. section 0, and section 1 ..., section q-1.The horizontal ordinate scope of each section comprises A
I-1-D～A
0, the ordinate scope comprises A
N-1～A
I-1-DD is the bit wide of data, and the bit wide of data has 3 kinds, is respectively: 8,16 and 32, corresponding D value is respectively 0,1,2.The D value is at maximum number of digits selector switch D[1:0] in set, be used for to set be used for the bit wide of data relatively.The indicated part of y is the comparing data section among Fig. 3.Start address wherein is to obtain for arranging in the described address accumulator 1 by described system controller 3, in conjunction with start address, i, j and segment boundary register B[i-1:0] the value of address boundary value of storage can obtain the end address.When each data segment compared, the value of described test circuit address was added to segment boundary register B[i-1:0] the address boundary value of storage the time, figure place carry or borrow that described test circuit address is corresponding.When relatively arriving described end address, described address boundary controller 4 will produce stop condition signal stop_sig and send to described system controller, so that test finishes.
The automatic compare test circuit of described data also comprises manner of comparison selector switch C[1:0], be used for to set manner of comparison, manner of comparison has four kinds, is respectively: row adds, row subtracts, Lie Jia and row subtract.When manner of comparison adds or is listed as the added-time for row, start address is set to the lowest address of described comparing data section; When manner of comparison subtracts for row or is listed as when subtracting, start address is set to the maximum address of described comparing data section.
The method of work of the automatic compare test circuit of the data of embodiment of the invention non-volatility memorizer is as follows:
Value j, the manner of comparison selector switch C[1:0 of the value i of described data segment sized registers, a described data segment number register are set by the external testing unit], maximum number of digits selector switch D[1:0] and segment boundary register B[i-1:0] value, and the value that the described test circuit address of described address accumulator 1 is set is initial address.
According to i and j value, 4 pairs of described non-volatility memorizers 5 of described address boundary controller carry out segmentation, and calculate segmentation stop condition relatively.
Described test circuit address in the described address accumulator 1 is mapped to the non-volatility memorizer address by described address mapping selector switch, and the data in the corresponding non-volatility memorizer in described test circuit address are compared test; Described test circuit address carries out+/-1 accumulating operation, and the more described test circuit address after the computing is mapped to the non-volatility memorizer address, and the data in the corresponding non-volatility memorizer in described test circuit address are compared test; Repeat above-mentioned compare test process, until described test circuit address is when being the end address, compare test finishes.
When compare test finished, described address boundary controller 4 will produce stop condition signal stop_sig and send to described system controller, so that test finishes.
Abovely by specific embodiment the present invention is had been described in detail, but these are not to be construed as limiting the invention.In the situation that do not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (6)
1. the automatic compare test circuit of the data of a non-volatility memorizer is characterized in that, the automatic compare test circuit of data comprises: address accumulator, address mapping selector switch, system controller, address boundary controller;
Described system controller provides control signal for described address accumulator, described address mapping selector switch and described address boundary controller;
Described address accumulator is comprised of n bit address register, for the plus-minus of the test circuit address of finishing the automatic compare test circuit of data;
Described address mapping selector switch is under the control of the control signal of described system controller, realize described test circuit address in the described address accumulator and the mapping between the non-volatility memorizer address in the non-volatility memorizer, and produce described non-volatility memorizer address according to mapping relations;
Described address boundary controller is comprised of sector address generation module and sector address computing module;
Described sector address generation module is used for described non-volatility memorizer is divided into a plurality of data segments, and the number of described data segment is determined by described system controller;
Described sector address computing module calculates the address boundary of each described data segment and produces segmentation stop condition relatively according to the division of described data segment.
2. the automatic compare test circuit of the data of non-volatility memorizer as claimed in claim 1, it is characterized in that: described non-volatility memorizer address comprises row address, column address and block address, the bit wide n of described address accumulator be the described row address of described non-volatility memorizer address, described column address and described block address width and.
3. the automatic compare test circuit of the data of non-volatility memorizer as claimed in claim 1 or 2, it is characterized in that: the mapping relations between described test circuit address and the described non-volatility memorizer address have six kinds, are respectively: 8 bit data row relatively shine upon, 16 bit data row relatively shine upon, 32 bit data row relatively shine upon, 8 bit data row relatively shine upon, 16 bit data row relatively shine upon, the relatively mapping of 32 bit data row.
4. the automatic compare test circuit of the data of non-volatility memorizer as claimed in claim 1 is characterized in that:
Comprise the data segment sized registers in the described sector address generation module, the size of described data segment is set by the value that the data segment sized registers is set;
Comprise a data segment number register in the described sector address generation module, need to compare the number of the described data segment of test by the value setting that a data segment number register is set;
Comprise the segment boundary register in the described sector address computing module, set the address boundary value of each described data segment in this segment boundary register, the address boundary value of each described data segment is the maximum address value of described test circuit address corresponding to each described data segment;
Described sector address computing module calculates segmentation stop condition relatively according to the value of the value of described data segment sized registers, a described data segment number register and the address boundary value of each described data segment.
5. the automatic compare test circuit of the data of non-volatility memorizer as claimed in claim 1, it is characterized in that: the automatic compare test circuit of described data also comprises the manner of comparison selector switch, be used for to set manner of comparison, manner of comparison has four kinds, is respectively: row adds, row subtracts, Lie Jia and row subtract.
6. the automatic compare test circuit of the data of non-volatility memorizer as claimed in claim 1, it is characterized in that: the automatic compare test circuit of described data also comprises the maximum number of digits selector switch, be used for setting the bit wide that is used for data relatively, the bit wide of data has 3 kinds, is respectively: 8,16 and 32.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229009A (en) * | 2016-07-12 | 2016-12-14 | 北京兆易创新科技股份有限公司 | A kind of folded sealing chip processing means containing abnormal non-volatility memorizer and method |
| CN106843813A (en) * | 2016-12-28 | 2017-06-13 | 华为技术有限公司 | A kind of data processing method and device |
| CN110751978A (en) * | 2019-10-16 | 2020-02-04 | 上海华虹宏力半导体制造有限公司 | Test calibration method and test calibration circuit for non-volatile memory |
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| US20040006730A1 (en) * | 2002-07-08 | 2004-01-08 | Samsung Electronics Co., Ltd. | Apparatus and method for testing on-chip ROM |
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| CN1336553A (en) * | 2000-05-19 | 2002-02-20 | 株式会社鼎新 | Mode generator used for testing semiconductor system |
| US20040006730A1 (en) * | 2002-07-08 | 2004-01-08 | Samsung Electronics Co., Ltd. | Apparatus and method for testing on-chip ROM |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106229009A (en) * | 2016-07-12 | 2016-12-14 | 北京兆易创新科技股份有限公司 | A kind of folded sealing chip processing means containing abnormal non-volatility memorizer and method |
| CN106229009B (en) * | 2016-07-12 | 2019-06-28 | 北京兆易创新科技股份有限公司 | A kind of folded sealing chip processing unit and method containing abnormal non-volatility memorizer |
| CN106843813A (en) * | 2016-12-28 | 2017-06-13 | 华为技术有限公司 | A kind of data processing method and device |
| WO2018120767A1 (en) * | 2016-12-28 | 2018-07-05 | 华为技术有限公司 | Data processing method and device |
| CN110751978A (en) * | 2019-10-16 | 2020-02-04 | 上海华虹宏力半导体制造有限公司 | Test calibration method and test calibration circuit for non-volatile memory |
| CN110751978B (en) * | 2019-10-16 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Test calibration method and test calibration circuit for non-volatile memory |
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