CN106229009B - A kind of folded sealing chip processing unit and method containing abnormal non-volatility memorizer - Google Patents
A kind of folded sealing chip processing unit and method containing abnormal non-volatility memorizer Download PDFInfo
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- CN106229009B CN106229009B CN201610548009.5A CN201610548009A CN106229009B CN 106229009 B CN106229009 B CN 106229009B CN 201610548009 A CN201610548009 A CN 201610548009A CN 106229009 B CN106229009 B CN 106229009B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
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Abstract
The present invention provides a kind of folded sealing chip processing unit and method containing abnormal non-volatility memorizer, processing unit therein includes that PAD value defines non-volatility memorizer address mapping module, non-volatility memorizer address of cache is defined for PAD value, it further include modified address mapping block, when folding the tested confirmation of sealing chip for non-volatility memorizer and including abnormal non-volatility memorizer, modify to the address of cache of each individual non-volatility memorizer.The address of each independent non-volatility memorizer is remapped by folding the mapping of sealing chip modified address to containing abnormal non-volatility memorizer, keeps the capacity of the folded mounting small by changing greatly, continued to use, to improve the utilization rate of chip by the present invention.
Description
Technical field
The present invention relates to technology of semiconductor chips fields, more particularly to a kind of folded envelope containing abnormal non-volatility memorizer
Chip processing device and method.
Background technique
With the rapid development of microelectric technique, to meet user for the diversified need of non-volatility memorizer capacity
It asks, by the way that the folded non-volatility memorizer for being enclosed in generation large capacity together of multiple low capacity non-volatility memorizers is folded envelope core
Piece, design cost can also be greatly reduced by being designed in this way.It folds in sealing chip in packaged non-volatility memorizer if there is certain
One or several non-volatility memorizers are abnormal or fail, and will lead to the folded sealing chip of non-volatility memorizer can not work normally,
The non-volatility memorizer folds sealing chip and is typically only capable to scrap processing, causes greatly to waste.
Therefore a technical problem that is urgently needed by the technical personnel in the field at present is that: how by some or it is several non-
Volatile storage exception or the non-volatility memorizer of failure fold sealing chip and are handled and be used.
Summary of the invention
To solve the above-mentioned problems, the invention discloses a kind of, and the folded sealing chip containing abnormal non-volatility memorizer handles dress
It sets, described device includes that PAD value defines non-volatility memorizer address mapping module, further includes:
Modified address mapping block, for non-volatility memorizer fold the tested confirmation of sealing chip include it is abnormal non-volatile
When memory, modify to the address of cache of each individual non-volatility memorizer.
Preferably, further include that modified address maps non-volatile signal writing module, include modification ground in the write module
Location maps non-volatile signal, for by the new address write-in non-volatility memorizer to remap fold sealing chip each is non-
Volatile storage;Further include:
Modified address maps non-volatile signal and enables module, includes the non-volatile letter of modified address mapping in the enabled module
Number enable signal, the address of cache of non-volatile modification of signal non-volatility memorizer is mapped for enabling modified address.
Preferably, the modified address maps non-volatile signal, for by the address of cache of abnormal non-volatility memorizer
It is revised as the address of cache not used, and the address for other non-volatility memorizers that remap, while made non-volatile
Memory folds the capacity of sealing chip by 2NMultiple value is reduced to 2KMultiple value, N and K are natural integer, and N > K.
Preferably, the modified address maps the enable signal of non-volatile signal for selective signal, deposits when non-volatile
When reservoir folds sealing chip tested confirmation non-volatility memorizer without exception, PAD value defines non-volatility memorizer address of cache
Effectively, when non-volatility memorizer, which folds the tested confirmation of sealing chip, includes abnormal non-volatility memorizer, PAD value defines non-wave
The storage address mapping of hair property is invalid, and the non-volatile signal of enabled modified address mapping carrys out modified address mapping.
Preferably, the bit wide that the modified address maps non-volatile signal is folded the non-of sealing chip by non-volatility memorizer and is waved
Hair property memory number N determines, is defined as that [(N/2-1): 0], the bit wide can just correspond to the N number of non-volatile holographic storage of modification
The address of cache of device.
On the other hand, the folded sealing chip processing method containing abnormal non-volatility memorizer that the invention also discloses a kind of, packet
It includes PAD value and defines non-volatility memorizer address of cache step, the method also includes:
Modified address mapping step: the tested confirmation of sealing chip is folded when non-volatility memorizer and includes extremely non-volatile deposit
When reservoir, modify to the address of cache of each individual non-volatility memorizer.
Preferably, further includes:
Modified address maps non-volatile signal write step: modified address being mapped non-volatile signal, non-volatile deposit is written
Reservoir folds each non-volatility memorizer of sealing chip, and the modified address maps what non-volatile signal was used to remap
New address write-in non-volatility memorizer folds each non-volatility memorizer of sealing chip;
Modified address mapping step: the tested confirmation of sealing chip is folded when non-volatility memorizer and includes extremely non-volatile deposit
When reservoir, non-volatile signal is mapped by modified address, the address of cache of each individual non-volatility memorizer is repaired
Change;Further include
Modified address maps non-volatile signal and enables step, is made by the enable signal that modified address maps non-volatile signal
Energy modified address maps the address of cache of non-volatile modification of signal non-volatility memorizer.
Preferably, described that non-volatile signal is mapped to the ground of each individual non-volatility memorizer by modified address
Location mapping is modified, it is characterised in that: the address of cache of abnormal non-volatility memorizer is become to the address of cache not used,
And the address for other non-volatility memorizers that remap, while non-volatility memorizer being made to fold the capacity of sealing chip by 2N
Multiple value is reduced to 2KMultiple value, N and K are natural integer, and N > K.
Preferably, modified address used in the modified address mapping step maps the enable signal of non-volatile signal and is
Selective signal correspondingly further includes the enabled step of selectivity: folding the tested confirmation of sealing chip when non-volatility memorizer and is no different
When normal non-volatility memorizer, it is effective that PAD value defines non-volatility memorizer address of cache, when the folded envelope core of non-volatility memorizer
When the tested confirmation of piece includes abnormal non-volatility memorizer, it is invalid that PAD value defines non-volatility memorizer address of cache, enables
Modified address maps non-volatile signal and carrys out modified address mapping.
Preferably, the modified address maps non-volatile signal write step further include:
Bit wide design procedure: before write-in modified address maps non-volatile signal, it is non-volatile to be pre-designed modified address mapping
The bit wide of signal is determined by the non-volatility memorizer number N that non-volatility memorizer folds sealing chip, is defined as N/2-1, described
Bit wide can just correspond to the address of cache for modifying N number of non-volatility memorizer.
Compared with the existing method of background technique, the invention has the following advantages that
Existing method with respect to the background art: scrapping processing for the folded sealing chip containing abnormal non-volatility memorizer,
It causes for greatly wasting, the present invention, will be every by mapping the folded sealing chip modified address containing abnormal non-volatility memorizer
The address of one independent non-volatility memorizer is remapped, and is kept the capacity of the folded mounting small by changing greatly, is continued to use, from
And improve the utilization rate of chip.
Detailed description of the invention
Fig. 1 is a kind of structure chart of the folded sealing chip processing device embodiment 1 containing abnormal non-volatility memorizer of the present invention;
Fig. 2 is a kind of structure chart of the folded sealing chip processing device embodiment 2 containing abnormal non-volatility memorizer of the present invention;
Fig. 3 is a kind of structure chart of the folded sealing chip processing device embodiment 3 containing abnormal non-volatility memorizer of the present invention;
Fig. 4 is a kind of flow chart of the folded sealing chip processing method embodiment 4 containing abnormal non-volatility memorizer of the present invention;
Fig. 5 is a kind of flow chart of the folded sealing chip processing method embodiment 5 containing abnormal non-volatility memorizer of the present invention;
Fig. 6 be the present invention it is a kind of containing abnormal non-volatility memorizer folded sealing chip processing method modified address mapping before,
Address number schematic diagram afterwards;
Fig. 7 is a kind of flow chart of the folded sealing chip processing method embodiment 6 containing abnormal non-volatility memorizer of the present invention.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing and specific real
Applying mode, the present invention is described in further detail.
One of the core concepts of the embodiments of the present invention is, by some or several non-volatility memorizers be abnormal or failure
Non-volatility memorizer fold sealing chip handled and be used;Accordingly, with respect to the existing method of background technique, setting
Modified address mapping block, the modified address that non-volatile signal is mapped comprising modified address map non-volatile signal writing module
And modified address maps non-volatile signal and enables module, by each list for folding sealing chip containing abnormal non-volatility memorizer
Only non-volatility memorizer modified address mapping, enable its continue using.
Referring to Fig.1, a kind of folded sealing chip processing device embodiment 1 containing abnormal non-volatility memorizer of the present invention is shown
Structure chart, can specifically include:
PAD value defines non-volatility memorizer address mapping module 101, reflects for carrying out address to non-volatility memorizer
It penetrates;
Modified address mapping block 102 folds the tested confirmation of sealing chip for non-volatility memorizer and includes extremely non-wave
When hair property memory, modify to the address of cache of each individual non-volatility memorizer.
Processing unit of the invention can be applied to the modified address mapping process of various folded sealing chips, for example, non-volatile
Property memory fold sealing chip, non-volatility memorizer includes Nand Flash and Nor Flash etc..Below only with Nand
Flash is illustrated for folding sealing chip, and other memory chips please refer to.
With 2NThe folded envelope of the non-volatility memorizer that a capacity is mG is (2 at a capacityN* m) for the folded sealing chip of G, N
For natural integer, the non-volatility memorizer number for folding envelope is determined.By traditional address mapping method, defined by PAD value non-
Volatile storage address mapping module 101 solidifies the relevant PAD of each non-volatility memorizer in the folded envelope of folded sealing chip
Value defines each non-volatility memorizer address, such as its non-volatility memorizer address number is successively defined as from top to bottom
chip0,chip1,chip2…chip(2N-1)。
When non-volatility memorizer, which folds the tested confirmation of sealing chip, includes one or several abnormal non-volatility memorizers,
Enabled modified address mapping block 102, each individual non-volatility memorizer of sealing chip is folded to non-volatility memorizer
Address of cache modify.Modified non-volatility memorizer is folded sealing chip and can be continued to use.
Referring to Fig. 2, a kind of folded sealing chip processing device embodiment 2 containing abnormal non-volatility memorizer of the present invention is shown
Structure chart, can specifically include PAD value and define non-volatility memorizer address mapping module 201, for being deposited to non-volatile
Reservoir carries out address of cache;Can also include:
Modified address mapping block 202 folds the tested confirmation of sealing chip for non-volatility memorizer and includes extremely non-wave
When hair property memory, modify to the address of cache of each individual non-volatility memorizer;Can also include:
Modified address maps non-volatile signal writing module 203, maps in the write module 203 comprising modified address non-
Volatilization signal 2031 is the new address remapped, and before folded envelope or folded test discovery of being honored as a queen has abnormal non-volatility memorizer
When, write-in non-volatility memorizer folds each non-volatility memorizer of sealing chip, and the modified address maps non-volatile letter
Numbers 2031, the address of cache for the address of cache of abnormal non-volatility memorizer to be revised as not using, and remap it
His non-volatility memorizer address, while non-volatility memorizer being made to fold the capacity of sealing chip by 2NMultiple value is reduced to 2K
Multiple value, N and K are natural integer, and N > K;Further include:
Modified address maps non-volatile signal and enables module 204, and including that modified address mapping is non-in the enabled module waves
The enable signal 2041 of signalling, the address that non-volatile modification of signal non-volatility memorizer is mapped for enabling modified address are reflected
It penetrates.
The present embodiment is relative to the difference of embodiment 1, increases modified address and maps non-volatile signal writing module
203 and modified address map non-volatile signal and enable module 204, the write module 203 include modified address map it is non-volatile
Signal 2031, when non-volatility memorizer, which folds the tested confirmation of sealing chip, includes abnormal non-volatility memorizer, starting modification
The non-volatile signal of address of cache enables module 204, with enabling the front or rear modification that each non-volatility memorizer is written of folded envelope
Location maps non-volatile signal 2031, completes to map its modified address;The modified address maps non-volatile signal 2031, is used for
The address of cache of abnormal non-volatility memorizer is revised as to the address of cache not used, and it is other non-volatile to remap
Storage address, while non-volatility memorizer being made to fold the capacity of sealing chip by 2NMultiple value is reduced to 2KMultiple value.
Referring to Fig. 3, a kind of folded sealing chip processing device embodiment 3 containing abnormal non-volatility memorizer of the present invention is shown
Structure chart, can specifically include PAD value and define non-volatility memorizer address mapping module 301, for being deposited to non-volatile
Reservoir carries out address of cache;Can also include:
Modified address mapping block 302 folds the tested confirmation of sealing chip for non-volatility memorizer and includes extremely non-wave
When hair property memory, the address of cache for folding sealing chip to non-volatility memorizer is modified;Can also include:
Modified address maps non-volatile signal writing module 303, and the write module 303, which includes that modified address mapping is non-, waves
It signals the 3031 i.e. new addresses remapped, before folded envelope or folded test discovery of being honored as a queen has abnormal non-volatility memorizer
When, write-in non-volatility memorizer folds each non-volatility memorizer of sealing chip, and the modified address maps non-volatile letter
Numbers 3031, the address of cache for the address of cache of abnormal non-volatility memorizer to be revised as not using, and remap it
His non-volatility memorizer address, while non-volatility memorizer being made to fold the capacity of sealing chip by 2NMultiple value is reduced to 2K
Multiple value, N and K are natural integer, and N > K;Further include:
Modified address maps non-volatile signal and enables module 304, and including that modified address mapping is non-in the enabled module waves
The enable signal 3041 of signalling, the address that non-volatile modification of signal non-volatility memorizer is mapped for enabling modified address are reflected
It penetrates;
The enable signal 3041 is selective signal, when to fold the tested confirmation of sealing chip without exception for non-volatility memorizer
When non-volatility memorizer, it is effective that PAD value defines non-volatility memorizer address of cache, when non-volatility memorizer folds sealing chip
Tested confirmation is when including abnormal non-volatility memorizer, and it is invalid that PAD value defines non-volatility memorizer address of cache, enabled to repair
Change of address maps non-volatile signal 3031 and carrys out modified address mapping;The modified address maps non-volatile signal 3031, bit wide
3032 are folded the non-volatility memorizer number 2 of sealing chip by non-volatility memorizerNIn N determine, be defined as [(N/2-1):
0], the bit wide can just correspond to the address of cache for modifying N number of non-volatility memorizer.
The present embodiment is relative to the difference of embodiment 2, preferably defines modified address and maps non-volatile signal
Enable signal 3041 is selective signal, when non-volatility memorizer folds the tested confirmation non-volatile holographic storage without exception of sealing chip
When device, it is effective that PAD value defines non-volatility memorizer address of cache, when non-volatility memorizer is folded in the tested confirmation of sealing chip
When containing abnormal non-volatility memorizer, it is invalid that PAD value defines non-volatility memorizer address of cache, and it is non-to enable modified address mapping
Volatilization signal comes modified address and maps each non-volatility memorizer;The modified address maps non-volatile signal 3031,
Its bit wide is folded the non-volatility memorizer number 2 of sealing chip by non-volatility memorizerNIn N determine, be defined as [(N/2-1):
0]。
It is corresponding to aforementioned device embodiment 1, the invention also discloses a kind of folded envelope core containing abnormal non-volatility memorizer
Piece processing method embodiment 4, referring to Fig. 4, the method be can specifically include:
PAD value defines non-volatility memorizer address of cache step 401, carries out address of cache to non-volatility memorizer;
Modified address mapping step 402, the tested confirmation of the folded sealing chip of non-volatility memorizer include abnormal non-volatile
When memory, modify to the address of cache of each individual non-volatility memorizer.
Processing method of the invention can be applied to the modified address mapping process of various folded sealing chips, for example, non-volatile
Property memory fold sealing chip, non-volatility memorizer includes Nand Flash and Nor Flash etc..Below only with Nand
Flash is illustrated for folding sealing chip, and other memory chips please refer to.
With 2NThe folded envelope of the non-volatility memorizer that a capacity is mG is (2 at a capacityN* m) for the folded sealing chip of G, tool
Body, 22The folded envelope of the non-volatility memorizer that a capacity is 2G is (2 at a capacity2* 2) the folded sealing chip of G, that is, 8G.By tradition
Address mapping method defines non-volatility memorizer address of cache step 401 by PAD value, solidifies in the folded envelope of folded sealing chip
The relevant PAD value of each non-volatility memorizer defines the device address of each non-volatility memorizer, such as from top to bottom
Its non-volatility memorizer address number is successively defined as chip0, chip1, chip2, chip 3.
When non-volatility memorizer, which folds the tested confirmation of sealing chip, includes an abnormal non-volatility memorizer, specifically
The non-volatility memorizer on ground, corresponding chip0 address number is abnormal, independent to each by modified address mapping step 402
The address of cache of non-volatility memorizer modify, in the present embodiment, chip0 address number is changed to not use
Chip3, and the address chip1 is changed to chip0, the address chip2 is changed to chip1, the address chip3 is changed to chip2.After modification
Non-volatility memorizer fold sealing chip can continue to use, become a capacity be (22-1* 2) the folded sealing chip of G, that is, 4G.
Referring to Fig. 5, a kind of folded sealing chip processing method embodiment 5 containing abnormal non-volatility memorizer of the present invention is shown
Flow chart, can specifically include:
PAD value defines non-volatility memorizer address of cache step 501, carries out address of cache to non-volatility memorizer;
Can also include:
Modified address mapping step 502, the tested confirmation of the folded sealing chip of non-volatility memorizer include abnormal non-volatile
When memory, modify to the address of cache of each individual non-volatility memorizer;May be used also before or after the step
To include:
Modified address maps non-volatile signal write step 503, the new address that said write step 503 will remap
I.e. modified address maps non-volatile signal 5031, before folded envelope or when folded test discovery of being honored as a queen has abnormal non-volatility memorizer,
Each non-volatility memorizer that non-volatility memorizer folds sealing chip is written, the modified address maps non-volatile signal
The address of cache of abnormal non-volatility memorizer is revised as the address of cache not used by 5031, and each non-volatile is deposited
The address of reservoir is remapped, while non-volatility memorizer being made to fold the capacity of sealing chip by 2NMultiple value is reduced to 2KMultiple
Value;Can also include:
Modified address maps non-volatile signal and enables step 504, and the enabled letter of non-volatile signal is mapped by modified address
Numbers 5041, enabled modified address maps the address of cache of non-volatile modification of signal non-volatility memorizer.
The present embodiment is relative to the difference of embodiment 4, increases modified address and maps non-volatile signal write step
503 and modified address map non-volatile signal and enable step 504, modified address is mapped non-volatile letter by said write step 503
Number each non-volatility memorizer is written before or after non-volatility memorizer folds the folded envelope of sealing chip, works as non-volatility memorizer
When the tested confirmation of folded sealing chip includes abnormal non-volatility memorizer, address of cache of modifying step 502, which includes
Modified address maps non-volatile signal and enables step 504, and the modified address for enabling each non-volatility memorizer maps non-wave
It signals to complete to map its modified address, after the mapping of modified address, the address of cache of abnormal non-volatility memorizer is modified as
For without using address of cache, and the address of each non-volatility memorizer is remapped, while making non-volatile deposit
Reservoir folds the capacity of sealing chip by 2NMultiple value is reduced to 2KMultiple value.
Referring to Fig. 6, with 2NThe folded envelope of the non-volatility memorizer that a capacity is mG is (2 at a capacityN* m) the folded envelope core of G
For piece.First by traditional address mapping method, non-volatility memorizer address of cache step 501 is defined by PAD value, in folded envelope
Chip solidifies the address that the relevant PAD value of each non-volatility memorizer defines each non-volatility memorizer when folding envelope,
Such as its non-volatility memorizer address number is successively defined as 0,1,2 from top to bottom ... .K ... M ... 2N- 1, in the present embodiment just
The number that corresponding non-volatility memorizer is called with non-volatility memorizer address number is chip0, chip1,
chip2…..chipK……chipM……chip(2N- 1), non-volatility memorizer ... the ..chipK that chip0, that is, address is 0
As address be K non-volatility memorizer ... ..chip (2N- 1) i.e. address is (2N- 1) non-volatility memorizer.
Then non-volatile signal write step 503 is mapped by modified address, modified address is mapped into non-volatile signal i.e.
The new address remapped, write-in non-volatility memorizer folds each non-volatile holographic storage of sealing chip before or after folded envelope
Device.If causing chip K and chip M abnormal for some reason in the folded test or use process being honored as a queen, envelope folded in this way
Chip just can not work normally.But other non-volatility memorizers other than chip K and chip M are all normal
, we can use other non-volatility memorizers other than chip K and chip M and form a capacity less than (2N*
M) the folded sealing chip of G, such as capacity are (2N-1* m) G, this just needs to rewrite the non-volatile holographic storage of each non-volatility memorizer
The address of these non-volatility memorizers is remapped in device address.
Remap non-volatility memorizer address method it is shown in Figure 6.Firstly, one non-volatile signal of design
CHIP_AD is written this signal in each chip, uses it to redefine non-volatility memorizer address.Because of chip K
Abnormal chips with chip M, by modification chip K and its more than non-volatility memorizer chip (K+1) ... chip N etc.
Non-volatility memorizer address, to realize that folding sealing chip address to non-volatility memorizer remaps.By former chip K
The non-volatility memorizer address of (chip K or less in Fig. 6) remains unchanged below, and the address of former chip K is changed to chip (2N -1), successively to subtract 1 up to the non-volatility memorizer address below chip M, the address of former chip M is changed to former chip K
chip(2N-1+ 1), former chip M is up to chip (2N-1) chip address between+1 successively subtracts 2, former chip (2N-1)+1 it is non-
Volatile storage address becomes chip (2N-1) -1, former chip (2N-1)+1 or more non-volatility memorizer address keep not
Become.Original chip0 in this way to original chip (2N-1) just to have reformulated a capacity be (2 to the non-volatility memorizer between+1N-1*m)G
Folded sealing chip, which can continue to use.chip(2N-1)+1 or more non-volatility memorizer do not use, ground
Location need not modify.
Referring to Fig. 7, a kind of folded sealing chip processing method embodiment 6 containing abnormal non-volatility memorizer of the present invention is shown
Flow chart, can specifically include:
PAD value defines non-volatility memorizer address of cache step 601, carries out address of cache to non-volatility memorizer;
Can also include:
Modified address mapping step 602, the tested confirmation of the folded sealing chip of non-volatility memorizer include abnormal non-volatile
When memory, modify to the address of cache of each individual non-volatility memorizer;May be used also before or after the step
To include:
Modified address maps non-volatile signal write step 603, and said write step 603 maps modified address non-volatile
Signal 6031 is the new address remapped, before folded envelope or when folded test discovery of being honored as a queen has abnormal non-volatility memorizer,
Each non-volatility memorizer that non-volatility memorizer folds sealing chip is written, the modified address maps non-volatile signal
6031, the address of cache for the address of cache of abnormal non-volatility memorizer to be revised as not using, and remap other
Non-volatility memorizer address, while make non-volatility memorizer fold sealing chip capacity by 2NMultiple value is reduced to 2KTimes
Numerical value, N and K are natural integer, and N > K;Further include:
Modified address maps non-volatile signal and enables module 604, and including that modified address mapping is non-in the enabled module waves
The enable signal 6041 of signalling, the address that non-volatile modification of signal non-volatility memorizer is mapped for enabling modified address are reflected
It penetrates;
The enable signal 6041 is selective signal, when to fold the tested confirmation of sealing chip without exception for non-volatility memorizer
When non-volatility memorizer, it is effective that PAD value defines non-volatility memorizer address of cache, when non-volatility memorizer folds sealing chip
Tested confirmation is when including abnormal non-volatility memorizer, and it is invalid that PAD value defines non-volatility memorizer address of cache, enabled to repair
Change of address maps non-volatile signal 6031 and carrys out modified address mapping;
The modified address maps non-volatile signal write step 603 further include:
Bit wide design procedure 6032 is pre-designed modified address and reflects before write-in modified address maps non-volatile signal 6031
The bit wide of non-volatile signal is penetrated, bit wide is folded the non-volatility memorizer number 2 of sealing chip by non-volatility memorizerNIn N
It determines, is defined as that [(N/2-1): 0], the bit wide can just correspond to the address of cache for modifying N number of non-volatility memorizer, i.e.,
The bit wide can just correspond to the address of cache for modifying N number of non-volatility memorizer.
The present embodiment is that the modified address mapping is non-volatile except preferably defining relative to the difference of embodiment 5
The enable signal 6041 of signal is selective signal, when to fold the tested confirmation of sealing chip without exception non-volatile for non-volatility memorizer
Property memory when, it is effective that PAD value defines non-volatility memorizer address of cache, when to fold sealing chip tested for non-volatility memorizer
Confirmation is when including abnormal non-volatility memorizer, and it is invalid that PAD value defines non-volatility memorizer address of cache, enables modified address
It maps non-volatile signal 6031 and carrys out modified address mapping;Also non-volatile signal write step 603 is mapped in modified address to increase
Bit wide design procedure 605, design code modified address map the bit wide of non-volatile signal 6031 by non-volatility memorizer number
N in 2N is determined, is defined as [(N/2-1): 0].
Referring to Fig. 6, with 2NThe folded envelope of the non-volatility memorizer that a capacity is mG is (2 at a capacityN* m) the folded envelope core of G
For piece.First by traditional address mapping method, non-volatility memorizer address of cache step 601 is defined by PAD value, in folded envelope
Chip solidifies the relevant PAD value of each non-volatility memorizer when folding envelope and defines the non-volatile of each non-volatility memorizer
Property storage address, such as its non-volatility memorizer address number is successively defined as 0,1,2 from top to bottom ... K ... M ... (2N-
1) number for, just calling corresponding non-volatility memorizer in the present embodiment with non-volatility memorizer address number is
chip0,chip1,chip2…..chipK……chipM……chip(2N- 1), chip0 be address be 0 it is non-volatile
Memory ... ..chipK is non-volatility memorizer ... the ..chip (2 that non-volatility memorizer address is KN- 1) as non-
Volatile storage address is (2N- 1) non-volatility memorizer.
Cause chip K and chip M abnormal for some reason in the folded test or use process being honored as a queen, envelope folded in this way
Chip just can not work normally.But other non-volatility memorizers other than chip K and chip M are all normal
, we can use other non-volatility memorizers other than chip K and chip M and form a capacity less than (2N*
M) the folded sealing chip of G, such as capacity are (2N-1* m) G, this just needs to rewrite the non-volatile holographic storage of each non-volatility memorizer
The non-volatility memorizer address of these non-volatility memorizers is remapped in device address.The present embodiment is by modification ground
Location maps non-volatile signal write step 603, modified address is mapped non-volatile signal 6031 after folded envelope test, non-wave is written
Hair property memory folds each non-volatility memorizer of sealing chip.
Remap non-volatility memorizer address method it is shown in Figure 6.Firstly, one non-volatile signal of design
[(N/2-1): 0], bit wide [(N/2-1): 0] indicates that the address of cache of N number of non-volatility memorizer can be modified, often CHIP_AD
This signal is all written in a non-volatility memorizer, uses it to redefine non-volatility memorizer address.Enable signal
CHIP_AD_EN is 1bit bit wide, and as CHIP_AD_EN=0, it is effective to define non-volatility memorizer address with PAD;When
When CHIP_AD_EN=1, the non-volatility memorizer address that PAD is defined will be invalid, [(N/2-1): 0] is determined using CHIP_AD
Adopted non-volatility memorizer address.The method being specifically defined is referring to embodiment 5.
All the embodiments in this specification are described in a progressive manner, the highlights of each of the examples are with
The difference of other embodiments, the same or similar parts between the embodiments can be referred to each other.For embodiment of the method
For, since it is substantially similar to Installation practice, so being described relatively simple, referring to the portion of embodiment of the method in place of correlation
It defends oneself bright.
Above to a kind of folded sealing chip processing unit and method containing abnormal non-volatility memorizer provided by the present invention,
It is described in detail, used herein a specific example illustrates the principle and implementation of the invention, the above reality
The explanation for applying example is merely used to help understand method and its core concept of the invention;Meanwhile for the general technology of this field
Personnel, according to the thought of the present invention, there will be changes in the specific implementation manner and application range, in conclusion this theory
Bright book content should not be construed as limiting the invention.
Claims (8)
1. a kind of folded sealing chip processing unit containing abnormal non-volatility memorizer, described device include PAD value define it is non-volatile
Property storage address mapping block, for non-volatility memorizer carry out address of cache, which is characterized in that further include:
Modified address mapping block folds the tested confirmation of sealing chip for non-volatility memorizer and includes abnormal non-volatile holographic storage
When device, modify to the address of cache of each individual non-volatility memorizer;
Modified address maps non-volatile signal writing module, includes that modified address maps non-volatile signal in the write module,
For the new address write-in non-volatility memorizer to remap to be folded to each non-volatility memorizer of sealing chip;
Modified address maps non-volatile signal and enables module, includes that modified address maps non-volatile signal in the enabled module
Enable signal maps the address of cache of non-volatile modification of signal non-volatility memorizer for enabling modified address;
The modified address maps non-volatile signal, for the address of cache of abnormal non-volatility memorizer to be revised as not using
Address of cache, and the address for other non-volatility memorizers that remap, while making the folded envelope core of non-volatility memorizer
The capacity of piece is by 2NMultiple value is reduced to 2KMultiple value, N and K are natural integer, and N > K.
2. device as described in claim 1, which is characterized in that the enable signal that the modified address maps non-volatile signal is
Selective signal, when non-volatility memorizer folds sealing chip tested confirmation non-volatility memorizer without exception, the definition of PAD value
Non-volatility memorizer address of cache is effective, when non-volatility memorizer fold the tested confirmation of sealing chip include it is abnormal non-volatile
When memory, it is invalid that PAD value defines non-volatility memorizer address of cache, and enabled modified address maps non-volatile signal to modify
Address of cache.
3. device as described in claim 1, which is characterized in that the bit wide that the modified address maps non-volatile signal is waved by non-
The non-volatility memorizer number N that hair property memory folds sealing chip is determined, is defined as that [(N/2-1): 0], the bit wide just can
Enough corresponding address of cache for modifying N number of non-volatility memorizer.
4. device as claimed in claim 2, which is characterized in that the bit wide that the modified address maps non-volatile signal is waved by non-
The non-volatility memorizer number N that hair property memory folds sealing chip is determined, is defined as that [(N/2-1): 0], the bit wide just can
Enough corresponding address of cache for modifying N number of non-volatility memorizer.
5. a kind of folded sealing chip processing method containing abnormal non-volatility memorizer, including PAD value define non-volatility memorizer
Address of cache step, for carrying out address of cache to non-volatility memorizer, which is characterized in that the method also includes:
Modified address mapping step: the tested confirmation of sealing chip is folded when non-volatility memorizer and includes abnormal non-volatility memorizer
When, it modifies to the address of cache of each individual non-volatility memorizer;
Modified address maps non-volatile signal write step: modified address being mapped non-volatile signal, non-volatility memorizer is written
Each non-volatility memorizer of folded sealing chip, it is new for what will be remapped that the modified address maps non-volatile signal
Each non-volatility memorizer that non-volatility memorizer folds sealing chip is written in address;
Modified address mapping step: the tested confirmation of sealing chip is folded when non-volatility memorizer and includes abnormal non-volatility memorizer
When, non-volatile signal is mapped by modified address and is modified to the address of cache of each individual non-volatility memorizer;
Modified address maps non-volatile signal and enables step, and the enable signal for mapping non-volatile signal by modified address is enabled to repair
Change of address maps the address of cache of non-volatile modification of signal non-volatility memorizer;
It is described that address of cache progress of the non-volatile signal to each individual non-volatility memorizer is mapped by modified address
Modification, it is characterised in that: the address of cache of abnormal non-volatility memorizer is become to the address of cache not used, and is remapped
The address of other non-volatility memorizers, while non-volatility memorizer being made to fold the capacity of sealing chip by 2NMultiple value reduces
It is 2KMultiple value, N and K are natural integer, and N > K.
6. method as claimed in claim 5, which is characterized in that modified address used in the modified address mapping step is reflected
The enable signal of non-volatile signal is penetrated as selective signal, correspondingly further includes the enabled step of selectivity: working as non-volatile holographic storage
When device folds sealing chip tested confirmation non-volatility memorizer without exception, PAD value, which defines non-volatility memorizer address of cache, to be had
Effect, when non-volatility memorizer, which folds the tested confirmation of sealing chip, includes abnormal non-volatility memorizer, PAD value defines non-volatile
Property storage address mapping it is invalid, enabled modified address maps non-volatile signal and carrys out modified address mapping.
7. method as claimed in claim 5, which is characterized in that the modified address maps non-volatile signal write step and also wraps
It includes:
Bit wide design procedure: it before write-in modified address maps non-volatile signal, is pre-designed modified address and maps non-volatile signal
Bit wide, determined by the non-volatility memorizer number N that non-volatility memorizer folds sealing chip, be defined as [(N/2-1): 0], institute
Rheme is wide can just to correspond to the address of cache for modifying N number of non-volatility memorizer.
8. method as claimed in claim 6, which is characterized in that the modified address maps non-volatile signal write step and also wraps
It includes:
Bit wide design procedure: it before write-in modified address maps non-volatile signal, is pre-designed modified address and maps non-volatile signal
Bit wide, determined by the non-volatility memorizer number N that non-volatility memorizer folds sealing chip, be defined as [(N/2-1): 0], institute
Rheme is wide can just to correspond to the address of cache for modifying N number of non-volatility memorizer.
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