CN106229009A - A kind of folded sealing chip processing means containing abnormal non-volatility memorizer and method - Google Patents
A kind of folded sealing chip processing means containing abnormal non-volatility memorizer and method Download PDFInfo
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- CN106229009A CN106229009A CN201610548009.5A CN201610548009A CN106229009A CN 106229009 A CN106229009 A CN 106229009A CN 201610548009 A CN201610548009 A CN 201610548009A CN 106229009 A CN106229009 A CN 106229009A
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- 238000007789 sealing Methods 0.000 title claims abstract description 114
- 230000002159 abnormal effect Effects 0.000 title claims abstract description 66
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000012545 processing Methods 0.000 title claims abstract description 14
- 238000013507 mapping Methods 0.000 claims abstract description 76
- 238000012790 confirmation Methods 0.000 claims abstract description 32
- 238000003672 processing method Methods 0.000 claims description 10
- 238000013461 design Methods 0.000 claims description 9
- 238000012986 modification Methods 0.000 claims description 8
- 230000004048 modification Effects 0.000 claims description 8
- 238000000151 deposition Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 239000002699 waste material Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
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Abstract
The invention provides a kind of folded sealing chip processing means containing abnormal non-volatility memorizer and method, processing means therein includes that PAD value defines non-volatility memorizer address mapping module, map for PAD value definition non-volatility memorizer address, also include modified address mapping block, for non-volatility memorizer fold the tested confirmation of sealing chip include abnormal non-volatility memorizer time, the address of each single non-volatility memorizer is mapped and modifies., by folding the mapping of sealing chip modified address to containing abnormal non-volatility memorizer, being remapped in the address of each independent non-volatility memorizer by the present invention, the capacity making this folded mounting is little by changing greatly, is continuing with, thus improves the utilization rate of chip.
Description
Technical field
The present invention relates to technology of semiconductor chips field, particularly relate to a kind of folded envelope containing abnormal non-volatility memorizer
Chip processing means and method.
Background technology
Along with developing rapidly of microelectric technique, for meeting the user's diversified need for non-volatility memorizer capacity
Ask, by folded for multiple low capacity non-volatility memorizers being enclosed in is generated jumbo non-volatility memorizer folded envelope core together
Sheet, is so designed that and also can greatly reduce design cost.If folding in sealing chip at packaged non-volatility memorizer and having certain
One or several non-volatility memorizer is abnormal or loses efficacy, and non-volatility memorizer will be caused to fold sealing chip cannot normally work,
This non-volatility memorizer is folded sealing chip and is typically only capable to scrap process, causes waste greatly.
It is thus desirable to the technical problem that those skilled in the art urgently solve is exactly: how by some or several non-
Volatile storage non-volatility memorizer that is abnormal or that lost efficacy is folded sealing chip and is processed and be used.
Summary of the invention
In order to solve the problems referred to above, the invention discloses a kind of folded sealing chip containing abnormal non-volatility memorizer and process dress
Putting, described device includes that PAD value defines non-volatility memorizer address mapping module, also includes:
Modified address mapping block, folds the tested confirmation of sealing chip for non-volatility memorizer and includes abnormal non-volatile
During memorizer, the address mapping to each single non-volatility memorizer is modified.
Preferably, also include that modified address maps non-volatile signal writing module, in said write module, comprise amendment ground
Location maps non-volatile signal, non-for the new address write non-volatility memorizer remapped is folded each of sealing chip
Volatile storage；Also include:
Modified address maps non-volatile signal and enables module, comprises modified address and map non-volatile letter in described enable module
Number enable signal, for enable modified address map non-volatile modification of signal non-volatility memorizer address map.
Preferably, described modified address maps non-volatile signal, for being mapped the address of abnormal non-volatility memorizer
It is revised as the address that do not uses to map, and other the address of non-volatility memorizer of remapping, make non-volatile simultaneously
Memorizer folds the capacity of sealing chip by 2NMultiple value is reduced to 2KMultiple value, N and K is natural integer, and N > K.
Preferably, it is selectivity signal that described modified address maps the enable signal of non-volatile signal, deposits when non-volatile
When sealing chip tested confirmation non-volatility memorizer without exception folded by reservoir, PAD value definition non-volatility memorizer address maps
Effectively, when non-volatility memorizer fold the tested confirmation of sealing chip include abnormal non-volatility memorizer time, PAD value defines non-waving
It is invalid that the property sent out storage address maps, and the non-volatile signal enabling modified address mapping carrys out modified address mapping.
Preferably, described modified address maps the bit wide of non-volatile signal and is folded the non-of sealing chip by non-volatility memorizer and wave
The property sent out memorizer number N determines, is defined as [(N/2-1): 0], and described bit wide just corresponding can revise N number of non-volatile holographic storage
The address of device maps.
On the other hand, the invention also discloses a kind of folded sealing chip processing method containing abnormal non-volatility memorizer, bag
Including PAD value definition non-volatility memorizer address mapping step, described method also includes:
Modified address mapping step: fold the tested confirmation of sealing chip when non-volatility memorizer and include the most non-volatile depositing
During reservoir, the address mapping to each single non-volatility memorizer is modified.
Preferably, also include:
Modified address maps non-volatile signal write step: modified address maps non-volatile signal and writes non-volatile depositing
Each non-volatility memorizer of sealing chip folded by reservoir, and described modified address maps non-volatile signal for remapping
New address write non-volatility memorizer folds each non-volatility memorizer of sealing chip；
Modified address mapping step: fold the tested confirmation of sealing chip when non-volatility memorizer and include the most non-volatile depositing
During reservoir, map non-volatile signal by modified address and the address mapping of each single non-volatility memorizer is repaiied
Change；Also include
Modified address maps non-volatile signal and enables step, and the enable signal being mapped non-volatile signal by modified address is made
Energy modified address maps the address of non-volatile modification of signal non-volatility memorizer and maps.
Preferably, described the non-volatile signal ground to each single non-volatility memorizer is mapped by modified address
Location maps modifies, it is characterised in that: the address of abnormal non-volatility memorizer is mapped the address becoming not using and maps,
And other the address of non-volatility memorizer of remapping, make non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyN
Multiple value is reduced to 2KMultiple value, N and K is natural integer, and N > K.
Preferably, the modified address that described modified address mapping step is used maps the enable signal of non-volatile signal
Selectivity signal, the most also includes that selectivity enables step: fold the tested confirmation of sealing chip when non-volatility memorizer and be as good as
Often during non-volatility memorizer, PAD value definition non-volatility memorizer address maps effectively, when non-volatility memorizer folded envelope core
When the tested confirmation of sheet includes abnormal non-volatility memorizer, it is invalid that PAD value definition non-volatility memorizer address maps, and enables
Modified address maps non-volatile signal and carrys out modified address mapping.
Preferably, mapping non-volatile signal write step in described modified address also includes:
Bit wide design procedure: before write modified address maps non-volatile signal, is pre-designed modified address and maps non-volatile
The bit wide of signal, non-volatility memorizer non-volatility memorizer number N folding sealing chip determines, is defined as N/2-1, described
Bit wide just corresponding can be revised the address of N number of non-volatility memorizer and map.
Compared with the existing method of background technology, the invention have the advantages that
Existing method relative to background technology: process will be scrapped containing the folded sealing chip of abnormal non-volatility memorizer,
For causing waste greatly, the present invention, will be every by folding the mapping of sealing chip modified address to containing abnormal non-volatility memorizer
Remapping in the address of one independent non-volatility memorizer, the capacity making this folded mounting is little by changing greatly, is continuing with, from
And improve the utilization rate of chip.
Accompanying drawing explanation
Fig. 1 is the structure chart of a kind of folded sealing chip processing means embodiment 1 containing abnormal non-volatility memorizer of the present invention；
Fig. 2 is the structure chart of a kind of folded sealing chip processing means embodiment 2 containing abnormal non-volatility memorizer of the present invention；
Fig. 3 is the structure chart of a kind of folded sealing chip processing means embodiment 3 containing abnormal non-volatility memorizer of the present invention；
Fig. 4 is the flow chart of a kind of folded sealing chip processing method embodiment 4 containing abnormal non-volatility memorizer of the present invention；
Fig. 5 is the flow chart of a kind of folded sealing chip processing method embodiment 5 containing abnormal non-volatility memorizer of the present invention；
Fig. 6 is before a kind of folded sealing chip processing method modified address containing abnormal non-volatility memorizer of the present invention maps,
Rear address number schematic diagram；
Fig. 7 is the flow chart of a kind of folded sealing chip processing method embodiment 6 containing abnormal non-volatility memorizer of the present invention.
Detailed description of the invention
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, real with concrete below in conjunction with the accompanying drawings
The present invention is further detailed explanation to execute mode.
One of core idea of the embodiment of the present invention is, by abnormal to some or several non-volatility memorizer or lost efficacy
Non-volatility memorizer fold sealing chip and processed and be used；Accordingly, with respect to the existing method of background technology, arrange
Modified address mapping block, comprise modified address and map the modified address of non-volatile signal and map non-volatile signal writing module
And modified address maps non-volatile signal and enables module, by each list folding sealing chip containing abnormal non-volatility memorizer
Only non-volatility memorizer modified address maps so that it is continued to use.
With reference to Fig. 1, it is shown that a kind of folded sealing chip processing means embodiment 1 containing abnormal non-volatility memorizer of the present invention
Structure chart, specifically may include that
PAD value definition non-volatility memorizer address mapping module 101, reflects for non-volatility memorizer is carried out address
Penetrate；
Modified address mapping block 102, folds the tested confirmation of sealing chip for non-volatility memorizer and includes the most non-waving
During the property sent out memorizer, the address mapping to each single non-volatility memorizer is modified.
The processing means of the present invention can apply to the modified address mapping process of various folded sealing chip, such as, non-volatile
Sealing chip folded by property memorizer, and non-volatility memorizer includes Nand Flash and Nor Flash etc..The most only with Nand
Flash illustrates as a example by folding sealing chip, and other memory chip refer to.
With 2NIndividual capacity is that to fold Feng Chengyi capacity be (2 for the non-volatility memorizer of mGNM) as a example by the folded sealing chip of G, N
For natural integer, determine to be folded the non-volatility memorizer number of envelope.By tradition address mapping method, non-by the definition of PAD value
Volatile storage address mapping module 101, solidifies the PAD that each non-volatility memorizer is relevant when folded sealing chip folds envelope
Value defines each non-volatility memorizer address, and its non-volatility memorizer address number is defined as successively the most from top to bottom
chip0,chip1,chip2…chip(2N-1)。
When non-volatility memorizer fold the tested confirmation of sealing chip include one or several abnormal non-volatility memorizer time,
Enable modified address mapping block 102, non-volatility memorizer is folded each single non-volatility memorizer of sealing chip
Address map modify.Amended non-volatility memorizer is folded sealing chip and can be continuing with.
With reference to Fig. 2, it is shown that a kind of folded sealing chip processing means embodiment 2 containing abnormal non-volatility memorizer of the present invention
Structure chart, specifically can include that PAD value defines non-volatility memorizer address mapping module 201, for depositing non-volatile
Reservoir carries out address mapping；Can also include:
Modified address mapping block 202, folds the tested confirmation of sealing chip for non-volatility memorizer and includes the most non-waving
During the property sent out memorizer, the address mapping to each single non-volatility memorizer is modified；Can also include:
Modified address maps non-volatile signal writing module 203, comprises modified address and map non-in said write module 203
The new address i.e. remapped of volatilization signal 2031, before folded envelope or folded test of being honored as a queen is found to have abnormal non-volatility memorizer
Time, write non-volatility memorizer folds each non-volatility memorizer of sealing chip, the non-volatile letter of described modified address mapping
Numbers 2031, map for the address of abnormal non-volatility memorizer is mapped the address being revised as not using, and remap it
His non-volatility memorizer address, makes non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyNMultiple value is reduced to 2K
Multiple value, N and K is natural integer, and N > K；Also include:
Modified address maps non-volatile signal and enables module 204, comprises modified address and map non-waving in described enable module
The enable signal 2041 signaled, the address mapping non-volatile modification of signal non-volatility memorizer for enabling modified address is reflected
Penetrate.
The present embodiment is relative to the difference of embodiment 1, adds modified address and maps non-volatile signal writing module
203 and modified address map non-volatile signal enable module 204, said write module 203 comprise modified address map non-volatile
Signal 2031, when non-volatility memorizer fold the tested confirmation of sealing chip include abnormal non-volatility memorizer time, start amendment
Address maps non-volatile signal and enables module 204, writes the amendment ground of each non-volatility memorizer before or after enabling folded envelope
Location maps non-volatile signal 2031, completes to map its modified address；Described modified address maps non-volatile signal 2031, is used for
The address of abnormal non-volatility memorizer is mapped the address being revised as not using map, and the non-volatile of other that remap
Storage address, makes non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyNMultiple value is reduced to 2KMultiple value.
With reference to Fig. 3, it is shown that a kind of folded sealing chip processing means embodiment 3 containing abnormal non-volatility memorizer of the present invention
Structure chart, specifically can include that PAD value defines non-volatility memorizer address mapping module 301, for depositing non-volatile
Reservoir carries out address mapping；Can also include:
Modified address mapping block 302, folds the tested confirmation of sealing chip for non-volatility memorizer and includes the most non-waving
During the property sent out memorizer, the address mapping that non-volatility memorizer is folded sealing chip is modified；Can also include:
Modified address maps non-volatile signal writing module 303, and said write module 303 comprises modified address and maps non-waving
Signal the 3031 new addresses i.e. remapped, before folded envelope or folded test of being honored as a queen is found to have abnormal non-volatility memorizer
Time, write non-volatility memorizer folds each non-volatility memorizer of sealing chip, the non-volatile letter of described modified address mapping
Numbers 3031, map for the address of abnormal non-volatility memorizer is mapped the address being revised as not using, and remap it
His non-volatility memorizer address, makes non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyNMultiple value is reduced to 2K
Multiple value, N and K is natural integer, and N > K；Also include:
Modified address maps non-volatile signal and enables module 304, comprises modified address and map non-waving in described enable module
The enable signal 3041 signaled, the address mapping non-volatile modification of signal non-volatility memorizer for enabling modified address is reflected
Penetrate；
Described enable signal 3041 is selectivity signal, and when non-volatility memorizer, to fold the tested confirmation of sealing chip without exception
During non-volatility memorizer, PAD value definition non-volatility memorizer address maps effectively, when non-volatility memorizer folds sealing chip
When tested confirmation includes abnormal non-volatility memorizer, it is invalid that PAD value definition non-volatility memorizer address maps, and enable is repaiied
Change of address maps non-volatile signal 3031 and carrys out modified address mapping；Described modified address maps non-volatile signal 3031, its bit wide
3032 are folded the non-volatility memorizer number 2 of sealing chip by non-volatility memorizerNIn N determine, be defined as [(N/2-1):
0], described bit wide just corresponding can revise the address mapping of N number of non-volatility memorizer.
The present embodiment is relative to the difference of embodiment 2, preferably defines modified address and maps non-volatile signal
Enabling signal 3041 is selectivity signal, when non-volatility memorizer folds sealing chip tested confirmation non-volatile holographic storage without exception
During device, PAD value definition non-volatility memorizer address maps effectively, in non-volatility memorizer folds the tested confirmation of sealing chip
During containing abnormal non-volatility memorizer, it is invalid that PAD value definition non-volatility memorizer address maps, and enables modified address and maps non-
Volatilization signal comes modified address and maps each non-volatility memorizer；Described modified address maps non-volatile signal 3031,
Its bit wide is folded the non-volatility memorizer number 2 of sealing chip by non-volatility memorizerNIn N determine, be defined as [(N/2-1):
0]。
Corresponding to aforementioned means embodiment 1, the invention also discloses a kind of folded envelope core containing abnormal non-volatility memorizer
Sheet processing method embodiment 4, with reference to Fig. 4, described method specifically may include that
PAD value definition non-volatility memorizer address mapping step 401, carries out address mapping to non-volatility memorizer；
Modified address mapping step 402, non-volatility memorizer is folded the tested confirmation of sealing chip and is included abnormal non-volatile
During memorizer, the address mapping to each single non-volatility memorizer is modified.
The processing method of the present invention can apply to the modified address mapping process of various folded sealing chip, such as, non-volatile
Sealing chip folded by property memorizer, and non-volatility memorizer includes Nand Flash and Nor Flash etc..The most only with Nand
Flash illustrates as a example by folding sealing chip, and other memory chip refer to.
With 2NIndividual capacity is that to fold Feng Chengyi capacity be (2 for the non-volatility memorizer of mGNM) as a example by the folded sealing chip of G, tool
Body ground, 22Individual capacity is that to fold Feng Chengyi capacity be (2 for the non-volatility memorizer of 2G2* 2) the folded sealing chip of the i.e. 8G of G.By tradition
Address mapping method, by PAD value definition non-volatility memorizer address mapping step 401, the solidification when folded sealing chip folded envelope
The PAD value that each non-volatility memorizer is relevant defines the device address of each non-volatility memorizer, the most from top to bottom
Its non-volatility memorizer address number is defined as chip0, chip1, chip2, chip 3 successively.
When non-volatility memorizer fold the tested confirmation of sealing chip include an abnormal non-volatility memorizer time, specifically
Ground, the non-volatility memorizer of corresponding chip0 address number is abnormal, by modified address mapping step 402, independent to each
The address of non-volatility memorizer map and modify, in the present embodiment, change into chip0 address number not using
Chip3, and change chip1 address into chip0, change chip2 address into chip1, change chip3 address into chip2.After amendment
Non-volatility memorizer fold sealing chip and can be continuing with, becoming a capacity is (22-1* 2) the folded sealing chip of the i.e. 4G of G.
With reference to Fig. 5, it is shown that a kind of folded sealing chip processing method embodiment 5 containing abnormal non-volatility memorizer of the present invention
Flow chart, specifically may include that
PAD value definition non-volatility memorizer address mapping step 501, carries out address mapping to non-volatility memorizer；
Can also include:
Modified address mapping step 502, non-volatility memorizer is folded the tested confirmation of sealing chip and is included abnormal non-volatile
During memorizer, the address mapping to each single non-volatility memorizer is modified；Also may be used before or after this step
To include:
Modified address maps non-volatile signal write step 503, the new address that said write step 503 will remap
I.e. modified address maps non-volatile signal 5031, before folded envelope or when folded test of being honored as a queen is found to have abnormal non-volatility memorizer,
Write non-volatility memorizer folds each non-volatility memorizer of sealing chip, and described modified address maps non-volatile signal
The address of abnormal non-volatility memorizer is mapped the address being revised as not using by 5031 to be mapped, and each non-volatile is deposited
Remap in the address of reservoir, make non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyNMultiple value is reduced to 2KMultiple
Value；Can also include:
Modified address maps non-volatile signal and enables step 504, and the enable being mapped non-volatile signal by modified address is believed
Numbers 5041, enable modified address and map the address of non-volatile modification of signal non-volatility memorizer and map.
The present embodiment is relative to the difference of embodiment 4, adds modified address and maps non-volatile signal write step
503 and modified address map non-volatile signal enable step 504, modified address is mapped non-volatile letter by said write step 503
Number before or after non-volatility memorizer folds the folded envelope of sealing chip, write each non-volatility memorizer, work as non-volatility memorizer
When the folded tested confirmation of sealing chip includes abnormal non-volatility memorizer, address mapping step 502 of modifying, this step comprises
Modified address maps non-volatile signal and enables step 504, and the modified address enabling each non-volatility memorizer maps non-waving
Signalling completes to map its modified address, and after modified address maps, the address of abnormal non-volatility memorizer maps and is modified as
Address for not using maps, and is remapped the address of each non-volatility memorizer, makes non-volatile depositing simultaneously
Reservoir folds the capacity of sealing chip by 2NMultiple value is reduced to 2KMultiple value.
See Fig. 6, with 2NIndividual capacity is that to fold Feng Chengyi capacity be (2 for the non-volatility memorizer of mGNM) the folded envelope core of G
As a example by sheet.First by tradition address mapping method, by PAD value definition non-volatility memorizer address mapping step 501, in folded envelope
Chip solidifies the relevant PAD value of each non-volatility memorizer and defines the address of each non-volatility memorizer when folding envelope,
Its non-volatility memorizer address number is defined as 0,1,2 successively the most from top to bottom ... .K ... M ... 2N-1, in the present embodiment just
Numbered chip0, the chip1 of corresponding non-volatility memorizer is called with non-volatility memorizer address number,
chip2…..chipK……chipM……chip(2N-1), chip0 i.e. address is the non-volatility memorizer of 0 ... ..chipK
It is the non-volatility memorizer that address is K ... ..chip (2N-1) i.e. address is (2N-1) non-volatility memorizer.
Then map non-volatile signal write step 503 by modified address, modified address is mapped non-volatile signal i.e.
The new address remapped, writes non-volatility memorizer before or after folded envelope and folds each non-volatile holographic storage of sealing chip
Device.If causing chip K and chip M abnormal for a certain reason during the folded test being honored as a queen or use, so folded envelope
Chip just cannot normally work.But, other non-volatility memorizer in addition to chip K and chip M is all normal
, we can utilize other non-volatility memorizer in addition to chip K and chip M to form a capacity less than (2N*
M) the folded sealing chip of G, such as capacity are (2N-1M) G, this non-volatile holographic storage being accomplished by rewriting each non-volatility memorizer
Device address, remaps the address of these non-volatility memorizers.
The method of non-volatility memorizer address of remapping is shown in Figure 6.First, one non-volatile signal of design
CHIP_AD, writes this signal in each chip, use it to redefine non-volatility memorizer address.Because chip is K
It is abnormal chips with chip M, by amendment chip K and above non-volatility memorizer chip (K+1) thereof ... chip N etc.
Non-volatility memorizer address, realize that non-volatility memorizer is folded sealing chip address and remap.By former chip K
The non-volatility memorizer address of (below chip K in Fig. 6) keeps constant below, and the address of former chip K changes to chip (2N -1), former chip K subtracts 1 successively with the non-volatility memorizer address of up to below chip M, and the address of former chip M changes to
chip(2N-1+ 1), former chip M is with up to chip (2N-1) chip address between+1 subtracts 2 successively, former chip (2N-1)+1 non-
Volatile storage address becomes chip (2N-1)-1, former chip (2N-1) more than+1 non-volatility memorizer address keeps not
Become.The most former chip0 to former chip (2N-1) just to have reformulated a capacity be (2 for non-volatility memorizer between+1N-1*m)G
Folded sealing chip, this folded sealing chip can be continuing with.chip(2N-1) more than+1 non-volatility memorizer is not in use by, ground
Location need not be revised.
With reference to Fig. 7, it is shown that a kind of folded sealing chip processing method embodiment 6 containing abnormal non-volatility memorizer of the present invention
Flow chart, specifically may include that
PAD value definition non-volatility memorizer address mapping step 601, carries out address mapping to non-volatility memorizer；
Can also include:
Modified address mapping step 602, non-volatility memorizer is folded the tested confirmation of sealing chip and is included abnormal non-volatile
During memorizer, the address mapping to each single non-volatility memorizer is modified；Also may be used before or after this step
To include:
Modified address maps non-volatile signal write step 603, and modified address is mapped non-volatile by said write step 603
The new address that signal 6031 i.e. remaps, before folded envelope or when folded test of being honored as a queen is found to have abnormal non-volatility memorizer,
Write non-volatility memorizer folds each non-volatility memorizer of sealing chip, and described modified address maps non-volatile signal
6031, map for the address of abnormal non-volatility memorizer is mapped the address being revised as not using, and remap other
Non-volatility memorizer address, make non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyNMultiple value is reduced to 2KTimes
Numerical value, N and K is natural integer, and N > K；Also include:
Modified address maps non-volatile signal and enables module 604, comprises modified address and map non-waving in described enable module
The enable signal 6041 signaled, the address mapping non-volatile modification of signal non-volatility memorizer for enabling modified address is reflected
Penetrate；
Described enable signal 6041 is selectivity signal, and when non-volatility memorizer, to fold the tested confirmation of sealing chip without exception
During non-volatility memorizer, PAD value definition non-volatility memorizer address maps effectively, when non-volatility memorizer folds sealing chip
When tested confirmation includes abnormal non-volatility memorizer, it is invalid that PAD value definition non-volatility memorizer address maps, and enable is repaiied
Change of address maps non-volatile signal 6031 and carrys out modified address mapping；
Described modified address maps non-volatile signal write step 603 and also includes:
Bit wide design procedure 6032, before write modified address maps non-volatile signal 6031, is pre-designed modified address and reflects
Penetrating the bit wide of non-volatile signal, its bit wide is folded the non-volatility memorizer number 2 of sealing chip by non-volatility memorizerNIn N
Determining, be defined as [(N/2-1): 0], described bit wide just corresponding can be revised the address of N number of non-volatility memorizer and map, i.e.
Described bit wide just corresponding can be revised the address of N number of non-volatility memorizer and map.
The present embodiment is relative to the difference of embodiment 5, maps non-volatile except preferably defining described modified address
The enable signal 6041 of signal is selectivity signal, and when non-volatility memorizer, to fold the tested confirmation of sealing chip without exception non-volatile
Property memorizer time, PAD value definition non-volatility memorizer address maps effectively, and when non-volatility memorizer, to fold sealing chip tested
When confirming to include abnormal non-volatility memorizer, it is invalid that PAD value definition non-volatility memorizer address maps, and enables modified address
Map non-volatile signal 6031 and carry out modified address mapping；Also map non-volatile signal write step 603 to add in modified address
Bit wide design procedure 605, design code modified address maps the bit wide of non-volatile signal 6031 by non-volatility memorizer number
N in 2N determines, is defined as [(N/2-1): 0].
See Fig. 6, with 2NIndividual capacity is that to fold Feng Chengyi capacity be (2 for the non-volatility memorizer of mGNM) the folded envelope core of G
As a example by sheet.First by tradition address mapping method, by PAD value definition non-volatility memorizer address mapping step 601, in folded envelope
Chip solidifies the relevant PAD value of each non-volatility memorizer and defines the non-volatile of each non-volatility memorizer when folding envelope
Property storage address, its non-volatility memorizer address number is defined as 0,1,2 successively the most from top to bottom ... K ... M ... (2N-
1), the present embodiment just calls the numbered of corresponding non-volatility memorizer with non-volatility memorizer address number
chip0,chip1,chip2…..chipK……chipM……chip(2N-1), chip0 be address be 0 non-volatile
Memorizer ... ..chipK is the non-volatility memorizer that non-volatility memorizer address is K ... ..chip (2N-1) be non-
Volatile storage address is (2N-1) non-volatility memorizer.
Cause chip K and chip M abnormal for a certain reason during the folded test being honored as a queen or use, so folded envelope
Chip just cannot normally work.But, other non-volatility memorizer in addition to chip K and chip M is all normal
, we can utilize other non-volatility memorizer in addition to chip K and chip M to form a capacity less than (2N*
M) the folded sealing chip of G, such as capacity are (2N-1M) G, this non-volatile holographic storage being accomplished by rewriting each non-volatility memorizer
Device address, remaps the non-volatility memorizer address of these non-volatility memorizers.The present embodiment is by amendment ground
Location maps non-volatile signal write step 603, modified address maps non-volatile signal 6031 and writes non-waving after folded envelope is tested
Each non-volatility memorizer of sealing chip folded by the property sent out memorizer.
The method of non-volatility memorizer address of remapping is shown in Figure 6.First, one non-volatile signal of design
CHIP_AD [(N/2-1): 0], bit wide [(N/2-1): 0] represents that the address that can revise N number of non-volatility memorizer maps, often
Individual non-volatility memorizer all writes this signal, uses it to redefine non-volatility memorizer address.Enable signal
CHIP_AD_EN is 1bit bit wide, as CHIP_AD_EN=0, effective with PAD definition non-volatility memorizer address；When
During CHIP_AD_EN=1, the non-volatility memorizer address of PAD definition, by invalid, uses CHIP_AD [(N/2-1): 0] to determine
Justice non-volatility memorizer address.The method being specifically defined sees embodiment 5.
Each embodiment in this specification all uses the mode gone forward one by one to describe, what each embodiment stressed is with
The difference of other embodiments, between each embodiment, identical similar part sees mutually.For embodiment of the method
For, due to itself and device embodiment basic simlarity, so describe is fairly simple, relevant part sees the portion of embodiment of the method
Defend oneself bright.
Above to a kind of folded sealing chip processing means containing abnormal non-volatility memorizer provided by the present invention and method,
Being described in detail, principle and the embodiment of the present invention are set forth by specific case used herein, above reality
The explanation executing example is only intended to help to understand method and the core concept thereof of the present invention；General technology simultaneously for this area
Personnel, according to the thought of the present invention, the most all will change, in sum, and this theory
Bright book content should not be construed as limitation of the present invention.
Claims (12)
1., containing a folded sealing chip processing means for abnormal non-volatility memorizer, described device includes that the definition of PAD value is non-volatile
Property storage address mapping block, it is characterised in that also include:
Modified address mapping block, folds the tested confirmation of sealing chip for non-volatility memorizer and includes abnormal non-volatile holographic storage
During device, the address mapping to each single non-volatility memorizer is modified.
2. device as claimed in claim 1, it is characterised in that also include that modified address maps non-volatile signal writing module,
Comprise modified address in said write module and map non-volatile signal, for the new address remapped is write non-volatile
Each non-volatility memorizer of sealing chip folded by memorizer；Also include:
Modified address maps non-volatile signal and enables module, comprises modified address and map non-volatile signal in described enable module
Enabling signal, the address mapping non-volatile modification of signal non-volatility memorizer for enabling modified address maps.
3. device as claimed in claim 2, it is characterised in that described modified address maps non-volatile signal, for by abnormal
The address of non-volatility memorizer maps the address being revised as not using and maps, and other the non-volatility memorizer of remapping
Address, make non-volatility memorizer fold the capacity of sealing chip by 2 simultaneouslyNMultiple value is reduced to 2KMultiple value, N and K is certainly
So integer, and N > K.
4. device as claimed in claim 2 or claim 3, it is characterised in that described modified address maps the enable letter of non-volatile signal
Number it is selectivity signal, when non-volatility memorizer folds sealing chip tested confirmation non-volatility memorizer without exception, PAD value
Definition non-volatility memorizer address maps effectively, folds the tested confirmation of sealing chip when non-volatility memorizer and includes the most non-waving
During the property sent out memorizer, it is invalid that PAD value definition non-volatility memorizer address maps, and enables the modified address non-volatile signal of mapping and comes
Modified address maps.
5. as claimed in claim 2 or claim 3 device, it is characterised in that described modified address map the bit wide of non-volatile signal by
Non-volatility memorizer is folded non-volatility memorizer number N of sealing chip and is determined, being defined as [(N/2-1): 0], described bit wide is just
The address that corresponding can revise well N number of non-volatility memorizer maps.
6. device as claimed in claim 4, it is characterised in that described modified address maps the bit wide of non-volatile signal and waved by non-
The property sent out memorizer is folded non-volatility memorizer number N of sealing chip and is determined, being defined as [(N/2-1): 0], described bit wide just can
Enough correspondences are revised the address of N number of non-volatility memorizer and are mapped.
7., containing a folded sealing chip processing method for abnormal non-volatility memorizer, define non-volatility memorizer including PAD value
Address mapping step, it is characterised in that described method also includes:
Modified address mapping step: fold the tested confirmation of sealing chip when non-volatility memorizer and include abnormal non-volatility memorizer
Time, the address mapping to each single non-volatility memorizer is modified.
8. method as claimed in claim 7, it is characterised in that also include:
Modified address maps non-volatile signal write step: modified address maps non-volatile signal write non-volatility memorizer
Each non-volatility memorizer of folded sealing chip, described modified address maps non-volatile signal for new by remap
Address write non-volatility memorizer folds each non-volatility memorizer of sealing chip；
Modified address mapping step: fold the tested confirmation of sealing chip when non-volatility memorizer and include abnormal non-volatility memorizer
Time, map non-volatile signal by modified address and the address mapping of each single non-volatility memorizer is modified；
Also include
Modified address maps non-volatile signal and enables step, and the enable signal enable being mapped non-volatile signal by modified address is repaiied
Change of address maps the address of non-volatile modification of signal non-volatility memorizer and maps.
9. method as claimed in claim 8, described map non-volatile signal by modified address and the most non-waves each
The address of the property sent out memorizer maps modifies, it is characterised in that: the address of abnormal non-volatility memorizer is mapped and becomes not
The address used maps, and other the address of non-volatility memorizer of remapping, and makes non-volatility memorizer fold simultaneously
The capacity of sealing chip is by 2NMultiple value is reduced to 2KMultiple value, N and K is natural integer, and N > K.
10. method as claimed in claim 8 or 9, it is characterised in that the amendment ground that described modified address mapping step is used
It is selectivity signal that location maps the enable signal of non-volatile signal, the most also includes that selectivity enables step: when non-volatile
When sealing chip tested confirmation non-volatility memorizer without exception folded by memorizer, PAD value definition non-volatility memorizer address is reflected
Penetrate effectively, when non-volatility memorizer fold the tested confirmation of sealing chip include abnormal non-volatility memorizer time, PAD value defines non-
It is invalid that volatile storage address maps, and enables the modified address non-volatile signal of mapping and carrys out modified address mapping.
11. methods as claimed in claim 8 or 9, it is characterised in that described modified address maps non-volatile signal write step
Also include:
Bit wide design procedure: before write modified address maps non-volatile signal, is pre-designed modified address and maps non-volatile signal
Bit wide, by non-volatility memorizer fold sealing chip non-volatility memorizer number N determine, be defined as N/2-1, described bit wide
The address that just corresponding can revise N number of non-volatility memorizer maps.
12. methods as claimed in claim 10, it is characterised in that described modified address maps non-volatile signal write step also
Including:
Bit wide design procedure: before write modified address maps non-volatile signal, is pre-designed modified address and maps non-volatile signal
Bit wide, by non-volatility memorizer fold sealing chip non-volatility memorizer number N determine, be defined as N/2-1, described bit wide
The address that just corresponding can revise N number of non-volatility memorizer maps.
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| CN101030167A (en) * | 2007-01-17 | 2007-09-05 | 忆正存储技术(深圳)有限公司 | Flash-memory zone block management |
| CN102122531A (en) * | 2011-01-27 | 2011-07-13 | 浪潮电子信息产业股份有限公司 | Method for improving stability in use of large-capacity solid state disk |
| US20130031296A1 (en) * | 2011-04-27 | 2013-01-31 | Seagate Technology Llc | System and method for managing address mapping information due to abnormal power events |
| CN103325423A (en) * | 2012-03-20 | 2013-09-25 | 上海华虹Nec电子有限公司 | Data automatically-comparing test circuit of non-volatile memory |
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