CN103324593A - PCI Express data transmission control method based on FPGA (field programmable gate array) - Google Patents
PCI Express data transmission control method based on FPGA (field programmable gate array) Download PDFInfo
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- CN103324593A CN103324593A CN2013102624626A CN201310262462A CN103324593A CN 103324593 A CN103324593 A CN 103324593A CN 2013102624626 A CN2013102624626 A CN 2013102624626A CN 201310262462 A CN201310262462 A CN 201310262462A CN 103324593 A CN103324593 A CN 103324593A
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Abstract
The invention discloses a PCI Express data transmission control method based on FPGA (field programmable gate array). The method includes the steps of S1, inputting a clock signal and a reset signal; S2, changing the state of a state machine into master and executing data exchange request allowance, new data transmission allowance and beat counter 1 setting when a reset signal input wire is in high level; S3, allowing for data transmission, inspecting the state of a data transmission interface, configuring a slave module to transmit, controlling a data transmission mode, executing data transmission and counting with the beat counter; S4, changing the data transmission mode into a transmission termination mode; and S5, changing the state of the state machine into slave when the reset signal input wire is in low level. The method has the advantages that data transmission speed is high, data width of interfaces is customizable, the interfaces occupy no memory in terms of drive and equipment, and running speed of both drive and equipment is unaffected.
Description
Technical field
The present invention relates to a kind of PCI Express data transfer control method based on FPGA.
Background technology
FPGA(Field-Programmable Gate Array), it is field programmable gate array, occur as a kind of semi-custom circuit in special IC (ASIC) field, both solved the deficiency of custom circuit, overcome the limited shortcoming of original programming device gate circuit number again.With traditional logic circuit and gate array (as PAL, GAL and CPLD device) compare, FPGA has different structures, FPGA utilizes small-sized look-up table, and (16 * 1RAM) realize combinational logic, each look-up table is connected to the input end of a d type flip flop, trigger drives other logical circuits again or drives I/O, constituted the basic logic unit module that not only can realize combination logic function but also can realize the sequential logic function thus, these intermodules utilize metal connecting line to be connected to each other or are connected to the I/O module.The logic of FPGA realizes by loading programming data to inner static storage cell, being stored in value in the memory cell has determined between the logic function of logical block and each module or the connecting mode between module and I/O, and final decision the FPGA function that can realize, FPGA allows unlimited programming.
Utilize FPGA to realize that the maximum reason of PCI Express is its reconfigurability.To this new technology of PCI Express, specification is in the stage of continuous variation, when specification changes, by reconfigurability can be corresponding change, the upgrading that software programming realizes version is carried out in former design.Adopt the built-in high-speed transceiver module of some FPGA and programmable structure, Virtex series as Xilinx, its built-in high-speed transceiver (Rocket IOTMGTP transceiver) can be supported the 2.5Gbps speed that PCI Express agreement is required, the 8B/10B encoding and decoding can be extracted clock reliably from data, realize clock recovery, can reduce cost and difficulty, reduce design difficulty and cycle.
The concrete technology of Data Transmission Controlling that the transport layer of disclosed PIPE Core is seldom arranged in the market, there is following problem in some known control technologys at present:
1, speed is not high, and the exchanges data speed of host driver and equipment room only can reach 150MBytes/s;
2, interface difference, what the product on the market adopted is the structure that records the controll block of transmission both sides' start address and length, be characterized in that adaptability is better, but 3 shortcomings are arranged: 1) data width of interface is not enough, does not meet the requirement of my company's product Large Volume Data transmission; 2) interface will drive and equipment on committed memory, do not meet the requirement that my company's product data are transmitted; 3) setup time long, remote effect speed;
3, extendability is poor, only can use the FPGA internal RAM, can not use various internal memories easily.
Summary of the invention
The objective of the invention is to overcome the deficiencies in the prior art, a kind of data rate height is provided, and the data width of interface can be self-defined, meets the requirement of Large Volume Data transmission, interface drive and equipment on committed memory not, do not influence the work efficiency of driving and equipment; Transmission control setup time weak point, a kind of PCI Express data transfer control method based on FPGA of raising transmission speed.
The objective of the invention is to be achieved through the following technical solutions: a kind of PCI Express data transfer control method based on FPGA, it may further comprise the steps:
S1: input clock signal clock and reset signal reset;
S2: if reset reset signal input line is high level, then state machine state becomes master, and carries out following operation:
S201 allows data exchange request;
S202 allows new round data transmission;
S203: beat count device zero clearing;
S3: after allowing to carry out data transmission, the following operation of response at once, state machine state keeps the master state in this process:
S301: check whether the data transmission interface state has one or more data transfer request, if a plurality of data transfer request are arranged, then begin response from the highest level request;
S302: the slave module that configuration will be transmitted;
S303: data-transmission mode control;
S304: carry out data transmission;
S305: rhythmic meter rolling counters forward;
S4: after data transmission was finished, data-transmission mode became the end transmission mode, the end data transmission;
S5:reset reset signal input line is after the low level, and state machine responds slave input control operation at once, is converted into the slave state, carries out following operation:
The S501:slave state arranges;
S502: the operation of passive other master of execution, but do not count, also translation data transmission mode not.
The control of data-transmission mode among the described step S303 comprises that forms data transmission, incremental transmission, 4 clap transmission, 4 and clap incremental transmission, 8 and clap transmission, 8 and clap incremental transmission, 16 and clap transmission, 16 and clap in the incremental transmission any one.
The invention has the beneficial effects as follows:
1, data rate height, the exchanges data speed of host driver and equipment room can reach 172MBytes/s, even the RAM interface variation also can keep transmission speed not change;
2, the data width of interface can be self-defined, meets the requirement of Large Volume Data transmission, interface drive and equipment on committed memory not, do not influence the travelling speed of driving and equipment; Transmission control setup time weak point improves transmission speed;
3, favorable expandability can not only be used the FPGA internal RAM, also can use various internal memories easily.
Description of drawings
Fig. 1 is control method process flow diagram of the present invention.
Embodiment
Further specify technical scheme of the present invention below in conjunction with accompanying drawing, but the content that the present invention protects is not limited to the following stated.
As shown in Figure 1, a kind of PCI Express data transfer control method based on FPGA, it may further comprise the steps:
S1: input clock signal clock and reset signal reset;
S2: if reset reset signal input line is high level, then state machine state becomes master, and carries out following operation:
S201 allows data exchange request;
S202 allows new round data transmission;
S203: beat count device zero clearing;
S3: after allowing to carry out data transmission, the following operation of response at once, state machine state keeps the master state in this process:
S301: check whether the data transmission interface state has one or more data transfer request, if a plurality of data transfer request are arranged, then begin response from the highest level request;
S302: the slave module that configuration will be transmitted;
S303: data-transmission mode control;
S304: carry out data transmission;
S305: rhythmic meter rolling counters forward;
S4: after data transmission was finished, data-transmission mode became the end transmission mode, the end data transmission;
S5:reset reset signal input line is after the low level, and state machine responds slave input control operation at once, is converted into the slave state, carries out following operation:
The S501:slave state arranges;
S502: the operation of passive other master of execution, but counter do not count, also translation data transmission mode not.
The control of data-transmission mode among the described step S303 comprises that forms data transmission, incremental transmission, 4 clap transmission, 4 and clap incremental transmission, 8 and clap transmission, 8 and clap incremental transmission, 16 and clap transmission, 16 and clap in the incremental transmission any one.
Claims (2)
1. PCI Express data transfer control method based on FPGA, it is characterized in that: it may further comprise the steps:
S1: input clock signal clock and reset signal reset;
S2: if reset reset signal input line is high level, then state machine state becomes master, and carries out following operation:
S201 allows data exchange request;
S202 allows new round data transmission;
S203: beat count device zero clearing;
S3: after allowing to carry out data transmission, the following operation of response at once, state machine state keeps the master state in this process:
S301: check whether the data transmission interface state has one or more data transfer request, if a plurality of data transfer request are arranged, then begin response from the highest level request;
S302: the slave module that configuration will be transmitted
S303: data-transmission mode control;
S304: carry out data transmission;
S305: rhythmic meter rolling counters forward;
S4: after data transmission was finished, data-transmission mode became the end transmission mode, the end data transmission;
S5:reset reset signal input line is after the low level, and state machine responds slave input control operation at once, is converted into the slave state, carries out following operation:
The S501:slave state arranges;
S502: the operation of passive other master of execution, but do not count, also translation data transmission mode not.
2. a kind of PCI Express data transfer control method based on FPGA according to claim 1 is characterized in that: the data-transmission mode control among the described step S303 comprises that forms data transmission, incremental transmission, 4 clap transmission, 4 and clap incremental transmission, 8 and clap transmission, 8 and clap incremental transmission, 16 and clap transmission, 16 and clap in the incremental transmission any one.
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| CN2013102624626A CN103324593A (en) | 2013-06-27 | 2013-06-27 | PCI Express data transmission control method based on FPGA (field programmable gate array) |
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| CN2013102624626A CN103324593A (en) | 2013-06-27 | 2013-06-27 | PCI Express data transmission control method based on FPGA (field programmable gate array) |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6101132A (en) * | 1999-02-03 | 2000-08-08 | Xilinx, Inc. | Block RAM with reset |
| US6282127B1 (en) * | 1999-02-03 | 2001-08-28 | Xilinx, Inc. | Block RAM with reset to user selected value |
| US6496045B1 (en) * | 2001-08-28 | 2002-12-17 | Xilinx, Inc. | Programmable even-number clock divider circuit with duty cycle correction and optional phase shift |
| CN101158932A (en) * | 2007-08-31 | 2008-04-09 | 上海广电（集团）有限公司中央研究院 | Method for accessing on-site programmable gate array internal memory through I*C interface |
| CN101854353A (en) * | 2010-04-28 | 2010-10-06 | 国网电力科学研究院 | Multi-chip parallel encryption method based on FPGA |
| CN102664902A (en) * | 2012-05-15 | 2012-09-12 | 南京华兴数控技术有限公司 | Hardware implementing method for kernels of POWERLINK communication protocol master and slave stations |
-
2013
- 2013-06-27 CN CN2013102624626A patent/CN103324593A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6101132A (en) * | 1999-02-03 | 2000-08-08 | Xilinx, Inc. | Block RAM with reset |
| US6282127B1 (en) * | 1999-02-03 | 2001-08-28 | Xilinx, Inc. | Block RAM with reset to user selected value |
| US6496045B1 (en) * | 2001-08-28 | 2002-12-17 | Xilinx, Inc. | Programmable even-number clock divider circuit with duty cycle correction and optional phase shift |
| CN101158932A (en) * | 2007-08-31 | 2008-04-09 | 上海广电（集团）有限公司中央研究院 | Method for accessing on-site programmable gate array internal memory through I*C interface |
| CN101854353A (en) * | 2010-04-28 | 2010-10-06 | 国网电力科学研究院 | Multi-chip parallel encryption method based on FPGA |
| CN102664902A (en) * | 2012-05-15 | 2012-09-12 | 南京华兴数控技术有限公司 | Hardware implementing method for kernels of POWERLINK communication protocol master and slave stations |
Non-Patent Citations (3)
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| 丰平等: "只从并行状态机用于复杂FPGA控制系统设计", 《微计算机应用》 * |
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