CN103324593A - PCI Express data transmission control method based on FPGA (field programmable gate array) - Google Patents

PCI Express data transmission control method based on FPGA (field programmable gate array) Download PDF

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CN103324593A
CN103324593A CN 201310262462 CN201310262462A CN103324593A CN 103324593 A CN103324593 A CN 103324593A CN 201310262462 CN201310262462 CN 201310262462 CN 201310262462 A CN201310262462 A CN 201310262462A CN 103324593 A CN103324593 A CN 103324593A
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data transmission
transmission
data
state
fpga
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CN 201310262462
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Chinese (zh)
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吴伟林
李承镛
杨宇航
黄耀
何戎辽
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成都林海电子有限责任公司
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Abstract

The invention discloses a PCI Express data transmission control method based on FPGA (field programmable gate array). The method includes the steps of S1, inputting a clock signal and a reset signal; S2, changing the state of a state machine into master and executing data exchange request allowance, new data transmission allowance and beat counter 1 setting when a reset signal input wire is in high level; S3, allowing for data transmission, inspecting the state of a data transmission interface, configuring a slave module to transmit, controlling a data transmission mode, executing data transmission and counting with the beat counter; S4, changing the data transmission mode into a transmission termination mode; and S5, changing the state of the state machine into slave when the reset signal input wire is in low level. The method has the advantages that data transmission speed is high, data width of interfaces is customizable, the interfaces occupy no memory in terms of drive and equipment, and running speed of both drive and equipment is unaffected.

Description

—种基于FPGA的PCI Express数据传输控制方法 - Species PCI Express data transmission controlling method based on FPGA

技术领域 FIELD

[0001] 本发明涉及一种基于FPGA的PCI Express数据传输控制方法。 [0001] The present invention relates to a data transmission controlling method PCI Express FPGA-based.

背景技术 Background technique

[0002] FPGA (Field — Programmable Gate Array),即现场可编程门阵列,作为专用集成电路(ASIC)领域中的一种半定制电路而出现,既解决了定制电路的不足,又克服了原有可编程器件门电路数有限的缺点。 [0002] FPGA (Field - Programmable Gate Array), a field programmable gate array, i.e., as an application specific integrated circuit (ASIC) in the field of a semi-custom circuit occurs, not only solves the problem custom circuits, but also to overcome the existing limited number of programmable devices gates disadvantages. 与传统逻辑电路和门阵列(如PAL, GAL及CPLD器件)相t匕,FPGA具有不同的结构,FPGA利用小型查找表(16X 1RAM)来实现组合逻辑,每个查找表连接到一个D触发器的输入端,触发器再来驱动其他逻辑电路或驱动1/0,由此构成了既可实现组合逻辑功能又可实现时序逻辑功能的基本逻辑单元模块,这些模块间利用金属连线互相连接或连接到I/O模块。 And the conventional gate array logic circuit (e.g., PAL, GAL and CPLD device) with t dagger, FPGA having different structures, FPGA use of small lookup tables (16X 1RAM) to implement combinational logic, each connected to a D flip-flop lookup table input of flip-flop again drives or drive other logic circuits 1/0, thereby constituting a combinational logic functions can achieve while achieving a basic logic unit module sequential logic functions among the modules connected to each other by metal wires or connection to I / O module. FPGA的逻辑是通过向内部静态存储单元加载编程数据来实现的,存储在存储器单元中的值决定了逻辑单元的逻辑功能以及各模块之间或模块与I/O间的联接方式,并最终决定了FPGA所能实现的功能,FPGA允许无限次的编程。 FPGA logic is implemented by loading the program data to the internal static memory cell, the value stored in the memory unit determines the connection mode between or modules and I / O between the logic functions of logic cells and modules, and the final decision FPGA can realize the function, FPGA allowing an unlimited number of programming.

[0003] 利用FPGA来实现PCI Express的最大理由是它的可重构性。 [0003] the biggest reason for the use of FPGA to implement PCI Express is its reconstruction. 对PCI Express这种新技术,规格处在不断变化的阶段,当规格变更时,通过可重构性可对应的更改,对原设计进行软件编程来实现版本的升级。 This new technology for PCI Express specifications in a changing phase, when specifications change, through reconfiguration can be corresponding changes to the original design software program to upgrade version. 采用一些FPGA内置高速收发器模块和可编程结构,如Xilinx的Virtex系列,其内置高速收发器(Rocket 10TMGTP收发器)可以支持PCIExpress协议所需的2.5Gbps速率,8B / IOB编解码能从数据中可靠地提取时钟,实现时钟恢复,可以降低成本和难度,减少设计难度和周期。 Use some internal high-speed FPGA transceiver module and a programmable structure, such as the Xilinx Virtex family, which internal high-speed transceiver (Rocket 10TMGTP transceiver) may be needed to support a rate of 2.5Gbps PCIExpress protocol, 8B / IOB data from codec extracted clock reliably achieve clock recovery, it can reduce the cost and difficulty, the difficulty of the design and reduce the cycle.

[0004]目前市场上很少有公开的PIPE Core的传输层的数据传输控制具体的技术,目前已知的一些控制技术存在以下问题: [0004] There are few disclosed on the market data transport layer PIPE Core specific control technique, the following problems, some known control techniques:

1、速度不高,主机驱动程序和设备间的数据交换速度仅能达到150MBytes/s ; 1, the speed is not high, the speed of data exchange between the host drivers and the device can only reach 150MBytes / s;

2、接口不同,市场上的产品采用的是记录有传输双方起始地址和长度的控制块的结构,其特点是适应性较好,但是有3个缺点:1)接口的数据宽度不够,不符合我公司产品大容量数据传输的要求;2)接口要在驱动和设备上占用内存,不符合我公司产品数据传输的要求;3)准备时间长,间接影响了速度; 2, different interfaces, products on the market is used in the transmission control block structure is recorded both the start address and length, which is characterized by better adaptability, but has three disadvantages: 1) the interface data width is not enough, not our products meet the high-capacity data transmission requirements; 2) the interface takes up memory on the drive and equipment, our products do not meet the requirements for data transmission; 3) preparing for a long time, indirectly affect the speed;

3、扩展性差,仅能使用FPGA内部RAM,不能方便地使用各种内存。 3, poor scalability, only the FPGA internal RAM, can not easily use various kinds of memory.

发明内容 SUMMARY

[0005] 本发明的目的在于克服现有技术的不足,提供一种数据传输速度高,接口的数据宽度可自定义,符合大容量数据传输的要求,接口在驱动和设备上不占用内存,不影响驱动和设备的工作效率;传输控制准备时间短,提高传输速度的一种基于FPGA的PCI Express数据传输控制方法。 [0005] The object of the present invention is to overcome the disadvantages of the prior art, there is provided a data transmission speed is high, the width of the data interface can be customized to meet the requirements of large-capacity data transmission, and the interface on the driving device does not occupy memory, not Effect of driving efficiency and equipment; transmission control preparation time is short, the speed increase for transmitting PCI Express data transmission controlling method based on FPGA.

[0006] 本发明的目的是通过以下技术方案来实现的:一种基于FPGA的PCI Express数据传输控制方法,它包括以下步骤: [0006] The object of the present invention is achieved by the following technical solutions: An FPGA-based PCI Express data transmission controlling method, comprising the steps of:

S1:输入时钟信号clock和复位信号reset ;52:如果reset复位信号输入线为高电平,则状态机状态变为master,并执行以下操 S1: the input clock signal CLOCK and reset signal reset; 52: reset if the reset signal input line is high, the state machine changes to master, and performs the following operations

作: As:

S201允许数据交换请求; S201 allows data exchange request;

S202允许新一轮数据传输; S202 allows a new data transmission;

S203:节拍计数器清零; S203: the beat counter is cleared;

53:允许进行数据传输后,立刻响应以下操作,此过程中状态机状态保持master状态: 53: After allowing data transmission immediately in response to the following operations, the process remains master state machine state:

5301:检查数据传输接口状态是否有一个或多个数据传输请求,若有多个数据传输请求,贝1J从最高级别请求开始响应; 5301: Check if there is data transfer interface state of one or more data transfer requests, if a plurality of data transfer requests, in response to requests start 1J shellfish from the highest level;

5302:配置要传输的slave模块; 5302: the configuration of slave modules to be transmitted;

5303:数据传输模式控制; 5303: control data transfer mode;

5304:执行数据传输; 5304: performing data transfer;

5305:节拍计数器计数; 5305: beat counter;

54:数据传输完成后,数据传输模式变为结束传输模式,结束数据传输; 54: After the data transfer is completed, the data transfer mode to the transmission mode ends, end of data transfer;

55:reset复位信号输入线为低电平以后,状态机立刻响应slave输入控制操作,转化为slave状态,执行以下操作: 55: reset after the reset signal input line is low, the slave state machine in response to an input control operation immediately converted to slave status, perform the following operations:

5501:slave状态设置; 5501: slave state setting;

5502:被动执行其他master的操作,但不计数,也不转换数据传输模式。 5502: the master operation for other passive, but does not count, does not switch the data transmission mode.

[0007] 所述的步骤S303中的数据传输模式控制包括单数据传输、增量传输、4拍传输、4拍增量传输、8拍传输、8拍增量传输、16拍传输、16拍增量传输中的任意一种。 [0007] The data transmission mode in step S303, the control data comprises a single transmission, an incremental transmission, the transmission 4 shoot, shoot incremental transmission 4, the transmission pat 8, 8-beat incrementing the transmission, the transmission pat 16, 16 shot by the amount of any one transmission.

[0008] 本发明的有益效果是: [0008] Advantageous effects of the present invention are:

1、数据传输速度高,主机驱动程序和设备间的数据交换速度能达到172MBytes/s,即使RAM接口变化也能保持传输速度不变化; 1, a high data transfer rate, the speed of data exchange between the host and the device driver can reach 172MBytes / s, even if the RAM interface transmission speed change can be kept unchanged;

2、接口的数据宽度可自定义,符合大容量数据传输的要求,接口在驱动和设备上不占用内存,不影响驱动和设备的运行速度;传输控制准备时间短,提高传输速度; 2, the width of the data interface can be customized to meet the requirements of large-capacity data transmission, the drive interface and memory for the device is not, and does not affect the operating speed of the driving apparatus; controlling transmission of short preparation time, increase the transmission speed;

3、扩展性好,不仅能使用FPGA内部RAM,也能方便地使用各种内存。 3, scalability, not only can use the FPGA internal RAM, can easily use various memory.

附图说明 BRIEF DESCRIPTION

[0009] 图1为本发明的控制方法流程图。 [0009] FIG. 1 is a flowchart of a control method of the present invention.

具体实施方式 detailed description

[0010] 下面结合附图进一步说明本发明的技术方案,但本发明所保护的内容不局限于以下所述。 [0010] The following further illustrate the technical solutions of the present invention in conjunction with the accompanying drawings, but the present invention is protected by the content is not limited to the following.

[0011] 如图1所示,一种基于FPGA的PCI Express数据传输控制方法,它包括以下步骤: [0011] As shown in FIG. 1, based on FPGA PCI Express data transmission controlling method, comprising the steps of:

51:输入时钟信号clock和复位信号reset ; 51: the input clock signal CLOCK and reset signal RESET;

52:如果reset复位信号输入线为高电平,则状态机状态变为master,并执行以下操 52: reset if the reset signal input line is high, the state machine changes to master, and performs the following operations

作: As:

S201允许数据交换请求; S201 allows data exchange request;

S202允许新一轮数据传输; S202 allows a new data transmission;

S203:节拍计数器清零;53:允许进行数据传输后,立刻响应以下操作,此过程中状态机状态保持master状态: S203: tick counter is cleared; 53: After allowing data transmission immediately in response to the following operations, the process remains master state machine state:

5301:检查数据传输接口状态是否有一个或多个数据传输请求,若有多个数据传输请求,贝1J从最高级别请求开始响应; 5301: Check if there is data transfer interface state of one or more data transfer requests, if a plurality of data transfer requests, in response to requests start 1J shellfish from the highest level;

5302:配置要传输的slave模块; 5302: the configuration of slave modules to be transmitted;

5303:数据传输模式控制; 5303: control data transfer mode;

5304:执行数据传输; 5304: performing data transfer;

5305:节拍计数器计数; 5305: beat counter;

54:数据传输完成后,数据传输模式变为结束传输模式,结束数据传输; 54: After the data transfer is completed, the data transfer mode to the transmission mode ends, end of data transfer;

55:reset复位信号输入线为低电平以后,状态机立刻响应slave输入控制操作,转化为slave状态,执行以下操作: 55: reset after the reset signal input line is low, the slave state machine in response to an input control operation immediately converted to slave status, perform the following operations:

5501:slave状态设置; 5501: slave state setting;

5502:被动执行其他master的操作,但计数器不计数,也不转换数据传输模式。 5502: the master operation for other passive, but the counter is not counting, data transmission mode is not switched.

[0012] 所述的步骤S303中的数据传输模式控制包括单数据传输、增量传输、4拍传输、4拍增量传输、8拍传输、8拍增量传输、16拍传输、16拍增量传输中的任意一种。 [0012] Data transmission mode in step S303, the control data comprises a single transmission, an incremental transmission, the transmission 4 shoot, shoot incremental transmission 4, the transmission pat 8, 8-beat incrementing the transmission, the transmission pat 16, 16 shot by the amount of any one transmission.

Claims (2)

  1. 1.一种基于FPGA的PCI Express数据传输控制方法,其特征在于:它包括以下步骤: 51:输入时钟信号clock和复位信号reset ; 52:如果reset复位信号输入线为高电平,则状态机状态变为master,并执行以下操作: S201允许数据交换请求; S202允许新一轮数据传输; S203:节拍计数器清零; 53:允许进行数据传输后,立刻响应以下操作,此过程中状态机状态保持master状态: 5301:检查数据传输接口状态是否有一个或多个数据传输请求,若有多个数据传输请求,贝1J从最高级别请求开始响应; 5302:配置要传输的slave模块5303:数据传输模式控制; 5304:执行数据传输; 5305:节拍计数器计数; 54:数据传输完成后,数据传输模式变为结束传输模式,结束数据传输; 55:reset复位信号输入线为低电平以后,状态机立刻响应slave输入控制操作,转化为slave状态,执行以下操作: 5501:slave状态设置; 5502:被动 An FPGA-based PCI Express data transmission control method characterized in that: it comprises the steps of: 51: the input clock signal CLOCK and reset signal reset; 52 is: If the reset signal reset input line is high, the state machine state to a master, and performs the following operations: allowing data exchange request S201; S202 allows a new data transmission; S203: tick counter is cleared; 53: after allowing data transmission immediately in response to the operation, during which state machine holding the state of master: 5301: check if there is data transfer interface state of one or more data transfer requests, if a plurality of data transfer requests, 1J shell from the highest level in response to the start request; 5302: the configuration of slave modules to be transmitted 5303: data transmission mode control; 5304: performing data transmission; 5305: beat counter; 54: after the data transfer is completed, the data transfer mode to the transmission mode ends, end of data transfer; 55: reset after the reset signal input line is low, the state machine immediately in response to an input control slave operation, into slave state, perform the following operations: 5501: slave state setting; 5502: passive 行其他master的操作,但不计数,也不转换数据传输模式。 Other operations master line, but does not count, does not switch the data transmission mode.
  2. 2.根据权利要求1所述的一种基于FPGA的PCI Express数据传输控制方法,其特征在于:所述的步骤S303中的数据传输模式控制包括单数据传输、增量传输、4拍传输、4拍增量传输、8拍传输、8拍增量传输、16拍传输、16拍增量传输中的任意一种。 According to one of the claims 1 to PCI Express data transmission controlling method based on FPGA, characterized in that: said data transmission mode in step S303, the data transmission control comprises a single incremental transmission, the transmission pat 4, 4 Sign incremental transmission, the transmission pat 8, 8-beat incrementing the transmission, the transmission pat 16, and 16 beats any incremental transmission.
CN 201310262462 2013-06-27 2013-06-27 PCI Express data transmission control method based on FPGA (field programmable gate array) CN103324593A (en)

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