CN103324462A - True random number generation system - Google Patents
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- CN103324462A CN103324462A CN2013101976628A CN201310197662A CN103324462A CN 103324462 A CN103324462 A CN 103324462A CN 2013101976628 A CN2013101976628 A CN 2013101976628A CN 201310197662 A CN201310197662 A CN 201310197662A CN 103324462 A CN103324462 A CN 103324462A
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Abstract
The invention provides a true random number generation system. The true random number generation system comprises a clock signal input interface unit, a phase locked loop module, a frequency divider, a D flip-flop for sampling, a metastable state eliminating module, an m-bit shift line and a random number output interface unit, wherein the phase locked loop module comprises a phase locked loop and a multipath disturbance line, and the multipath disturbance line is provided with m pairs of forward control terminals and reverse control terminals. According to the true random number generation system, the multipath disturbance line is additionally arranged in a feedback branch of the phase locked loop module on the basis of the fact that the phase locked loop already can generate random Jitter and accordingly generate random numbers, further, the disturbance size of the multipath disturbance line is also controlled by a random number sequence generated by the system, namely, the output already containing the random Jitter of the phase locked loop is subjected to a random disturbance again, so that the phase locked loop has difficulty in completing locking to result in the increase of the Jitter, and the randomness is greatly enhanced.
Description
Technical field
The present invention relates to the true random number generation systems.
Background technology
Random number has important application at numerous areas such as data statistics, information security and encryption, channel simulator, system simulations, and along with the development of electronic information technology, random number generating chip or circuit are more and more extensive in the application of integrated circuit fields.Random number is divided into two kinds of pseudo random number and true random numbers according to the difference of genesis mechanism.Wherein pseudo random number is according to some algorithms, and in conjunction with a series of numerals that are difficult to find rule of random seed generation, and true random number is to utilize some physics effects, a series of numerals that do not have mathematical law of generation.According to the present situation of present Information Technology Development, pseudo random number more and more is difficult to the requirement of reply " unpredictability ", so the generation of true random number and application become more and more important.So the true random number circuit for generating becomes the focus of research on true random number generating chip or the integrated circuit (IC) chip.
The generation of true random number must rely on physical process, and the generation of the true random number in circuit also must rely on some physical processes that have random character in the circuit, utilizes the structure in the circuit, and the method for generation of true random number has three classes on the typical sheet, comprising:
1) direct amplifying method: the random thermonoise that utilizes resistance in the circuit or other elements to exist above, it is amplified processing, compare rear acquisition random number sequence by comparer;
2) vibration sampling method: utilize some with the oscillator generation high-frequency oscillation signal of larger Jitter, and utilize the clock of lower frequency that the output of this oscillator is sampled, because the level state of high frequency oscillator when the low-frequency clock edge is uncertain, therefore can obtain random series;
3) discrete time chaos method: utilize chaos circuit unpredictable and to the dependent characteristics generation random series of starting condition sensitivity.
Directly amplifying method generation random number need to be used the devices such as amplifier, electric capacity, inductance, and power consumption is large, and high to voltage request.And based on vibration sampling method and discrete time chaos method, can utilize at present the logic gate chip to make up that the typical stochastic source of real random number generator has two kinds on the sheet: a kind of is to utilize digital logic gate to make up the high-speed digital circuit oscillator, and another kind is to utilize the shake above the dagital clock signal that analog PLL (phaselocked loop) circuit occurs to make up random quantity.Utilize the method for digital logic gate structure high-speed digital circuit oscillator comparatively simple, but very high to the chip circuit performance requirement, circuit power consumption is very large, and the chip life-span is very short; And based on the method for analog PLL (phaselocked loop) circuit, complex structure, design difficulty is high.And the randomness of the random number that these two kinds of methods produce is still not undesirable.
Summary of the invention
For solving the undesirable technical matters of random number randomness that existing true random number generating means power consumption is large, produce, the invention provides a kind of true random number generation systems, comprise master clock signal input interface unit, phase-locked loop module, frequency divider, sampling d type flip flop, metastable state cancellation module, m displacement bit line and random number output interface unit, the phase-locked loop module comprises phase-locked loop circuit and multichannel wavelet, and the multichannel wavelet has m to forward control end and reverse control end; The output one tunnel of master clock signal input interface unit is as the input of frequency divider, and another road is connected with the input of phase-locked loop circuit; The output of phase-locked loop circuit is connected with the input of multichannel wavelet, and the output one tunnel of multichannel wavelet is as the feed back input of phase-locked loop circuit, and another road is as the input of sampling with d type flip flop; The output of frequency divider is as the clock of sampling with d type flip flop; Sampling is connected with the input of metastable state cancellation module with the output of d type flip flop, and the output one tunnel of metastable state cancellation module is connected with the input of m displacement bit line; I position in the m displacement bit line export one the tunnel as i corresponding in the multichannel wavelet to forward control end and the reverse forward control end in the control end, another road is as corresponding oppositely control end; Another road of metastable state cancellation module output inputs to random number output interface unit; I=1 wherein, 2,3 ..., m.
Adopt technical scheme of the present invention, beat utilizing phase-locked loop circuit itself just can produce random Jitter(, shake) thus produce on the basis of random number, in the feedback branch of phase-locked loop module, increase a multichannel wavelet, and the random number sequence that the disturbance size of multichannel wavelet is produced by system is controlled, be equivalent to the output that basis to phase-locked loop circuit contained random Jitter and be carried out again once random disturbance, so that phaselocked loop is difficult to finish locking, cause Jitter to strengthen, randomness strengthens greatly.Use frequency-dividing clock, by d type flip flop the high-frequency clock that contains very large Jitter and process random perturbation of phaselocked loop output is sampled, the result of sampling is the data with good randomness.The sampling metastable state of also utilizing the metastable state cancellation module to eliminate may to occur guarantees the normal operation of circuit, avoids circuit the system that metastable state causes to occur unstable.
Further, the multichannel wavelet comprises the successively m group wavelet line structure of serial connection, and each group wavelet line structure has a pair of forward control end and reverse control end, and i group wavelet line structure is corresponding with the i position output in the m displacement bit line; I group wavelet line structure comprises that input end, two transmission gates, time delays are 2
I-1With phase inverter and output terminal, a road of input end arrives output terminal through a transmission gate with lag line, control for the disturbance of individual chronomere, and another road arrives output terminal through another transmission gate and the disturbance of serial connection with lag line successively; The i position is exported one the tunnel and is connected respectively the positive control end of a transmission gate and the revertive control end of another transmission gate in the m displacement bit line, and another road connects respectively the revertive control end of a transmission gate and the positive control end of another transmission gate after control is with phase inverter.
Adopt such technical scheme, each control bit (being a pair of forward control end and reverse control end) can be controlled and select a lag line or a wire to carry out disturbance, like this, along with the level of m control bit is different, whole piece multichannel wavelet can permutation and combination go out 0-Σ 2
I-1The carryover effects of individual chronomere can according to the value of the needs of random number randomness rationally being set m, satisfy the needs to the different random requirement.
Further, the metastable state module comprises successively a plurality of d type flip flops of serial connection, and the output of frequency divider is respectively as the sampling clock of each d type flip flop.
Further, described true random number generation systems also comprises clock edge race hazard generator, XOR gate module and the main delay line that is complementary with the time delay of race hazard generator; The output one tunnel of master clock signal input interface unit is connected with frequency divider with phase-locked loop circuit respectively through main delay line first again, and another road is as the clock of race hazard generator; Sampling is connected with the metastable state cancellation module through the XOR gate module first with d type flip flop again, sampling uses the output of d type flip flop as an input of XOR gate module, the output of race hazard generator is as another input of XOR gate module, and the output of XOR gate module is connected with the input of metastable state cancellation module.
Adopt such technical scheme, utilize system clock, adopt special clock edge race hazard generator architecture, can constantly make up at the edge of system clock and have a large amount of burr signals, the random number of utilizing sort signal and front phaselocked loop to produce is carried out the logic of XOR gate, and its result can increase a large amount of random burrs to a random number signal that is produced by phaselocked loop.
Further, the race hazard generator comprise NOR gate circuit, a n d type flip flop, n from upset with phase inverter and the n root phase matching lag line of serial connection successively, the n root phase matching of serial connection is with the time delay sum of the lag line generation semiperiod less than master clock signal successively; The clock end of race hazard generator through the j root phase matching of serial connection successively with lag line after as the clock of j d type flip flop, the output terminal of d type flip flop is through certainly overturning with behind the phase inverter, one tunnel input as NOR gate circuit, another road is as the input of same d type flip flop; J=1 wherein, 2,3 ..., n.
Further, in the race hazard generator: the time delay that the delay inequality between the clock signal of one of them d type flip flop and the master clock signal and main delay line produce is identical, and the delay inequality of remaining d type flip flop and this trigger is compared to semiperiod of master clock signal order of magnitude extremely when young.
Further again, n=2k-1, in the race hazard generator: the time delay that the delay inequality between k d type flip flop and the master clock signal and main delay line produce is identical, and the delay inequality of remaining d type flip flop and k d type flip flop is compared to semiperiod of master clock signal order of magnitude extremely when young; Wherein, k is positive integer.
Sampling technique scheme, race hazard generator adopt the XOR gate logic that is difficult to most eliminate risk as final combinational logic circuit, utilize odd number from the input of the d type flip flop that overturns as combinational logic.Normally, the initial value of d type flip flop is a random quantity when powering on, so the seed that this circuit produces random number is random.And, utilize lag line by near this odd number d type flip flop saltus step clock edge, the clock of the d type flip flop in the middle of allowing is consistent through the phase place behind the main delay line with system clock, and the clock phase of the d type flip flop of front is successively more in advance., the d type flip flop of face face falls behind a bit again successively, and the combinational logic input signal that produces so all changes at the edge of system clock saltus step, so output signal produces a large amount of little burrs with good randomness at the system clock edge.
Further, described true random number generation systems also comprises controller; The master clock signal input interface unit comprises input interface, master clock signal switch and is used for setting the frequency counter of frequency divider output frequency; Input interface is connected with the input of master clock signal switch, and the output of master clock signal switch is connected with phase-locked loop circuit with frequency divider respectively, and the switch motion of master clock signal switch is controlled by the controller, and controller can write frequency division value in frequency counter.
Adopt such technical scheme, can control as required whether produce random number, and can reduce power consumption, and can control the speed that random number produces according to the output frequency of the requirement of randomness being set frequency divider, strengthened the function of system.
Further, described true random number generation systems also comprises controller; The p counter that random number output interface unit comprises p bit parallel output interface, p displacement bit line and is used for the figure place that p displacement bit line is written into is counted; The input of p counter is connected with the output of frequency divider, and the output of p counter is connected with the input of controller; The input of p displacement bit line is connected with the output of metastable state cancellation module, and the p position output of p displacement bit line is connected with each input end of p bit parallel output interface respectively; Wherein, p=2
r, r is positive integer.
Adopt such technical scheme, once can export a row random number sequence, namely export simultaneously p position random number, set as required the value of p, the convenience that greatly enhancing system uses.
The present invention also provides a kind of another kind of true random number generation systems that mainly is comprised of master clock signal generator and above-mentioned true random number generation systems, and the output of master clock signal generator is connected with the input of master clock signal input interface unit.
Passed through theoretical analysis and emulation, this chip has reached desirable randomness effect.Chip utilizes the method for Clock Gating Technique and variable frequency, has reduced power consumption, possesses good actual application value.
The present invention has following beneficial effect.
Adopt technical scheme of the present invention, thereby utilizing phase-locked loop circuit itself just can produce on the basis of random Jitter generation random number, in the feedback branch of phase-locked loop module, increase a multichannel wavelet, and the random number sequence that the disturbance size of multichannel wavelet is produced by system is controlled, be equivalent to the output that basis to phase-locked loop circuit contained random Jitter and be carried out again once random disturbance, so that phaselocked loop is difficult to finish locking, cause Jitter to strengthen, randomness strengthens greatly.Use frequency-dividing clock, the high-frequency clock that contains very large Jitter and process random perturbation of phaselocked loop output is sampled with d type flip flop by sampling, the result of sampling is the data with good randomness.Also utilize the metastable state cancellation module to eliminate the metastable state that may occur, can obtain good random number.
True random number generation systems of the present invention can change the speed that random number produces as requested, made things convenient for use, make true random number generation systems of the present invention have extraordinary performance and actual application value, and utilize PLL(Phase Locked Loop, phaselocked loop) and Clock Gating Technique can effectively reduce power consumption and the stability of system, increase system lifetim.
Through the emulation of theoretical analysis and 1000 random number points, the random number of generation proves that according to Average probability distribution true random number generation systems of the present invention has extremely good randomness.
Description of drawings
Fig. 1 is the electrical block diagram of true random number generation systems embodiment of the present invention;
Fig. 2 is the electrical block diagram of the multichannel wavelet that adopts in the embodiment of the invention;
Fig. 3 is the electrical block diagram of the race hazard generator that adopts in the embodiment of the invention;
Fig. 4 is the electrical block diagram of the interface module that adopts in the embodiment of the invention;
Fig. 5 utilizes computing machine to produce 1000 distribution design sketchs that satisfy the random number of Gaussian distribution;
Fig. 6 utilizes Computer Simulation to adopt the distribution design sketch of the random number that the random number generating chip of the Technical Design of the embodiment of the invention produces;
Fig. 7 utilizes Quartus II the race hazard generator that adopts in the embodiment of the invention to be carried out the simulation waveform figure of emulation.
Embodiment
The present invention is further described below in conjunction with description of drawings and embodiment.
The present invention is further described below in conjunction with description of drawings and embodiment.In accompanying drawing of the present invention, same element will be used same symbolic representation in several relevant accompanying drawings of same embodiment.
As shown in Figure 1, true random number generation systems of the present invention, comprise master clock signal generator 100, interface module 1, phase-locked loop module 2, frequency divider 3, sampling d type flip flop 4, metastable state cancellation module 5 and m displacement bit line 6, interface module 1 comprises master clock signal input interface unit 11 and random number output interface unit 12, phase-locked loop module 2 comprises phase-locked loop circuit 21(Phase Locked Loop, PLL) and multichannel wavelet 22, multichannel wavelet 22 comprises that m is to forward control end and reverse control end; Master clock signal generator 100 output master clock signals are to master clock signal input interface unit 11, and it exports one tunnel input as frequency divider 3, and another road is connected with the input of phase-locked loop circuit 21; The output of phase-locked loop circuit 11 is connected with the input of multichannel wavelet 22, and the output one tunnel of multichannel wavelet 22 is as the feed back input of phase-locked loop circuit 21, and another road is as the input of sampling with d type flip flop 4; The output of frequency divider 3 is as the clock of sampling with d type flip flop (DFF) 4; Sampling is connected with the input of metastable state cancellation module 5 with the output of d type flip flop 4, and the output one tunnel of metastable state cancellation module 5 is connected with the input of m displacement bit line 6; In the m displacement bit line 6 the i position export one the tunnel as i corresponding in the multichannel wavelet 22 to forward control end and the reverse forward control end in the control end, another road is as corresponding oppositely control end; Another road of metastable state cancellation module 5 outputs is connected with the input of random number output interface unit 12, externally exports true random number; Metastable state cancellation module 5 comprises successively a plurality of (being preferably 3) d type flip flop (DFF) of serial connection, and the output of frequency divider 3 is respectively as the sampling clock of each d type flip flop.I=1 wherein, 2,3 ..., m.
The output signal of phase-locked loop circuit 21 itself just has certain random Jitter(and beats, shake), the output of phase-locked loop circuit 21 is admitted to again multichannel wavelet 22, and multichannel wavelet 22 is sizes of being come control disturbance by the random number sequence that the random number generation systems produces, has been equivalent to like this produce a random disturbance.Be admitted to " feedback signal " end of phase-locked loop circuit 21 through the signal of random perturbation, phase-locked loop circuit 21 just is difficult to finish locking like this, causes Jitter to strengthen, and randomness is grow greatly.3 pairs of system's major clocks of recycling frequency divider carry out frequency division, utilize frequency-dividing clock that the high-speed clock signal that contains very large Jitter and process random perturbation of phase-locked loop module 2 outputs is sampled, and the result of sampling is the data with good randomness; The optional three grades of d type flip flops of recycling metastable state cancellation module 5() eliminate the metastable state that may occur, will obtain good random number; Form random number sequence by m displacement bit line 6 at last, the control end that every row random number sequence is sent into multichannel wavelet 22 is done random perturbation control; Simultaneously, the true random number that produces is externally exported through random number output interface unit 12.
As shown in Figure 2, multichannel wavelet 22 comprises the successively m group wavelet line structure 220 of serial connection, each group wavelet line structure 220 has a pair of forward control end 221a and reverse control end 221b, and i group wavelet line structure 220 is corresponding with i line of displacement in the m displacement bit line 6; I group wavelet line structure 220 comprises that input end 222, two transmission gates 223, time delays are 2
I-1The disturbance of individual chronomere lag line 224, control phase inverter 225 and output terminal 226, a road of input end 222 arrives output terminals 226 through a transmission gate 223, and another road arrives output terminals 226 through another transmission gate 223 and the disturbance of serial connection with lag line 224 successively; The output one tunnel of the i position in the m displacement bit line 6 connects respectively the positive control end of a transmission gate 223 and the revertive control end of another transmission gate 223, and another road connects respectively the revertive control end of a transmission gate 223 and the positive control end of another transmission gate 223 after control is with phase inverter 225.
Preferably, as shown in Figure 1, the true random number generation systems also comprises clock edge race hazard generator 7, XOR gate module 8 and the main delay line 9 that is complementary with the time delay of race hazard generator 7; The output one tunnel of master clock signal input interface unit 11 is connected with frequency divider with phase-locked loop circuit 21 respectively through main delay line 9 first again and is connected, master clock signal is through sending into phase-locked loop circuit 21 conducts with reference to clock behind the main delay line 9, another road of master clock signal input interface unit 11 outputs is as the clock of race hazard generator 7; Sampling is connected with metastable state cancellation module 5 through XOR gate module 8 first with d type flip flop 4 again, sampling uses the output of d type flip flop 4 as an input of XOR gate module 8, the output of race hazard generator 7 is as another input of XOR gate module 8, and the output of XOR gate module 8 is connected with the input of metastable state cancellation module 5.
Utilize system's major clock, adopt special clock edge race hazard generator architecture, can constantly make up at the edge of system clock and have a large amount of burr signals, the random number of utilizing sort signal and phase-locked loop module 2 to produce is carried out the logic of XOR gate, and its result will be a random number signal that constantly has a large amount of burrs at clock edge; Recycling metastable state cancellation module 5 is eliminated the metastable state that the front may occur, and will obtain good random number; Through m displacement bit line 6 output random number sequences, the control end of at last every row random number sequence being sent into multichannel wavelet 22 is done random perturbation control again; Simultaneously, the random number that produces is externally exported through random number output interface unit 12.
The race hazard of combinational logic is because the input of combinational logic gate circuit changes asynchronous causing, usually the combinational logic race hazard does not have any randomness, the race hazard of these combinational logics can bring the burr of output, and these burrs have certain rule.But, if the burr that the combinational logic race hazard produces occurs in the d type flip flop data terminal, and occurring in the sampling edge of d type flip flop, the result of sampling has just possessed certain randomness so.Clock edge race hazard generator in the present embodiment as shown in Figure 3, the race hazard generator comprises NOR gate circuit 71, a n d type flip flop 72, the individual n root phase matching lag line 74 of using phase inverter 73 and being connected in series successively from overturning of n, and the n root phase matching of serial connection uses the time delay sum of lag line 74 generations less than the semiperiod of master clock signal successively; The clock end of race hazard generator 7 through the j root phase matching of serial connection successively with behind the lag line 74 as the clock of j d type flip flop 72, the output terminal of d type flip flop 72 is through after using phase inverter 73 from upset, one tunnel input as NOR gate circuit 71, another road is as the input of d type flip flop 72; J=1 wherein, 2,3 ..., n.
In the race hazard generator: as shown in Figure 3, the time delay that delay inequality between the clock signal of one of them d type flip flop 72 and the master clock signal and main delay line 9 produce is identical, and the delay inequality of all the other d type flip flops 72 and this d type flip flop 72 is compared to semiperiod of master clock signal to order of magnitude when young.For example, preferably, the quantity of the d type flip flop 72 in the race hazard generator 7 is odd number, be n=2k-1, in race hazard generator 7: the time delay that the delay inequality between k d type flip flop 72 and the master clock signal and main delay line 9 produce is identical, and the delay inequality of all the other d type flip flops 72 and k d type flip flop 72 is compared to the semiperiod of a master clock signal little positive integer order of magnitude; Wherein, k is positive integer.
The race hazard generator of the present embodiment adopts the XOR gate logic that is difficult to most eliminate risk as final combinational logic circuit, utilizes the d type flip flop 72 of certainly upset of odd number (for example 5) as the input of combinational logic.Normally, the initial value of d type flip flop 72 is the random quantitys when powering on, so the seed that this circuit produces random number is random.Want to cause at the edge of system clock the risk burr of combinational logic, need to allow near 5 d type flip flop 72 saltus steps clock edge.The race hazard generator 7 interior clock phase coupling lag lines 74 that accessed in the present embodiment, as shown in Figure 2, utilize phase matching lag line 74, the clock of the d type flip flop 72 in the middle of allowing is consistent with phase place after the system master clock signal passes through main delay line 9, the clock phase of the first two d type flip flop 72 successively leading system master clock signal through the phase place behind the main delay line 9 a bit, latter two d type flip flop 72 falls behind system's master clock signal through the phase place behind the main delay line 9 a bit again successively.The combinational logic input signal that produces so all changes at the edge of system's major clock saltus step, and output signal produces a large amount of little burrs at system major clock edge like this.
As shown in Figure 1, the true random number generation systems of the present embodiment also comprises controller 200; As shown in Figure 4, master clock signal input interface unit 11 comprises input interface 111, master clock signal switch 112 and is used for setting the frequency counter 113 of frequency divider frequency; Random number output interface unit 12 comprises p bit parallel output interface 121, p displacement bit line 122 and is used for the figure place that p displacement bit line 122 is written into is carried out the p counter 123 of technology.Input interface 111 is connected with the input of master clock signal switch 112, the output of master clock signal switch 112 is connected with phase-locked loop circuit with frequency divider 3 respectively and is connected, controlled device 200 controls of the switch motion of master clock signal switch 112, controller 200 can write frequency division value in frequency counter 113.The input of p counter 123 is connected with the output of frequency divider 3, and the output of p counter 123 is connected with the input of controller 200; The input of p displacement bit line 122 is connected with the output of metastable state cancellation module 5, and the p position output of p displacement bit line 122 is connected with each input end of p bit parallel output interface 121 respectively, the random number sequence of p bit parallel output interface 121 output p positions one row.Wherein, p=2
r, r is positive integer.System's major clock is gated clock, determines whether to produce random number sequence by controller 200; Master clock signal switch 112 is except selecting the switch of direct controlled device 200 controls, the switch that also can select transmission gate and gated clock controller 112a to combine, the switch motion of transmission gate is subjected to the control of gated clock controller 112a, and the control of the controlled device 200 of gated clock controller 112a.
Can be with the circuit structure except master clock generator 100 and controller 200 in the true random number generation systems of the present embodiment, comprise interface module 1, phase-locked loop module 2, frequency divider 3, sampling d type flip flop 4, metastable state cancellation module 5, m displacement bit line 6, race hazard generator 7, XOR gate module 8 and main delay line 9 etc., be integrated among the chip, for example utilize FPGA to realize, the circuit communications such as the master clock generator 100 that interface module 1 is responsible for and chip is outer and controller 200, master clock signal input interface unit 11 provides system's major clock and frequency division value for system, and the transmission of random number sequence is processed in random number output interface unit 12.Interface module 1 is whole chip and the bridge that connects of being connected, and is responsible for that system's major clock is carried out gate and processes, and accepts external control signal, the work such as assembles to exporting numeral.
As shown in Figure 4, two registers are arranged in the master clock signal input interface unit 11, a register is as gated clock controller 112a, whether its representative starts the sign of random number generating chip, if this zone bit is high level, is representing external clock is being sent into the random number generating chip, if this zone bit is low level, then whole clock is blocked in expression, and the random number generating chip quits work; The another one register is frequency counter 113, is storing the frequency division value that is used for control frequency divider 2 output frequency value, as the numerical standard of frequency divider 2 frequency divisions.These two registers are all worked under " write command " control signal of chip exterior controller 200.A very important effect of random number output interface unit 12 is that single random number is spliced, 8 counters that 8 displacement bit lines (being p=8) and this line of displacement of cooperation are arranged in this unit, requirement according to 8 one group is exported, the random number sequence that output p position is one group, whenever write expired 8 displacement bit lines after, produce the control signal of " writing out number ".
Various modules in the present embodiment, the unit, circuit, certainly can be self-existent circuit structure separately, then with each independently circuit structure link together and form the true random number generation systems of the present embodiment, they also can be default circuit units in the existing programmable chip, by the programming (be not the process of writing software program, the process of firing in the time of in fact) each circuit unit is linked together as requested, FPGA namely is the logical device of a kind of (firing) able to programme, the resource of its chip internal is digital circuit structure and a small amount of and the directly related analog circuit unit structure of digital circuit, the FPGA technology is as the faster a kind of technology of development of coming in, the inner integrated circuit structures such as various logic gates, can realize easily multiple circuit and then finish chip design, be a kind of good method that realizes fast chip design.Therefore, utilize the fpga chip resource, making up the random number circuit for generating is well to realize one of scheme of true random number generating chip.
This case inventor is to emulation and effect analysis based on the true random number generating chip of FPGA according to technique scheme design: in order to verify the randomness effect of PLL, the present embodiment utilizes computing machine to carry out emulation, at first utilize computing machine to produce 1000 random numbers that satisfy Gaussian distribution, be used for the Jitter of emulation PLL, this group random-number distribution as shown in Figure 5.
According to phase-locked loop circuit rule usually, the mean value of Jitter should suppose that the Jitter that can reach in the fpga chip is 5% within 5% ~ 10%, and the disturbance time of the multichannel wavelet of our design is made as 5% ~ 10% accordingly.Increased after the random perturbation to Jitter, having re-used sampling and with d type flip flop data being sampled, then obtained span and be 8 random numbers of 0 to 255, last, the random number of generation as shown in Figure 6.As seen the randomness of these points is good, and probability distribution is to be evenly distributed, and no longer is Gaussian distribution.
Utilize Quartus II to carry out modeling with the Verilog language to the circuit of FPGA inside, and can carry out emulation to its effect.Utilize Verilog that the race hazard generator in the present embodiment is designed, and carried out emulation, the waveform of emulation as shown in Figure 7.As seen from Figure 7, near the edge of clock, the output " rdata " of combinational logic race hazard generator has produced a large amount of burrs, and these burrs can produce uncertain sample effect when utilizing in the back sampling to sample with d type flip flop, reach the purpose that strengthens final randomness.
As above institute's cloud is in conjunction with concrete preferred implementation further description made for the present invention, can not assert that implementation of the present invention is confined to these explanations.For the general technical staff of the technical field of the invention, under the prerequisite that does not break away from design of the present invention and intension, can also make some simple deduction or replace, all should be considered as belonging to protection scope of the present invention.
Claims (10)
1. true random number generation systems, it is characterized in that: comprise master clock signal input interface unit (11), phase-locked loop module (2), frequency divider (3), sampling d type flip flop (4), metastable state cancellation module (5), m displacement bit line (6) and random number output interface unit (12), phase-locked loop module (2) comprises phase-locked loop circuit (21) and multichannel wavelet (22), and multichannel wavelet (22) has m to forward control end and reverse control end; The output one tunnel of master clock signal input interface unit (11) is as the input of frequency divider (3), and another road is connected with the input of phase-locked loop circuit (21); The output of phase-locked loop circuit (21) is connected with the input of multichannel wavelet (22), and the output one tunnel of multichannel wavelet (22) is as the feed back input of phase-locked loop circuit (21), and another road is as the input of sampling with d type flip flop (4); The output of frequency divider (3) is as the clock of sampling with d type flip flop (4); Sampling is connected with the input of metastable state cancellation module (5) with the output of d type flip flop (4), and the output one tunnel of metastable state cancellation module (5) is connected with the input of m displacement bit line (6); I position in the m displacement bit line (6) export one the tunnel as i corresponding in the multichannel wavelet (22) to forward control end and the reverse forward control end (221a) in the control end, another road is as corresponding oppositely control end (221b); Another road of metastable state cancellation module (5) output inputs to random number output interface unit (12); I=1 wherein, 2,3 ..., m.
2. true random number generation systems according to claim 1, it is characterized in that: multichannel wavelet (22) comprises the successively m group wavelet line structure (220) of serial connection, each group wavelet line structure (220) has a pair of forward control end (221a) and reverse control end (221b), and i group wavelet line structure (220) is corresponding with the i position output in the m displacement bit line (6); I group wavelet line structure (220) comprises that input end (222), two transmission gates (223), time delay are 2
I-1The disturbance of individual chronomere lag line (224), control phase inverter (225) and output terminal (226), a road of input end (222) arrives output terminal (226) through a transmission gate (223), another road successively through another transmission gate (223) of serial connection and disturbance with lag line (225) arrival output terminal (226); The i position is exported one the tunnel and is connected respectively the positive control end of a transmission gate (223) and the revertive control end of another transmission gate (223) in the m displacement bit line (6), and another road connects respectively the revertive control end of a transmission gate (223) and the positive control end of another transmission gate (223) after control is with phase inverter (225).
3. true random number generation systems according to claim 1 is characterized in that: metastable state module (5) comprises successively a plurality of d type flip flops of serial connection, and the output of frequency divider (3) is respectively as the sampling clock of each d type flip flop.
4. true random number generation systems according to claim 1 is characterized in that: also comprise clock edge race hazard generator (7), XOR gate module (8) and the main delay line (9) that is complementary with the time delay of race hazard generator (7); The output one tunnel of master clock signal input interface unit (11) is passed through first main delay line (9) and is connected 3 with phase-locked loop circuit (21) with frequency divider respectively again) be connected, another road is as the clock of race hazard generator (7); Sampling is passed through first XOR gate module (8) with d type flip flop (4) and is connected with metastable state cancellation module (5), sampling uses the output of d type flip flop (4) as an input of XOR gate module (8), the output of race hazard generator (7) is as another input of XOR gate module (8), and the output of XOR gate module (8) is connected with the input of metastable state cancellation module (5).
5. true random number generation systems according to claim 4, it is characterized in that: race hazard generator (7) comprises NOR gate circuit (71), a n d type flip flop (72), the individual n root phase matching lag line (74) of using phase inverter (73) and being connected in series successively from overturning of n, and the n root phase matching of serial connection uses the time delay sum of lag line (74) generation less than the semiperiod of master clock signal successively; The clock end of race hazard generator (7) is through the j root phase matching that is connected in series the successively rear clock as j d type flip flop (72) of lag line (74), the output terminal of d type flip flop (72) is through after upset is with phase inverter (73), one tunnel input as NOR gate circuit (71), another road is as the input of same d type flip flop (72); J=1 wherein, 2,3 ..., n.
6. true random number generation systems according to claim 5, it is characterized in that: in race hazard generator (7): the time delay that the delay inequality between the clock signal of one of them d type flip flop (72) and the master clock signal and main delay line (9) produce is identical, and the delay inequality of remaining d type flip flop (72) and this trigger (72) is compared to semiperiod of master clock signal to order of magnitude when young.
7. true random number generation systems according to claim 6, it is characterized in that: n=2k-1, in race hazard generator (7): the time delay that the delay inequality between k d type flip flop (72) and the master clock signal and main delay line (9) produce is identical, and the delay inequality of remaining d type flip flop (72) and k d type flip flop (72) is compared to semiperiod of master clock signal order of magnitude extremely when young; Wherein, k is positive integer.
8. true random number generation systems according to claim 1 is characterized in that: also comprise controller (200); Master clock signal input interface unit (11) comprises input interface (111), master clock signal switch (112) and is used for setting the frequency counter (113) of frequency divider (3) output frequency; Input interface (111) is connected with the input of master clock signal switch (112), the output of master clock signal switch (112) is connected 21 with frequency divider (3) with phase-locked loop circuit respectively) be connected, the controlled device of switch motion (200) control of master clock signal switch (112), controller (200) can write frequency division value in frequency counter (113).
9. true random number generation systems according to claim 1 is characterized in that: also comprise controller (200); The p counter (123) that random number output interface unit (12) comprises p bit parallel output interface (121), p displacement bit line (122) and is used for the figure place that p displacement bit line (122) is written into is counted; The input of p counter (123) is connected with the output of frequency divider (3), and the output of p counter (123) is connected with the input of controller (200); The input of p displacement bit line (122) is connected with the output of metastable state cancellation module (5), and the p position output of p displacement bit line (122) is connected with each input end of p bit parallel output interface (121) respectively; Wherein, p=2
r, r is positive integer.
10. a true random number generation systems comprises the described true random number generation systems of master clock signal generator (100) and claim 1-9, and the output of master clock signal generator (100) is connected with the input of master clock signal input interface unit (11).
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Family
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106201434A (en) * | 2016-07-05 | 2016-12-07 | 南通理工学院 | Reversible random number generator |
| CN106303312A (en) * | 2016-08-12 | 2017-01-04 | 中国科学院上海高等研究院 | Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor |
| CN106775583A (en) * | 2016-11-18 | 2017-05-31 | 杭州电子科技大学 | A kind of production method of high-speed, true random-number |
| CN107592098A (en) * | 2016-11-18 | 2018-01-16 | 上海兆芯集成电路有限公司 | For data-signal deposit to be arrived to the data synchronizing unit of clock zone |
| CN108733350A (en) * | 2017-04-13 | 2018-11-02 | 力旺电子股份有限公司 | Generating random number device and its control method |
| CN109412561A (en) * | 2018-09-12 | 2019-03-01 | 上海华力集成电路制造有限公司 | Randomizer, random sequence generation circuit and its course of work |
| CN110045947A (en) * | 2019-04-22 | 2019-07-23 | 湖南国科微电子股份有限公司 | A kind of random number generation unit and device |
| CN111540102A (en) * | 2020-04-30 | 2020-08-14 | 华南师范大学 | Dynamic password circuit, access control system and access control method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101414337A (en) * | 2008-11-17 | 2009-04-22 | 武汉大学 | Evolvement cipher chip |
| CN201327636Y (en) * | 2008-10-27 | 2009-10-14 | 张润捷 | True random number generator |
| CN103049242A (en) * | 2012-12-04 | 2013-04-17 | 清华大学 | Digital true random number generator circuit |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201327636Y (en) * | 2008-10-27 | 2009-10-14 | 张润捷 | True random number generator |
| CN101414337A (en) * | 2008-11-17 | 2009-04-22 | 武汉大学 | Evolvement cipher chip |
| CN103049242A (en) * | 2012-12-04 | 2013-04-17 | 清华大学 | Digital true random number generator circuit |
Non-Patent Citations (3)
| Title |
|---|
| 周干民等: "一种基于锁相环的真随机数发生器", 《电子与信息学报》 * |
| 张鸿飞等: "基于抖动的高速真随机数发生器的设计和实现", 《核技术》 * |
| 王莱等: "真随机数发生器的设计和实现", 《核电子学与探测技术》 * |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106201434B (en) * | 2016-07-05 | 2018-07-10 | 南通理工学院 | Reversible random number generator |
| CN106201434A (en) * | 2016-07-05 | 2016-12-07 | 南通理工学院 | Reversible random number generator |
| CN106303312A (en) * | 2016-08-12 | 2017-01-04 | 中国科学院上海高等研究院 | Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor |
| CN106303312B (en) * | 2016-08-12 | 2019-04-30 | 中国科学院上海高等研究院 | Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor |
| CN107592098B (en) * | 2016-11-18 | 2019-04-30 | 上海兆芯集成电路有限公司 | For data-signal to be deposited to the data synchronizing unit to clock domain |
| CN106775583B (en) * | 2016-11-18 | 2019-03-05 | 杭州电子科技大学 | A kind of production method of high-speed, true random-number |
| CN107592098A (en) * | 2016-11-18 | 2018-01-16 | 上海兆芯集成电路有限公司 | For data-signal deposit to be arrived to the data synchronizing unit of clock zone |
| CN106775583A (en) * | 2016-11-18 | 2017-05-31 | 杭州电子科技大学 | A kind of production method of high-speed, true random-number |
| CN108733350A (en) * | 2017-04-13 | 2018-11-02 | 力旺电子股份有限公司 | Generating random number device and its control method |
| CN108733350B (en) * | 2017-04-13 | 2021-08-27 | 力旺电子股份有限公司 | Random number generation device and control method thereof |
| CN109412561A (en) * | 2018-09-12 | 2019-03-01 | 上海华力集成电路制造有限公司 | Randomizer, random sequence generation circuit and its course of work |
| CN110045947A (en) * | 2019-04-22 | 2019-07-23 | 湖南国科微电子股份有限公司 | A kind of random number generation unit and device |
| CN110045947B (en) * | 2019-04-22 | 2021-09-17 | 湖南国科微电子股份有限公司 | Random number generating unit and device |
| CN111540102A (en) * | 2020-04-30 | 2020-08-14 | 华南师范大学 | Dynamic password circuit, access control system and access control method |
| CN111540102B (en) * | 2020-04-30 | 2022-01-04 | 华南师范大学 | Dynamic password circuit, access control system and access control method |
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