CN103198267A - Reconfigurable multi-port physical unclonable functions (PUF) circuit unit - Google Patents
Reconfigurable multi-port physical unclonable functions (PUF) circuit unit Download PDFInfo
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- CN103198267A CN103198267A CN201310086537XA CN201310086537A CN103198267A CN 103198267 A CN103198267 A CN 103198267A CN 201310086537X A CN201310086537X A CN 201310086537XA CN 201310086537 A CN201310086537 A CN 201310086537A CN 103198267 A CN103198267 A CN 103198267A
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Abstract
The invention discloses a reconfigurable multi-port physical unclonable functions (PUF) circuit unit. The reconfigurable multi-port PUF circuit unit comprises a first control circuit module, an input module, an output module and a random process deviation generation module, wherein the first control circuit module is connected with the input module, the output module and the random process deviation generation module respectively; the input module is connected with the random process deviation generation module; and the random process deviation generation module is connected with the output module. The reconfigurable multi-port PUF circuit unit has the advantages that the number of output secret keys and ports can be reconfigured; the number of output secret keys and ports can be exchanged flexibly; a plurality of secret keys can be generated within one clock period; the cost is low; and the running speed is high.
Description
Technical field
The present invention relates to a kind of PUF circuit, especially relate to a kind of restructural multiport PUF circuit unit.
Background technology
The physics that March calendar year 2001, Pappu proposed in " Physical One-Way Functions " can not be cloned function (Physical Unclonable Functions, be called for short PUF) have uniqueness and can not clone property, can be widely used for as authentication and false proof means.Adopt the PUF technology to be proposed by the researchists such as Gassend of Massachusetts Polytechnics the earliest on the integrated chip.The PUF technology is a kind of chip field " biological characteristic " recognition technology, also can be referred to as " chip DNA " technology, it (comprises oxidated layer thickness by the inevitable process deviation that produces in the PUF circuit extraction chip manufacturing proces, W/L and at random ion factor such as mix), generate infinitely a plurality of, distinctive keys, unpredictable and the arrangement of these keys, the permanent existence is even the manufacturer of chip also can't copy.The peculiar unlimited many keys of PUF circuit this chip of Dynamic Extraction from the chip, these keys can be widely used in the safety of chip and false proof.The PUF technology can improve safety and the reliable grade of chip and chip system, has obtained widely in chip safety anti-fake field and has used.
The ID that generates based on the security protocol of PUF has uniqueness and can not clone property, its with respect to other security protocol resist physical attacks, lie is attacked and be suitable for and aspects such as lightweight protocol attack have obvious superiority.But, existing P UF circuit generally is by a port output key, and in a clock period, only can export a key, travelling speed is slower, because the process deviation that unavoidably produces in the chip manufacturing proces of PUF circuit extraction is unique, is constant thereby cause the output key of PUF circuit in addition, can't be reconstructed, when product (for example chip) needs to change password, whole PUF circuit more can only be changed, cost is very high.
Summary of the invention
Technical matters to be solved by this invention provides a kind ofly can change the output key flexibly, and cost is lower, and travelling speed restructural multiport PUF circuit unit faster.
The present invention solves the problems of the technologies described above the technical scheme that adopts: a kind of restructural multiport PUF circuit unit, comprise the first control circuit module, load module, output module and process deviation generation module at random, described first control circuit module is provided with the enable signal input end, the pumping signal output terminal, control signal output terminal and output key port number output terminal, described load module is provided with the external signal input end, pumping signal input end and signal output part, described output module is provided with the port number input end, signal input part and signal output part, the described generation module of process deviation at random is provided with the control signal end, signal input part and signal output part, the pumping signal output terminal of described first control circuit module is connected with the pumping signal input end of described load module, the output key port number output terminal of described first control circuit module is connected with the port number input end of described output module, the control signal output terminal of described first control circuit module is connected with the control end of the described generation module of process deviation at random, the signal output part of described load module is connected with the signal input part of the described generation module of process deviation at random, the signal output part of the described generation module of process deviation at random is connected with the signal input part of described output module, and the signal that the external signal input end of described load module inserts comprises data-signal, address signal and control voltage signal.
Described load module is by first d type flip flop, second d type flip flop and 3d flip-flop are formed, the described first d type flip flop incoming data signal, the described second d type flip flop access address signal, described 3d flip-flop Access Control voltage signal and first clock signal, the described generation module of process deviation at random comprises register file, oscillator and N d type flip flop group that is in series by two d type flip flops, described register file respectively with described first d type flip flop, described second d type flip flop, described oscillator is connected with N d type flip flop group, described oscillator is connected with first d type flip flop in each d type flip flop group with described 3d flip-flop respectively, second d type flip flop in each d type flip flop group inserts described first clock signal, the output signal of described oscillator is the second clock signal, described output module is made up of N output unit, each output unit is in series by latch and FIFO output circuit, second d type flip flop in latch in N output unit and N the d type flip flop group connects one to one, described first control circuit module respectively with described first d type flip flop, described second d type flip flop, described 3d flip-flop is connected with FIFO output circuit in N the output unit, the frequency of described first clock signal is 0～50MHz, the frequency of described second clock signal is 500M-1GHz, N 〉=2.
Described oscillator comprises the differential delay circuit, level translator, duty cycle circuit and frequency divider, described differential delay circuit is provided with control voltage signal input end, first signal output part, the secondary signal output and ground, described level translator is provided with first signal input part, the secondary signal input end, first signal output part, the secondary signal output terminal, d. c. voltage signal input end and earth terminal, described duty cycle circuit is provided with first signal input part, the secondary signal input end, d. c. voltage signal input end and earth terminal, first signal output part of described differential delay circuit is connected with first signal input part of described level translator, the secondary signal output terminal of described differential delay circuit is connected with the secondary signal input end of described level translator, first signal output part of described level translator is connected with first signal input part of described duty cycle circuit, the secondary signal output terminal of described level translator is connected with the secondary signal input end of described duty cycle circuit, the signal output part of described duty cycle circuit is connected with the signal input part of described frequency divider, the earth terminal of described differential delay circuit, the earth terminal of described level translator is connected with the earth terminal of described duty cycle circuit, the d. c. voltage signal input end of described level translator and the d. c. voltage signal input end of described duty cycle circuit are connected, the control voltage signal input end of described differential delay circuit is the signal input part of described oscillator, and the signal output part of described frequency divider is the signal output part of described oscillator.
Described differential delay circuit is made up of 2n+1 differential delay unit, described differential delay unit is provided with first signal input part, the secondary signal input end, first signal output part, the secondary signal output terminal, control voltage signal input end and earth terminal, the control voltage signal input end connection of 2n+1 differential delay unit and its link are as the control voltage signal input end of described differential delay circuit, the earth terminal connection of 2n+1 differential delay unit and its link are as the earth terminal of described differential delay circuit, first signal output part of the differential delay unit of last position is connected with first signal input part of back one differential delay unit in 2n+1 differential delay unit, the secondary signal output terminal of the differential delay unit of last position is connected with the secondary signal input end of back one differential delay unit in 2n+1 differential delay unit, first signal input part of the first potential difference branch delay cell in first signal output part of last potential difference branch delay cell in 2n+1 differential delay unit and 2n+1 the differential delay unit is connected, the secondary signal input end of the first potential difference branch delay cell in the secondary signal output terminal of last potential difference branch delay cell in 2n+1 differential delay unit and 2n+1 the differential delay unit is connected, last potential difference in 2n+1 differential delay unit is divided first signal output part of first signal output part of delay cell as described differential delay circuit, last potential difference in 2n+1 differential delay unit is divided the secondary signal output terminal of the secondary signal output terminal of delay cell as described differential delay circuit, wherein n 〉=1.
Described differential delay unit is managed by a PMOS, the 2nd PMOS pipe, the one NMOS pipe and the 2nd NMOS pipe are formed, the drain electrode of a described PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe and its link is the control voltage signal input end of described differential delay unit, the grid of a described PMOS pipe, the drain electrode of the source electrode of described the 2nd PMOS pipe and described the 2nd NMOS pipe is connected and its link is first signal output part of described differential delay unit, the source electrode of a described PMOS pipe, the drain electrode of the grid of described the 2nd PMOS pipe and a described NMOS pipe is connected and its link is the secondary signal output terminal of described differential delay unit, the source electrode of the source electrode of a described NMOS pipe and described the 2nd NMOS pipe M2 is connected and its link is the earth terminal of described differential delay unit, the grid of a described NMOS pipe is first signal input part of described differential delay unit, and the grid of described the 2nd NMOS pipe is the secondary signal input end of described differential delay unit; Described level translator is managed by the 3rd PMOS, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, first phase inverter and second phase inverter are formed, the drain electrode of described the 3rd PMOS pipe, the drain electrode of described the 4th PMOS pipe, the drain electrode of the drain electrode of described the 5th PMOS pipe and described the 6th PMOS pipe is connected and its link is the d. c. voltage signal input end of described level translator, the grid of described the 3rd PMOS pipe, the drain electrode of the source electrode of described the 4th PMOS pipe and described the 4th NMOS pipe is connected and its link is first signal output part of described level translator, the source electrode of described the 3rd PMOS pipe, the drain electrode of described the 3rd NMOS pipe is connected with the grid of described the 4th PMOS pipe, the input end of the grid of described the 3rd NMOS pipe and described first phase inverter is connected and its link is first signal input part of described level translator, the output terminal of described first phase inverter is connected with the grid of described the 4th NMOS pipe, the source electrode of described the 3rd NMOS pipe, the source electrode of described the 4th NMOS pipe, the source electrode of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected and its link is the earth terminal of described level translator, the grid of described the 5th PMOS pipe, the drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe is connected and its link is the secondary signal output terminal of described level translator, the source electrode of described the 5th PMOS pipe, the drain electrode of described the 5th NMOS pipe is connected with the grid of described the 6th PMOS pipe, the input end of the grid of described the 5th NMOS pipe and described second phase inverter is connected and its link is the secondary signal input end of described level translator, and the output terminal of described second phase inverter is connected with the grid of described the 6th NMOS pipe; Described duty cycle circuit is managed by the 7th PMOS, the 8th PMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe are formed, the drain electrode of the drain electrode of described the 7th NMOS pipe and described the 7th PMOS pipe is connected and its link is the d. c. voltage signal input end of described duty cycle circuit, the source electrode of described the 7th NMOS pipe, the source electrode of described the 7th PMOS pipe, the drain electrode of the drain electrode of described the 8th NMOS pipe and described the 8th PMOS pipe is connected and its link is the signal output part of described duty cycle circuit, the source electrode of the source electrode of described the 8th NMOS pipe and described the 8th PMOS pipe is connected and its link is the earth terminal of described duty cycle circuit, the grid of described the 7th NMOS pipe is first signal input part of described duty cycle circuit, and the grid of described the 8th NMOS pipe is the secondary signal input end of described duty cycle circuit.
Described register file comprises the decoding scheme module, memory cell array, sense amplifier, selector switch, latch, second control circuit module and FIFO output circuit, described decoding scheme module comprises one-level decoding scheme unit and two-stage decode circuit unit, described one-level decoding scheme unit comprises first trigger, second trigger, the 3rd trigger, first code translator, second code translator and the 3rd code translator, described first trigger is connected with described first code translator, described second trigger is connected with described second code translator, described the 3rd trigger is connected with described the 3rd code translator, described two-stage decode circuit unit comprises three inputs and door and load driver module, described first code translator, described second code translator and described the 3rd code translator and described three inputs connect one to one with three input ends of door, described three inputs are connected with described load driver module with the output terminal of door, described load driver module is connected with described memory cell array, described memory cell array is connected with described sense amplifier, described sense amplifier is connected with described selector switch, described selector switch is connected with described latch, described latch is connected with described FIFO output circuit, described second control circuit module respectively with described memory cell array, described sense amplifier, described selector switch is connected with described latch, and described memory cell array comprises at least two storage unit.
Described first trigger, described second trigger and described the 3rd trigger are d type flip flop, and described first code translator and described second code translator are the 2-4 code translator, and described the 3rd code translator is the 1-2 code translator.
Compared with prior art, the invention has the advantages that the load module access comprises data-signal, the external signal of address signal and control voltage signal, first control circuit module output drive signal is counted to output module to load module and output output key port, load module outputs to process deviation generation module at random with pumping signal and external signal after handling, the process deviation generation module flows to output module with final data (output key) at random, output module is exported corresponding key signal according to the port number signal that receives and output key signal, by being controlled in external signal that load module inserts and the output key port number of first control circuit module output, realized the output key of PUF circuit unit and the reconstruct of port number, can change output key and the output port number of PUF circuit unit flexibly, in a clock period, produce a plurality of keys, cost is lower, and travelling speed is very fast.
Description of drawings
Fig. 1 is the theory diagram of restructural multiport PUF circuit unit of the present invention;
Fig. 2 (a) is the circuit diagram of restructural multiport PUF circuit unit of the present invention;
Fig. 2 (b) is the graphical diagram of restructural multiport PUF circuit unit of the present invention;
Fig. 3 is the theory diagram of oscillator;
Fig. 4 is the circuit structure diagram of differential delay circuit;
Fig. 5 is the circuit diagram of differential delay unit;
Fig. 6 is the circuit diagram of level translator;
Fig. 7 is the circuit diagram of duty cycle circuit;
Fig. 8 is the circuit structure diagram of register file.
Embodiment
Describe in further detail below in conjunction with the present invention of accompanying drawing embodiment.
Embodiment: as shown in Figure 1, a kind of restructural multiport PUF circuit unit, comprise first control circuit module 1, load module 2, output module 3 and process deviation generation module 4 at random, first control circuit module 1 is provided with the enable signal input end, the pumping signal output terminal, control signal output terminal and output key port number output terminal, load module 2 is provided with the external signal input end, pumping signal input end and signal output part, output module 3 is provided with the port number input end, signal input part and signal output part, process deviation generation module 4 is provided with the control signal end at random, signal input part and signal output part, the pumping signal output terminal of first control circuit module 1 is connected with the pumping signal input end of load module 2, the output key port number output terminal of first control circuit module 1 is connected with the port number input end of output module 3, the control signal output terminal of first control circuit module 1 is connected with the control end of process deviation generation module 4 at random, the signal output part of load module 2 is connected with the signal input part of process deviation generation module 4 at random, the signal output part of process deviation generation module 4 is connected with the signal input part of output module 2 at random, and the signal that the external signal input end of load module 2 inserts comprises data-signal, address signal and control voltage signal.
Shown in Fig. 2 (a), in the present embodiment, load module 2 is by first d type flip flop 21, second d type flip flop 22 and 3d flip-flop 23 are formed, first d type flip flop, 21 incoming data signals, second d type flip flop, 22 access address signals, 3d flip-flop 23 Access Control voltage signals and first clock signal, process deviation generation module 4 comprises register file 41 at random, oscillator 42 and N d type flip flop group 43 that is in series by two d type flip flops, register file 41 respectively with first d type flip flop 21, second d type flip flop 22, oscillator 42 is connected with N d type flip flop group 43, oscillator 42 is connected with first d type flip flop in each d type flip flop group 43 with 3d flip-flop 23 respectively, second d type flip flop in each d type flip flop group 43 inserts first clock signal, the output signal of oscillator 42 is the second clock signal, output module 3 is made up of N output unit 31, each output unit 31 is in series by latch and FIFO output circuit, second d type flip flop in latch in N output unit 31 and N the d type flip flop group 43 connects one to one, first control circuit module 1 respectively with first d type flip flop 21, second d type flip flop 22,3d flip-flop 23 is connected with FIFO output circuit in N the output unit 31, the frequency of first clock signal is 0～50MHz, the frequency of second clock signal is 500M-1GHz, N 〉=2, the graphical diagram of restructural multiport PUF circuit unit is shown in Fig. 2 (b).
As shown in Figure 3, in the present embodiment, oscillator 42 comprises differential delay circuit 421, level translator 422, duty cycle circuit 423 and frequency divider 424, differential delay circuit 421 is provided with control voltage signal input end, first signal output part, the secondary signal output and ground, level translator 422 is provided with first signal input part, the secondary signal input end, first signal output part, the secondary signal output terminal, d. c. voltage signal input end and earth terminal, duty cycle circuit 423 is provided with first signal input part, the secondary signal input end, d. c. voltage signal input end and earth terminal, first signal output part of differential delay circuit 421 is connected with first signal input part of level translator 422, the secondary signal output terminal of differential delay circuit 421 is connected with the secondary signal input end of level translator 422, first signal output part of level translator 422 is connected with first signal input part of duty cycle circuit 423, the secondary signal output terminal of level translator 422 is connected with the secondary signal input end of duty cycle circuit 423, the signal output part of duty cycle circuit 423 is connected with the signal input part of frequency divider 424, the earth terminal of differential delay circuit 421, the earth terminal of level translator 422 is connected with the earth terminal of duty cycle circuit 423, the d. c. voltage signal input end of level translator 422 is connected with the d. c. voltage signal input end of duty cycle circuit 423, the control voltage signal input end of differential delay circuit 421 is the signal input part of oscillator 42, and the signal output part of frequency divider 424 is the signal output part of oscillator 42.
As shown in Figure 4, in the present embodiment, differential delay circuit 421 is made up of 2n+1 differential delay unit 4211, differential delay unit 4211 is provided with first signal input part, the secondary signal input end, first signal output part, the secondary signal output terminal, control voltage signal input end and earth terminal, the control voltage signal input end connection of 2n+1 differential delay unit 4211 and its link are as the control voltage signal input end of differential delay circuit 421, the earth terminal connection of 2n+1 differential delay unit 4211 and its link are as the earth terminal of differential delay circuit 421, first signal output part of the differential delay unit of last position is connected with first signal input part of back one differential delay unit in the differential delay circuit 421, the secondary signal output terminal of the differential delay unit of last position is connected with the secondary signal input end of back one differential delay unit in the differential delay circuit 421, first signal input part of the first potential difference branch delay cell in first signal output part of last potential difference branch delay cell in the differential delay circuit 421 and the differential delay circuit 421 is connected, the secondary signal input end of the first potential difference branch delay cell in the secondary signal output terminal of last potential difference branch delay cell in the differential delay circuit 421 and the differential delay circuit 421 is connected, last potential difference in the differential delay circuit 421 is divided first signal output part of first signal output part of delay cell as described differential delay circuit, last potential difference in the differential delay circuit 421 is divided the secondary signal output terminal of the secondary signal output terminal of delay cell as differential delay circuit 521, wherein n 〉=1.
As Fig. 5～shown in Figure 7, in the present embodiment, differential delay unit 4211 is by PMOS pipe P1, the 2nd PMOS manages P2, the one NMOS pipe M1 and the 2nd NMOS pipe M2 form, the drain electrode of the one PMOS pipe P1 is connected with the drain electrode of the 2nd PMOS pipe P2 and its link is the control voltage signal input end of differential delay unit 4211, the grid of the one PMOS pipe P1, the drain electrode of the source electrode of the 2nd PMOS pipe P2 and the 2nd NMOS pipe M2 is connected and its link is first signal output part of differential delay unit 4211, the source electrode of the one PMOS pipe P1, the drain electrode of the grid of the 2nd PMOS pipe P2 and NMOS pipe M1 is connected and its link is the secondary signal output terminal of differential delay unit 4211, the source electrode of the source electrode of the one NMOS pipe M1 and the 2nd NMOS pipe M2 is connected and its link is the earth terminal of differential delay unit 4211, the grid of the one NMOS pipe M1 is first signal input part of differential delay unit 4211, and the grid of the 2nd NMOS pipe M2 is the secondary signal input end of differential delay unit 4211; Level translator 422 is by the 3rd PMOS pipe P3, the 4th PMOS manages P4, the 5th PMOS manages P5, the 6th PMOS manages P6, the 3rd NMOS manages M3, the 4th NMOS manages M4, the 5th NMOS manages M5, the 6th NMOS manages M6, the first phase inverter C1 and the second phase inverter C2 form, the drain electrode of the 3rd PMOS pipe P3, the drain electrode of the 4th PMOS pipe P4, the drain electrode of the drain electrode of the 5th PMOS pipe P5 and the 6th PMOS pipe P6 is connected and its link is the d. c. voltage signal input end of level translator 422, the grid of the 3rd PMOS pipe P3, the drain electrode of the source electrode of the 4th PMOS pipe P4 and the 4th NMOS pipe M4 is connected and its link is first signal output part of level translator 422, the source electrode of the 3rd PMOS pipe P3, the drain electrode of the 3rd NMOS pipe M3 is connected with the grid of the 4th PMOS pipe P4, and the input end of the first phase inverter C1 is connected the grid of the 3rd NMOS pipe M3 and its link is first signal input part of level translator 422, the output terminal of the first phase inverter C1 is connected with the grid of the 4th NMOS pipe M4, the source electrode of the 3rd NMOS pipe M3, the source electrode of the 4th NMOS pipe M4, the source electrode of the source electrode of the 5th NMOS pipe M5 and the 6th NMOS pipe M6 is connected and its link is the earth terminal of level translator 422, the grid of the 5th PMOS pipe P5, the drain electrode of the source electrode of the 6th PMOS pipe P6 and the 6th NMOS pipe M6 is connected and its link is the secondary signal output terminal of level translator 422, the source electrode of the 5th PMOS pipe P5, the drain electrode of the 5th NMOS pipe M5 is connected with the grid of the 6th PMOS pipe P6, and the input end of the second phase inverter C2 is connected the grid of the 5th NMOS pipe M5 and its link is the secondary signal input end of level translator 422, and the output terminal of the second phase inverter C2 is connected with the grid of the 6th NMOS pipe M6; Duty cycle circuit 423 is by the 7th PMOS pipe P7, the 8th PMOS manages P8, the 7th NMOS pipe M7 and the 8th NMOS pipe M8 form, the drain electrode of the drain electrode of the 7th NMOS pipe M7 and the 7th PMOS pipe P7 is connected and its link is the d. c. voltage signal input end of duty cycle circuit 423, the source electrode of the 7th NMOS pipe M7, the source electrode of the 7th PMOS pipe P7, the drain electrode of the drain electrode of the 8th NMOS pipe M8 and the 8th PMOS pipe P8 is connected and its link is the signal output part of duty cycle circuit 423, the source electrode of the source electrode of the 8th NMOS pipe M8 and the 8th PMOS pipe P8 is connected and its link is the earth terminal of duty cycle circuit 423, the grid of the 7th NMOS pipe M7 is first signal input part of duty cycle circuit 423, and the grid of the 8th NMOS pipe M8 is the secondary signal input end of duty cycle circuit 423.
As shown in Figure 8, in the present embodiment, register file 41 comprises decoding scheme module 411, memory cell array 412, sense amplifier 413, selector switch 414, latch 415, second control circuit module 416 and FIFO output circuit 417, decoding scheme module 411 comprises one-level decoding scheme unit 4111 and two-stage decode circuit unit 4112, one-level decoding scheme unit 4111 comprises first trigger, second trigger, the 3rd trigger, first code translator, second code translator and the 3rd code translator, first trigger is connected with first code translator, second trigger is connected with second code translator, the 3rd trigger is connected with the 3rd code translator, two-stage decode circuit unit 4112 comprises three inputs and door and load driver module, first code translator, second code translator and the 3rd code translator and three inputs connect one to one with three input ends of door, three inputs are connected with the load driver module with the output terminal of door, the load driver module is connected with memory cell array 412, memory cell array 412 is connected with sense amplifier 413, sense amplifier 413 is connected with selector switch 414, selector switch 414 is connected with latch 415, latch 415 is connected with FIFO output circuit 417, second control circuit module 416 respectively with memory cell array 412, sense amplifier 413, selector switch 414 is connected with latch 415, and memory cell array 412 comprises at least two storage unit; First trigger, second trigger and the 3rd trigger are d type flip flop, and first code translator and second code translator are the 2-4 code translator, and the 3rd code translator is the 1-2 code translator.
The design concept of restructural multiport PUF circuit unit of the present invention (RM-PUFs unit) is as described below:
The element set that at first defines restructural multiport PUF circuit unit is { S, F, N, C, R
0R
1... R
n, wherein, S is state space, and F is function space, and N is output key port number, and C is excitation space, R
0R
1... R
nBe the response space.In restructural multiport PUF circuit unit, function space F is the physical characteristics decision by circuit itself; State space S is determined by external input signal, can be called soft key.The output response of restructural multiport PUF circuit unit determines jointly that by physical characteristics and the soft key of circuit itself example model can be expressed as:
R(c)←F(N,R(S,C)),R(c)∈R
0R
1…R
n (1)
After introducing soft key concept, the RM-PUFs unit will be a kind of brand-new excitation-response modes.In conjunction with the definition of RM-PUFs unit and the thought of circuit design, we can obtain the structured flowchart of RM-PUFs unit as shown in Figure 1.The RM-PUFs unit comprises first control circuit module, load module, output module and process deviation generation module at random; The first control circuit module produces pumping signal C and output key port number N behind input enable signal rconf (); Load module is soft key S and pumping signal C,, through behind the process deviation generation module at random, final data exported in process deviation generation module at random by mapin () Function Mapping.The RM-PUFs unit can change current state space S * by soft key, changes the port number N that exports key by control signal, reconstruct output key and port number, the multiport restructural function of realization RM-PUFs unit.
The course of work of RM-PUFs element circuit can be divided into configuration phase, input phase, reconstruction stage and output stage:
1, internal register in the configuration phase initial configuration RM-PUFs unit comprises state space S, excitation space C and port number N;
2, input phase is input to pumping signal C among the function rconf () after configuration phase is finished, and the output of function rconf () is as the input signal of mapping function mapin (); The output signal conduct of mapping function mapin () is the pumping signal of process deviation generation module PUF () at random;
3, the soft key of reconstruction stage is by in load module state () the input RM-PUFs unit, the state S of inside, RM-PUFs unit changed to state S*, and then reach the output response of reconstruct RM-PUFs unit;
4, the output stage output module receives the output signal of process deviation generation module PUF () at random, according to the port number N of rconf () output, with the N group excitation/response of RM-PUFs unit to (C*, R*) output.
In the implementation of RM-PUFs unit, need to design respectively four basic modules.Wherein, the first control circuit module adopts state machine to realize; Load module and output module adopt fan-in network and the output network that is made of d type flip flop respectively; The process deviation generation module is realized by asynchronous clock at random.In the RM-PUFs unit, the soft key of register file stores is realized the multiport technology; External circuit upgrades the soft key of register file, realizes the restructural technology.Asynchronous clock comprises the first clock signal clock_s and second clock signal clock_f, and wherein clock_s is 0-50MHz, is provided by global clock; Clock_f is 500M-1GHz, and (VCO) provides by oscillator.For extraction process deviation farthest, under TSMC65nm technology, we adopt full method for customizing to realize the VCO circuit, and physical circuit as shown in Figure 3.The VCO circuit comprise differential delay circuit, level translator, duty cycle circuit and frequency divider.The differential delay circuit is connected and composed by odd number differential delay unit annular, circuit diagram as shown in Figure 4, its f
OscFrequency can be expressed as:
f
osc=1/(2M·T
D) (2)
Wherein, T
DBe the time delay of differential delay unit, M is that the quantity of differential delay unit is (in the design, M=9).The structure of differential delay unit as shown in Figure 5.Because chip is at the process deviation of manufacture process, at identical control voltage V
Ctr, the output frequency difference of different chip VCO.Level translator with the voltage of VCO output frequency from V
CtrBe transformed into and work as V
DdThe structure of level translator as shown in Figure 6, principle of work is as follows: work as X
i=V
Ss, M
3End M
4Conducting, in_a=V
SsWork as X
i=V
Ctr, M
3Conducting, M
4End P
4Conducting, in_a=V
DdThe frequency of in_a output clock keeps X
iFrequency is identical; The low level of in_a is V
Ss, high level is V
DdDuty cycle circuit is one of important indicator of VCO, and target of the present invention is that dutycycle is 50%.The structure of duty cycle circuit as shown in Figure 7, principle of work is as follows: work as in_a=V
Dd, M
7And P
7All conductings, out=V
DdWork as in_a=V
Ss, out will continue at high voltage, up to in_b=V
Dd, M
8And P
8All be conducting, out=V
SsWork as in_b=V
Ss, out will continue at high voltage, up to in_b=V
DdBecause in_a and in_b are differential signal, so dutycycle is 50%.
In the restructural multiport PUF circuit unit of the present invention, first d type flip flop 21 in the load module 2, second d type flip flop 22 and 3d flip-flop 23 receive trigger for data, first d type flip flop in each d type flip flop group 43 is the data sampling trigger, second d type flip flop in each d type flip flop group 43 is the data capture trigger, and the data-signal of input is stored in the register file 41 by receiving trigger; Register file 41 is at second clock signal controlling down-sampling, and stores data in the data sampling trigger; At last, under the control of first clock signal, sampled value is exported by the serial of data capture trigger.The logical value of final output is determined by data-signal and the frequency departure between the asynchronous clock of input.Because the process deviation that exists in the manufacture process, under the VCO of same structure, the frequency departure difference between the different chips, and then cause the difference of output logic value, the change that can realize exporting key by the data-signal that changes input thus.
Claims (7)
1. restructural multiport PUF circuit unit, it is characterized in that comprising the first control circuit module, load module, output module and process deviation generation module at random, described first control circuit module is provided with the enable signal input end, the pumping signal output terminal, control signal output terminal and output key port number output terminal, described load module is provided with the external signal input end, pumping signal input end and signal output part, described output module is provided with the port number input end, signal input part and signal output part, the described generation module of process deviation at random is provided with the control signal end, signal input part and signal output part, the pumping signal output terminal of described first control circuit module is connected with the pumping signal input end of described load module, the output key port number output terminal of described first control circuit module is connected with the port number input end of described output module, the control signal output terminal of described first control circuit module is connected with the control end of the described generation module of process deviation at random, the signal output part of described load module is connected with the signal input part of the described generation module of process deviation at random, the signal output part of the described generation module of process deviation at random is connected with the signal input part of described output module, and the signal that the external signal input end of described load module inserts comprises data-signal, address signal and control voltage signal.
2. restructural multiport PUF circuit unit according to claim 1, it is characterized in that described load module is by first d type flip flop, second d type flip flop and 3d flip-flop are formed, the described first d type flip flop incoming data signal, the described second d type flip flop access address signal, described 3d flip-flop Access Control voltage signal and first clock signal, the described generation module of process deviation at random comprises register file, oscillator and N d type flip flop group that is in series by two d type flip flops, described register file respectively with described first d type flip flop, described second d type flip flop, described oscillator is connected with N d type flip flop group, described oscillator is connected with first d type flip flop in each d type flip flop group with described 3d flip-flop respectively, second d type flip flop in each d type flip flop group inserts described first clock signal, the output signal of described oscillator is the second clock signal, described output module is made up of N output unit, each output unit is in series by latch and FIFO output circuit, second d type flip flop in latch in N output unit and N the d type flip flop group connects one to one, described first control circuit module respectively with described first d type flip flop, described second d type flip flop, described 3d flip-flop is connected with FIFO output circuit in N the output unit, the frequency of described first clock signal is 0～50MHz, the frequency of described second clock signal is 500M-1GHz, N 〉=2.
3. restructural multiport PUF circuit unit according to claim 2, it is characterized in that described oscillator comprises the differential delay circuit, level translator, duty cycle circuit and frequency divider, described differential delay circuit is provided with control voltage signal input end, first signal output part, the secondary signal output and ground, described level translator is provided with first signal input part, the secondary signal input end, first signal output part, the secondary signal output terminal, d. c. voltage signal input end and earth terminal, described duty cycle circuit is provided with first signal input part, the secondary signal input end, d. c. voltage signal input end and earth terminal, first signal output part of described differential delay circuit is connected with first signal input part of described level translator, the secondary signal output terminal of described differential delay circuit is connected with the secondary signal input end of described level translator, first signal output part of described level translator is connected with first signal input part of described duty cycle circuit, the secondary signal output terminal of described level translator is connected with the secondary signal input end of described duty cycle circuit, the signal output part of described duty cycle circuit is connected with the signal input part of described frequency divider, the earth terminal of described differential delay circuit, the earth terminal of described level translator is connected with the earth terminal of described duty cycle circuit, the d. c. voltage signal input end of described level translator and the d. c. voltage signal input end of described duty cycle circuit are connected, the control voltage signal input end of described differential delay circuit is the signal input part of described oscillator, and the signal output part of described frequency divider is the signal output part of described oscillator.
4. restructural multiport PUF circuit unit according to claim 3, it is characterized in that described differential delay circuit is made up of 2n+1 differential delay unit, described differential delay unit is provided with first signal input part, the secondary signal input end, first signal output part, the secondary signal output terminal, control voltage signal input end and earth terminal, the control voltage signal input end connection of 2n+1 differential delay unit and its link are as the control voltage signal input end of described differential delay circuit, the earth terminal connection of 2n+1 differential delay unit and its link are as the earth terminal of described differential delay circuit, first signal output part of the differential delay unit of last position is connected with first signal input part of back one differential delay unit in 2n+1 differential delay unit, the secondary signal output terminal of the differential delay unit of last position is connected with the secondary signal input end of back one differential delay unit in 2n+1 differential delay unit, first signal input part of the first potential difference branch delay cell in first signal output part of last potential difference branch delay cell in 2n+1 differential delay unit and 2n+1 the differential delay unit is connected, the secondary signal input end of the first potential difference branch delay cell in the secondary signal output terminal of last potential difference branch delay cell in 2n+1 differential delay unit and 2n+1 the differential delay unit is connected, last potential difference in 2n+1 differential delay unit is divided first signal output part of first signal output part of delay cell as described differential delay circuit, last potential difference in 2n+1 differential delay unit is divided the secondary signal output terminal of the secondary signal output terminal of delay cell as described differential delay circuit, wherein n 〉=1.
5. restructural multiport PUF circuit unit according to claim 4, it is characterized in that described differential delay unit managed by a PMOS, the 2nd PMOS pipe, the one NMOS pipe and the 2nd NMOS pipe are formed, the drain electrode of a described PMOS pipe is connected with the drain electrode of described the 2nd PMOS pipe and its link is the control voltage signal input end of described differential delay unit, the grid of a described PMOS pipe, the drain electrode of the source electrode of described the 2nd PMOS pipe and described the 2nd NMOS pipe is connected and its link is first signal output part of described differential delay unit, the source electrode of a described PMOS pipe, the drain electrode of the grid of described the 2nd PMOS pipe and a described NMOS pipe is connected and its link is the secondary signal output terminal of described differential delay unit, the source electrode of the source electrode of a described NMOS pipe and described the 2nd NMOS pipe M2 is connected and its link is the earth terminal of described differential delay unit, the grid of a described NMOS pipe is first signal input part of described differential delay unit, and the grid of described the 2nd NMOS pipe is the secondary signal input end of described differential delay unit; Described level translator is managed by the 3rd PMOS, the 4th PMOS pipe, the 5th PMOS pipe, the 6th PMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, the 5th NMOS pipe, the 6th NMOS pipe, first phase inverter and second phase inverter are formed, the drain electrode of described the 3rd PMOS pipe, the drain electrode of described the 4th PMOS pipe, the drain electrode of the drain electrode of described the 5th PMOS pipe and described the 6th PMOS pipe is connected and its link is the d. c. voltage signal input end of described level translator, the grid of described the 3rd PMOS pipe, the drain electrode of the source electrode of described the 4th PMOS pipe and described the 4th NMOS pipe is connected and its link is first signal output part of described level translator, the source electrode of described the 3rd PMOS pipe, the drain electrode of described the 3rd NMOS pipe is connected with the grid of described the 4th PMOS pipe, the input end of the grid of described the 3rd NMOS pipe and described first phase inverter is connected and its link is first signal input part of described level translator, the output terminal of described first phase inverter is connected with the grid of described the 4th NMOS pipe, the source electrode of described the 3rd NMOS pipe, the source electrode of described the 4th NMOS pipe, the source electrode of the source electrode of described the 5th NMOS pipe and described the 6th NMOS pipe is connected and its link is the earth terminal of described level translator, the grid of described the 5th PMOS pipe, the drain electrode of the source electrode of described the 6th PMOS pipe and described the 6th NMOS pipe is connected and its link is the secondary signal output terminal of described level translator, the source electrode of described the 5th PMOS pipe, the drain electrode of described the 5th NMOS pipe is connected with the grid of described the 6th PMOS pipe, the input end of the grid of described the 5th NMOS pipe and described second phase inverter is connected and its link is the secondary signal input end of described level translator, and the output terminal of described second phase inverter is connected with the grid of described the 6th NMOS pipe; Described duty cycle circuit is managed by the 7th PMOS, the 8th PMOS pipe, the 7th NMOS pipe and the 8th NMOS pipe are formed, the drain electrode of the drain electrode of described the 7th NMOS pipe and described the 7th PMOS pipe is connected and its link is the d. c. voltage signal input end of described duty cycle circuit, the source electrode of described the 7th NMOS pipe, the source electrode of described the 7th PMOS pipe, the drain electrode of the drain electrode of described the 8th NMOS pipe and described the 8th PMOS pipe is connected and its link is the signal output part of described duty cycle circuit, the source electrode of the source electrode of described the 8th NMOS pipe and described the 8th PMOS pipe is connected and its link is the earth terminal of described duty cycle circuit, the grid of described the 7th NMOS pipe is first signal input part of described duty cycle circuit, and the grid of described the 8th NMOS pipe is the secondary signal input end of described duty cycle circuit.
6. restructural multiport PUF circuit unit according to claim 2, it is characterized in that described register file comprises the decoding scheme module, memory cell array, sense amplifier, selector switch, latch, second control circuit module and FIFO output circuit, described decoding scheme module comprises one-level decoding scheme unit and two-stage decode circuit unit, described one-level decoding scheme unit comprises first trigger, second trigger, the 3rd trigger, first code translator, second code translator and the 3rd code translator, described first trigger is connected with described first code translator, described second trigger is connected with described second code translator, described the 3rd trigger is connected with described the 3rd code translator, described two-stage decode circuit unit comprises three inputs and door and load driver module, described first code translator, described second code translator and described the 3rd code translator and described three inputs connect one to one with three input ends of door, described three inputs are connected with described load driver module with the output terminal of door, described load driver module is connected with described memory cell array, described memory cell array is connected with described sense amplifier, described sense amplifier is connected with described selector switch, described selector switch is connected with described latch, described latch is connected with described FIFO output circuit, described second control circuit module respectively with described memory cell array, described sense amplifier, described selector switch is connected with described latch, and described memory cell array comprises at least two storage unit.
7. restructural multiport PUF circuit unit according to claim 6, it is characterized in that described first trigger, described second trigger and described the 3rd trigger are d type flip flop, described first code translator and described second code translator are the 2-4 code translator, and described the 3rd code translator is the 1-2 code translator.
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