CN107145804B - Low-overhead RO PUF circuit structure based on FPGA - Google Patents
Low-overhead RO PUF circuit structure based on FPGA Download PDFInfo
- Publication number
- CN107145804B CN107145804B CN201710315266.9A CN201710315266A CN107145804B CN 107145804 B CN107145804 B CN 107145804B CN 201710315266 A CN201710315266 A CN 201710315266A CN 107145804 B CN107145804 B CN 107145804B
- Authority
- CN
- China
- Prior art keywords
- output
- dual
- input
- bit
- puf
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0866—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
- H04L9/0861—Generation of secret information including derivation or calculation of cryptographic keys or passwords
- H04L9/0869—Generation of secret information including derivation or calculation of cryptographic keys or passwords involving random numbers or seeds
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
- H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
Abstract
The invention discloses an RO PUF circuit structure with low overhead based on FPGA, belonging to the field of information security and hardware security, in particular to the field of chip authentication and key generation.A configurable delay unit of the PUF circuit is odd-order dual-output RO, a configurable delay unit is dual-output L UT, the functions of two single-output L UT inside the PUF circuit are initialized into an inverter and a selector for selecting which inverter the signal passes through.
Description
Technical Field
The invention relates to the fields of information security and hardware security, in particular to the fields of chip authentication and key generation, and by designing a PUF circuit in an FPGA, the circuit can be used for converting small difference of on-chip device delay into a random sequence code unique to a chip, and the random sequence code can be used for generating a chip ID and a key. In addition, the method can also be used for the protection aspect of the IP core of the integrated circuit.
Background
With the development of information technology, the problems of information security and hardware security become more and more severe. In the field of super-large scale integrated circuit development, the reuse of Intellectual Property (IP) cores greatly reduces the development period of projects and reduces the development difficulty of projects; however, the problem of unauthorized use of IP core piracy is also increasingly highlighted. A physical unclonable function is a function that outputs a random unique binary sequence using the uncontrollable deviations that a physical entity experiences during its fabrication. Foreign researchers have studied physical unclonable functions for over a decade, and silicon PUFs, which are the relatively hot class of recent research, are physically unclonable circuits that can exploit differences in device delay size due to uncontrolled variations in the fabrication of integrated circuits to generate random binary sequences. For example, the RO PUF uses an odd number of inverters with the same number to form a plurality of oscillation rings, the oscillation rings are arranged at different positions of a chip, process deviations exist in devices at different positions of the chip, so that RO oscillation frequencies at different positions are likely to be different, the frequency of oscillators are compared pairwise to obtain a frequency difference, the binary output of the PUF is represented by the positive and negative of the frequency difference, the more ROs are arranged, the more response bits of the obtained PUF output are, and the more hardware resources are consumed. In the PUF research based on the FPGA platform, the rocpuf is paid attention to by a large number of researchers, because the basic device in the implementation of the RO PUF is relatively simple, the requirement on wiring is not high, and meanwhile, the FPGA has abundant computing units and logic units to count and compare the frequency of the RO.
The reconstructed RO PUF is realized by setting an AND gate enabling end, starting oscillation operation of the RO, counting the frequencies of the two ROs through a counter, and obtaining the frequency difference of the two ROs through a comparator to obtain a one-bit output response of the two ROs, wherein when the reconstructed RO PUF is realized on the FPGA, each configurable delay unit occupies one PUF L UT, each enabling unit occupies one PUF UT L, and at least 16 PUFs L are needed to realize the two ROs, so that the one-bit PUF output response is obtained, L resources are consumed by the FPGA with large resource consumption, and many PUFs cannot be occupied to realize the PUF circuit.
Disclosure of Invention
One object of the present invention is to propose a low-overhead ROPUF circuit structure based on L UT6_2 with dual outputs in FPGA, which has smaller hardware overhead and stronger universality and can be used to generate a true random sequence only related to uncontrollable deviation in chip manufacturing process as the credible random input data of a chip ID or a key generator.
The basic unit of the PUF circuit is an odd-order dual-output RO which is composed of a configurable delay unit L UT6_2, two L UT5 with single output in the circuit are initialized to be an inverter and a selector, and the two inverters are used for selecting the inverter to pass through.
According to the invention, by utilizing the structural characteristic that L UT6_2 in the FPGA is composed of two L UT5, the designed double-output RO PUF circuit saves nearly half L UT resources compared with the traditional RO PUF circuit.
In order to achieve the purpose, the technical scheme adopted by the invention is a low-overhead ROPUF circuit structure based on a FPGA L UT6_2, the circuit consists of a dual-output enabling unit and seven dual-output configurable delay units, the enabling unit consists of two AND gates, the inputs of one of the two AND gates are connected with each other, the input end of the other AND gate is connected with feedback signals of two oscillation rings, the configurable delay unit consists of two inverters and two alternative selectors, two paths of signals are connected into two inputs of the unit after being output from the AND gates, and are respectively connected into different input ends of the selectors after being inverted by the inverters, the signals are connected into two oscillation signal input ends of the next configurable delay unit after being output from the selectors, finally, the output end of the last configurable delay unit is fed back to the feedback input end of the enabling unit as shown in FIG. 2, the structure diagram of the inventive dual-output RO is provided, the output of the AND gates is always 0 before being set, the output of the inverter is always 1 after passing through the odd-level stage, the RO ring is always in a state, the RO is in a RO-output of the AND gate, the RO unit is set up-down state, the RO signal is set by the selection of the selection unit, the selection delay unit, the two output of the two adjacent dual-stage configurable delay units, the two adjacent dual-stage controllable delay units, the two adjacent dual-stage dual-delay units, the two oscillation units, the adjacent dual-delay units are replaced by the adjacent dual-stage.
The internal structure of UT _2 of FPGA is shown in FIG. 1, two UTs share five input address lines of 0UT _2, and in dual-Output RO, the inputs of two selectors forming their basic delay units are also shared, so, to fully utilize two 2 UTs of 1UT _2, one basic unit of dual-Output RO is arranged in one 3UT _2, A and A are two input ends of the selectors, A is a control end of the selectors, as shown in FIG. 4, a structure diagram of an inventive 1-bit response circuit based on FPGA basic logic unit, namely 4UT _2 is shown, only the internal signal flow direction of 5UT stage of one configurable delay unit is described in FIG. 4, the other configurable delay units do not have 6UT stage description listed one by one, as seen from FIG. 4, the dual-Output RO has two Output ends, the configuration of odd number of configurable delay units, each delay unit is realized by one 7UT _2, and such 8UT _2 is composed of two same mode UT 9, as shown in FIG. 1, the input end of UT _2 is connected with the input end of UT _2, the input end of the signal is connected with the input end of the UT _2, the input end of the signal, the Output end of the UT _2, and the input end of the Output end of the signal is connected with the input end of the external signal, the input end of the external signal, the external input end of the external signal, the external Output end of the external signal is controlled by the external Output end of the external signal, the external unit, the external signal is.
The configurable delay unit of the dual-output RO has two L UT5, in order to realize the function of the selection inverter, an initial value for realizing the function needs to be set for L UT6_2, the upper 32 bits of the 64-bit initial value are the initial value of the upper L UT5 and should be set to 0x00000053, the lower 32 bits are the initial value of the lower L UT5 and should be 0x 00000035. the enabling unit of the dual-output RO is two AND gates, one input end of the two AND gates is interconnected, the other two input ends are respectively connected with the feedback signal of the oscillation loop, similarly, the two AND gates are respectively realized in two L UT5, and the initial values of two L UT5 are respectively 0x000000a0 and 0x000000c 0.
The invention can configure inverters with different delay sizes through the configuration bit, form two RO. with different frequencies, use a counter to count respective oscillation frequencies at two output ends of the RO, use a comparator to obtain the frequency difference of the RO, and obtain the output response of the 1-bit PUF according to the positive and negative of the frequency difference.
Drawings
Fig. 1 is an internal structure diagram of a basic delay unit of a dual-output RO and L UT6_2, and the specific arrangement of each device of the basic delay unit in the L UT is also indicated in the diagram.
FIG. 2 is a schematic diagram of an inventive dual output RO, consisting of two units: an enabling unit and a delay unit.
FIG. 3 is an equivalent schematic diagram of the dual output RO of the present invention, with the inverter and selector reversed, illustrating the internal signal flow of the two oscillator rings of the dual output RO under a particular input excitation.
Fig. 4 is a one-bit-response dual-output RO PUF circuit structure under a specific input stimulus, illustrating a signal flow diagram in a dual-output RO with L UT level configurable delay cells, wherein the highest bit a6 of L UT6_2 is kept high, A3 is used as a selection control bit, and a1 and a2 are respectively signal input terminals of an oscillation ring.
Fig. 5 is a 7-order reconstructed RO PUF implementation.
Table 1 is a comprehensive comparison of the inventive delay measurement circuit with the reconstructed RO PUF scheme shown in fig. 5.
Detailed Description
The structure of the implementation circuit of a ring oscillator PUF on an FPGA is as shown in fig. 4, which lists a L UT-level circuit design in which one delay cell is implemented in the FPGA, and each delay cell constituting an oscillation ring, i.e., each L UT6_2 implementing the function of the delay cell, is constrained by a planhead tool within the same C L B of the FPGA, after the output of the and gate, each delay cell enters two single-output L UT, <tttranslation = L "&tttl <tt/t >ttut's a3 bit is a control bit, which determines which signal passes through the present L UT, for example, the value of the 7-bit control bit is" 1100000 "in the figure, when the control bit is 1, the paths are to be crossed, the solid line and dotted line in the figure showing two ring oscillator PUFs are interchanged, and the flow direction of the two pre-PUF signals to the PUF is shown as" 1100000 ", and the principle that the two delay cells are mutually connected by two straight lines is that the RO transmission path crossing circuit design is implemented on the basis of the present invention, the principle that the two RO transmission circuit design is not a straight line, the two RO crossing channel crossing circuit design, and the invention, the RO transmission circuit design is implemented by adopting the following two straight line design, the principle that the invention, the principle that the two straight line crossing channel design is also has No. 3 is implemented by the invention, the invention is not only has No. 3 is implemented:
step 1: designing a 7-order dual-output RO with an enable control bit by using a schematic diagram mode;
and step 3: integrating the circuits designed in the first two steps to obtain an instantiated template of the double-output RO, and instantiating the double-output RO in the program;
and 5: downloading a program, and sending 7-bit configuration bit information of a seven-order dual-output RO through a serial port, for example, the configuration is 1100000;
step 6: setting the enabling end x0 of the double-output RO, starting oscillation of the two oscillation rings simultaneously, and counting the natural frequency of the two RO by a counter;
and 7: and after setting and enabling for 100ms, resetting the enabling end x [0] of the double-output RO, and comparing the two frequencies through a comparator to obtain the output response of the one-bit PUF.
In addition, the invention realizes two branches in a single C L B of the FPGA, the connecting line between used RO devices does not need to cross C L B, the connecting line between the devices is reduced, the reliability and the safety of the RO PUF are indirectly improved, and when the circuit with the same order and the same number of output bits of the PUF output bits on the FPGA is realized, the hardware cost of the circuit with the same order and the same number of output bits of the PUF is only 50% of the hardware cost required by the invention, which is only 50% of the hardware cost required by the invention.
TABLE 1
| Name of circuit | ROOrder of the scale | PUF response bit number | L UT logical resources |
| Dual- |
7 | 1 | 8 |
| Reconstructing |
7 | 1 | 16 |
Claims (2)
1. A low-overhead RO PUF circuit structure based on FPGA is characterized in that the circuit structure consists of a dual-output enabling unit and seven dual-output configurable delay units, wherein the enabling unit consists of two AND gates, the input of one of the two AND gates is connected with each other, the input end of the other AND gate is connected with feedback signals of two oscillation rings, the configurable delay unit consists of two inverters and two alternative selectors, two paths of signals are connected into two inputs of the configurable delay units after being output from the AND gates, and are respectively connected into different input ends of the selectors after being reversed by the inverters, the signals are connected into two oscillation signal input ends of the configurable delay unit of the next stage after being output from the selectors, finally, the output signals of the configurable delay unit of the last stage are fed back to the feedback input ends of the enabling unit, the output of the AND gate is always 0 before being set, the output of the RO is always 0 after passing through the inverters of the odd stages, the output of the oscillation rings is always 1, the RO is in a closed state, after being set, the output of the AND gate is always equal to be equal to or less than 1, the output of the AND gate is always equal to be equal to or less than or equal to be equal to the output of;
in the internal structure of L UT6_2 of FPGA, two 6UT6 share five-bit address line of 6UT6_2, and in dual-Output RO, the inputs of two selectors forming basic delay units are also shared, so to fully utilize two 6UT6 forming 6_2, one basic unit of dual-Output RO is arranged in one 6 3UT6_2, A6 and A6 are allocated as two inputs of the selectors, A6 is the control end of the selector, based on FPGA basic logic unit, the dual-Output RO has two outputs, each time delay unit is realized by one 6UT6_2, two 6UT 72 share the lower five bits of the input 6UT 72 UT _2, the highest bit of 6UT 2 is connected with the input of the upper input 6UT 72 UT 6UT 72 UT 6A, the input of the upper input 6UT 72 UT is connected with the upper input 6UT 72A, the input of the upper input 6UT 72 UT, the input end 6UT 72 UT is connected with the upper input end 6UT 72 UT, the upper input end 6UT 72 UT 6UT 3;
the configurable delay unit of the dual-output RO is provided with two L UT5, in order to realize the function of the selection inverter, an initial value for realizing the function needs to be set for L UT6_2, the upper 32 bits of a 64-bit initial value are initial values of upper L UT5 and are set as 0x00000053, the lower 32 bits of the 64-bit initial value are initial values of lower L UT5 and are set as 0x00000035, the enabling units of the dual-output RO are two AND gates, one input end of the two AND gates is interconnected, the other two input ends are respectively connected with feedback signals of an oscillation ring, similarly, the two AND gates are respectively realized in two single outputs L UT, and the initial values of the upper L UT5 and the lower 8600 UT5 are respectively 0x000000a0 and 0x000000c 0;
configuring signal paths with different delay sizes through configuration bits to form two ROs with different frequencies; counting respective oscillation frequencies by using a counter at two output ends of the RO; then, a comparator is used for obtaining the frequency difference of the RO, and the output response of the 1-bit PUF is obtained according to the positive and negative of the frequency difference; by arranging a plurality of dual-output RO units in different areas of the chip, and comparing their natural frequencies, a multi-bit output PUF circuit is obtained.
2. An FPGA-based low-overhead RO PUF circuit structure according to claim 1, wherein a dual-output RO PUF is designed on the FPGA with the basic steps of:
step 1: designing a 7-order dual-output RO with an enable control bit;
step 2, setting an initial value of L UT6_2 used for realizing an enable AND gate to be 0x000000c0_000000a0, and setting an initial value of L UT6_2 used for realizing a delay unit to be 0x00000035_ 00000053;
and step 3: integrating the circuits designed in the first two steps to obtain an instantiated template of the double-output RO, and instantiating the double-output RO in the program;
step 4, using a PlanAdead tool to constrain L UT6_2 realizing enabling and L UT6_2 realizing 7 delay units in the same C L B;
and 5: downloading a program, and sending 7-bit configuration bit information of the seven-order dual-output RO through a serial port;
step 6: setting the enabling end x0 of the double-output RO, starting oscillation of the two oscillation rings simultaneously, and counting the natural frequency of the two RO by a counter;
and 7: and after setting and enabling for 100ms, resetting the enabling end x [0] of the double-output RO, and comparing the values of the two counters through a comparator to obtain the output response of the one-bit PUF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710315266.9A CN107145804B (en) | 2017-05-08 | 2017-05-08 | Low-overhead RO PUF circuit structure based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710315266.9A CN107145804B (en) | 2017-05-08 | 2017-05-08 | Low-overhead RO PUF circuit structure based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107145804A CN107145804A (en) | 2017-09-08 |
| CN107145804B true CN107145804B (en) | 2020-07-24 |
Family
ID=59777939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710315266.9A Active CN107145804B (en) | 2017-05-08 | 2017-05-08 | Low-overhead RO PUF circuit structure based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107145804B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108540109A (en) * | 2018-04-11 | 2018-09-14 | 中国电子科技集团公司第五十八研究所 | Physical fingerprint generative circuit based on ring oscillator and method |
| CN110442889B (en) * | 2018-05-03 | 2021-07-09 | 北京大学 | Circuit credibility design method based on PUF and fuzzy processing |
| CN108985105B (en) * | 2018-08-22 | 2022-01-11 | 合肥工业大学 | Method for generating physical unclonable function based on ring oscillator |
| CN109241781A (en) * | 2018-09-04 | 2019-01-18 | 合肥工业大学 | XOR gate RO PUF circuit and its working method are reconfigured based on FPGAs |
| CN109766672B (en) * | 2019-01-14 | 2022-07-12 | 湖南大学 | Anonymous authentication method for core copyright |
| CN110096397B (en) * | 2019-03-27 | 2022-10-25 | 天津大学 | Multi-ring oscillator FPGA configuration circuit robustness detection method |
| CN111565110B (en) * | 2020-05-09 | 2022-03-04 | 西安电子科技大学 | Unified identity authentication system and method based on RO PUF multi-core system |
| CN112187464B (en) * | 2020-08-19 | 2022-07-26 | 合肥工业大学 | Low-overhead design method of hybrid configurable RO PUF (reverse osmosis physical unclonable function) by utilizing cross path selection structure |
| US11379125B1 (en) | 2021-03-31 | 2022-07-05 | International Business Machines Corporation | Trusted field programmable gate array |
| CN116208145B (en) * | 2023-04-27 | 2023-08-04 | 湖北工业大学 | FPGA-based low-overhead tri-state PUF circuit and configuration method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236922A (en) * | 2013-04-23 | 2013-08-07 | 曹元� | Circuit and electronic device with physical unclonable function, and implementation method for circuit and electronic device |
| CN103902930A (en) * | 2014-03-10 | 2014-07-02 | 杭州晟元芯片技术有限公司 | Physical unclonable function circuit structure based on ring oscillators |
| CN106533654A (en) * | 2016-10-12 | 2017-03-22 | 南京航空航天大学 | Configurable physically unclonable function circuit and response generation method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9015500B2 (en) * | 2013-01-16 | 2015-04-21 | Qualcomm Incorporated | Method and apparatus for using dynamic voltage and frequency scaling with circuit-delay based integrated circuit identification |
-
2017
- 2017-05-08 CN CN201710315266.9A patent/CN107145804B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103236922A (en) * | 2013-04-23 | 2013-08-07 | 曹元� | Circuit and electronic device with physical unclonable function, and implementation method for circuit and electronic device |
| CN103902930A (en) * | 2014-03-10 | 2014-07-02 | 杭州晟元芯片技术有限公司 | Physical unclonable function circuit structure based on ring oscillators |
| CN106533654A (en) * | 2016-10-12 | 2017-03-22 | 南京航空航天大学 | Configurable physically unclonable function circuit and response generation method thereof |
Non-Patent Citations (3)
| Title |
|---|
| An Ultra-low Overhead LUT-based PUF for FPGA;Jiadong Wang等;《2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST)》;20170130;全文 * |
| 基于FPGA的ROPUF研究;唐彬;《万方数据知识服务平台》;20151228;全文 * |
| 改进的可配置RO PUF及其实现;丁浩等;《计算机工程与设计》;20151030(第10期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107145804A (en) | 2017-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107145804B (en) | Low-overhead RO PUF circuit structure based on FPGA | |
| CN104200180B (en) | Physical unclonable function based on reconfigurable ring oscillators and generation method of physical unclonable function based on reconfigurable ring oscillators | |
| Lim et al. | Sequential circuit design using Quantum-dot Cellular Automata (QCA) | |
| CN106533654B (en) | Configurable physics unclonable function circuit and its response production method | |
| CN104270141B (en) | Anti-single particle overturns the latch with single event transient pulse | |
| WO2019222866A1 (en) | True random number generation method and device having detection and correction functions | |
| CN109460681B (en) | Configurable physical unclonable function circuit based on delay chain | |
| CN103198268A (en) | Reconfigurable multi-port physical unclonable functions (PUF) circuit | |
| CN101213749A (en) | Multi-bit programmable frequency divider | |
| EP3455723B1 (en) | Generating and checking a quaternary pseudo random binary sequence | |
| CN103198267A (en) | Reconfigurable multi-port physical unclonable functions (PUF) circuit unit | |
| WO2017186816A1 (en) | Strong lightweight flip-flop arbiter physical unclonable function (puf) for fpga | |
| CN108509180A (en) | One kind is based on two input XOR gate low-power consumption random number generating apparatus | |
| CN102968290A (en) | Isomeric lightweight class true random number generator | |
| Mureddu et al. | Experimental study of locking phenomena on oscillating rings implemented in logic devices | |
| US8044833B2 (en) | High speed serializer | |
| CN113672199A (en) | Multi-entropy source random number generator with physical unclonable function | |
| CN105303127B (en) | Physics unclonable function circuit structure and its application based on tristate inverter | |
| CN105656474B (en) | A kind of FPGA subscriber's line circuit logic inversion optimization method based on signal probability | |
| Nair et al. | FPGA on cyber-physical Systems for the Implementation of Internet of Things | |
| CN110166041A (en) | Latch | |
| CN110336536A (en) | The circuit and equipment of real random number generator | |
| CN115758951A (en) | Digital entropy source integrated circuit based on multi-loop Boolean oscillation ring | |
| CN109086631B (en) | Strong/weak mixed PUF circuit for resisting model attack | |
| Sahoo et al. | Fault tolerant implementations of delay-based physically unclonable functions on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |