CN106303312B - Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor - Google Patents
Two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor Download PDFInfo
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- CN106303312B CN106303312B CN201610664364.9A CN201610664364A CN106303312B CN 106303312 B CN106303312 B CN 106303312B CN 201610664364 A CN201610664364 A CN 201610664364A CN 106303312 B CN106303312 B CN 106303312B
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- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
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Abstract
The present invention provides a kind of two-dimensional random Sequence Generation circuit and its working method for compressed sensing cmos image sensor, comprising: row linear feedback shift register, for generating pixel column random number and passing to trigger group by the method for displacement；Linear feedback shift register, for generating pixel column random number and passing to trigger group by the method for displacement；Trigger group provides input signal based on the pixel column random number and/or pixel column random number received for logic gate；Logic gate realizes corresponding Digital Logic based on the input signal, to generate all random numbers for entire pixel array.The method that the present invention is combined using linear feedback shift register and common shift register realizes that a kind of sequence is adjustable, mode is optional, ranks random (two dimension), complexity is low is convenient for hard-wired random number generation circuit.The configuration of the present invention is simple is with a wide range of applications in compressed sensing cmos image sensor design field.
Description
Technical field
The invention belongs to cmos image sensor design fields, pass more particularly to one kind for compressed sensing cmos image
The two-dimensional random Sequence Generation circuit and its working method of sensor.
Background technique
Random sequence sequence widely applies to communication system, information security, finance modeling, economics emulation and Molecule Motion
The fields such as mechanics.In addition to this, in compressed sensing imaging process, in order to be read at random to pixel array, random sequence
Generation circuit becomes its important component.
The research of random sequence generator based on software realization has had long history.Domestic and international related fields
Scientist proposes a variety of pseudo random sequence generation methods, including linear congruential method, non-linear congruence method, shift-register sequence
Generator, compound number-of-pixels generator and combination generator etc..On software view, concern focus on obtain sequence with
Machine feature, its essence is a kind of researchs of algorithm.Therefore, many random sequences generate algorithm complexity height, are unfavorable for hardware
It realizes.
In contrast, much less is then wanted in the research based on hard-wired random sequence generator.In all multi-methods, line
Property feedback shift register (Linear Feedback Shift Register, LFSR) have that structure is simple, is easy to hardware reality
The advantages such as now, therefore require to have in the environment compared with high operation speed again simultaneously to be widely applied some areas are limited.Cause
This, involved hardware random sequence generation circuit of the invention is also based on LFSR realization.
Application No. is CN102186025, entitled compressed sensing based cmos imaging measured value obtains system and its side
A kind of cmos image sensor typically based on LFSR random sequence generator is described in the patent of method, the course of work is such as
Shown in Fig. 1.Assuming that the array size of cmos image sensor is N × N.So corresponding random sequence generates process are as follows: first
Step generates the random sequence of M × N with LFSR, and required clock periodicity is also M × N, and M is observation frequency；Second step is obtaining
Each time during observed result, N number of random sequence is distributed into row and selects the corresponding shift register of circuit, and every progress one
Secondary measurement, row shift unit register require to obtain new N sequence from LFSR, need to repeat M operation altogether.
Random sequence generation circuit structure proposed in patent CN102186025 can actually be used for compressed sensing at
Picture, but still have improved space.First, M × N number of register is needed to store random sequence, and occupancy resource is larger, is unfavorable for
The considerations of in chip design to area；Second, only row embodies randomness in entire array, and column do not have randomness, thus
On compressed sensing imaging embodiment is expert at.
In view of some problems existing for hardware random sequence, the invention proposes one kind being imaged for compressed sensing newly
Two-dimensional random Sequence Generation circuit, to improve to corresponding problem.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide one kind schemes for compressed sensing CMOS
As the two-dimensional random Sequence Generation circuit and its working method of sensor, for solve in compressed sensing cmos image sensor with
Machine sequence is led to the problem of, and realizes one kind using the method that linear feedback shift register and common shift register combine
Sequence is adjustable, mode is optional, (two dimension), complexity are low convenient for hard-wired random number generation circuit at random for ranks.
In order to achieve the above objects and other related objects, the present invention provides a kind of for compressed sensing cmos image sensor
Two-dimensional random Sequence Generation circuit, the two-dimensional random Sequence Generation circuit includes: row linear feedback shift register, is used for
It generates pixel column random number and the method by shifting passes to trigger group；Linear feedback shift register, for generating
Pixel column random number simultaneously passes to trigger group by the method for displacement；Trigger group, based on the pixel column random number received
And/or pixel column random number provides input signal for logic gate；Logic gate realizes that corresponding number is patrolled based on the input signal
Volume, to generate all random numbers for entire pixel array.
One kind as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention is excellent
Scheme is selected, the row linear feedback shift register includes multiple d type flip flops and multiple XOR gates, the variation of the d type flip flop
Period is 2m-1, makes it possible to and takes all over 1 to 2m- 1, wherein the m is D triggering in the row linear feedback shift register
The number of device.
Further, the value of the row linear feedback shift register is discontinuous variation, and is based on the XOR gate
It is taken at random all over 2n- a kind of situation.
One kind as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention is excellent
Scheme is selected, the linear feedback shift register includes multiple d type flip flops and multiple XOR gates, the variation of the d type flip flop
Period is 2n-1, makes it possible to and takes all over 1 to 2n- 1, wherein the n is D triggering in the linear feedback shift register
The number of device.
Preferably, the value of the linear feedback shift register be discontinuous variation, and based on the XOR gate with
Machine takes all over 2n- a kind of situation.
One kind as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention is excellent
Scheme is selected, the logic gate includes one of NOT gate and door or door, NAND gate, nor gate, XOR gate and same or door.
One kind as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention is excellent
Select scheme, the compressed sensing cmos image sensor is divided into multiple blocks of pixels, the trigger group be divided into each
The corresponding igniter module of block of pixels, the igniter module include multiple d type flip flops, and each d type flip flop joins end to end to be formed
One circulating register, when received when clock signal, the value of the latter trigger can be by previous trigger
Replaced value, and the value in first trigger is then replaced the value in the last one trigger.
Preferably, the d type flip flop between each igniter module is mutually not attached to.
Preferably, the pixel array sized of the cmos image sensor is M × N, is divided into K × K block of pixels, often
The size of a block of pixels is m × n, wherein m=M/K, n=N/K, the length of the row linear feedback shift register are m,
It include m d type flip flop；The length of the linear feedback shift register is n, includes n d type flip flop, wherein M, N,
K, m, n are positive integer.
It further, include m d type flip flop and m corresponding to the row linear feedback shift register of each block of pixels
A XOR gate, the linear feedback shift register corresponding to each block of pixels include n d type flip flop and n XOR gate,
The row/column input signal of first igniter module is posted by corresponding row linear feedback shift register/linear feedback shift
Storage is provided by the last one igniter module, and is determined by the selector of an alternative.
The present invention also provides a kind of works of two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor
Make method, comprising steps of
The first step, respectively row linear feedback shift register and linear feedback shift register distribute different drivings
Signal；
Row linear feedback shift register and linear feedback shift register are initialized as complete 1 by second step；
Third step runs the i clock cycle, so that row linear feedback shift register and linear feedback shift register are equal
Generate an initialization random sequence, wherein i >=1；
The selector of alternative is gated row linear feedback shift register and linear feedback shift register by the 4th step
Device；
5th step runs multiple clock cycle, so that row linear feedback shift register and linear feedback shift register
All d type flip flops of device obtain a numerical value, and corresponding all gate circuits also obtain corresponding value, output composition institute
The random sequence to be generated；
6th step judges whether the matrix of random sequence composition is non-singular matrix, then carries out the 7th step if non-singular matrix,
Otherwise it returns to second step and the value of i is added 1 in the third step；
7th step once observes cmos image sensor based on the random code that each pixel of pixel array is assigned,
And after primary observation is completed, sequence generation process will return to third step, and after i clock cycle, all pixels will
It can be assigned to new random code, and then start to observe next time.
Work side as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
A kind of preferred embodiment of method, in the 7th step, it is I0 that total observation frequency, which is arranged, and it is I that random sequence, which generates number, when I is less than I0
When then continue step back to third step, otherwise stop random sequence and generate.
The present invention also provides a kind of works of two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor
Make method, comprising steps of
The first step, respectively row linear feedback shift register and linear feedback shift register distribute different drivings
Signal；
Row linear feedback shift register and linear feedback shift register are initialized as complete 1 by second step；
Third step runs the i clock cycle, so that row linear feedback shift register and linear feedback shift register are equal
Generate an initialization random sequence, wherein i >=1；
The selector of alternative is gated row linear feedback shift register and linear feedback shift register by the 4th step
Device；
5th step runs multiple clock cycle, so that row linear feedback shift register and linear feedback shift register
All d type flip flops of device obtain a numerical value, and corresponding all gate circuits also obtain corresponding value, output composition institute
The random sequence to be generated；
6th step judges whether the matrix of random sequence composition is non-singular matrix, then carries out the 7th step if non-singular matrix,
Otherwise it returns to second step and the value of i is added 1 in the third step；
The selector of alternative is gated the line trigger and column trigger in the last one igniter module by the 7th step
On, form circulating register structure；
8th step, one clock cycle of every experience, circulating register moves backward one, so that the latter pixel mould
Random sequence used in observed result is stochastic ordering used by previous block of pixels last time observed result to block next time
Column.
Work side as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
A kind of preferred embodiment of method, in the 8th step, it is I0 that total observation frequency, which is arranged, and it is I that random sequence, which generates number, when I is less than I0
Shi Ze repeats the 8th step, otherwise stops random sequence and generates.
As described above, two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention and its
Working method has the advantages that
The invention proposes a kind of two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor and its
Working method, realizing a kind of sequence using the method that linear feedback shift register and common shift register combine can
It adjusts, mode is optional, (two dimension), complexity are low convenient for hard-wired random number generation circuit at random for ranks.Structure of the invention
Simply, it is with a wide range of applications in compressed sensing cmos image sensor design field.
Detailed description of the invention
The measured value that Fig. 1 is shown as compressed sensing based cmos imaging measurement value-acquiring method in the prior art obtains
Process, wherein M is pendulous frequency, and N is array size, the random sequence of M × N size is generated with LFSR first, then each
N number of random value is pressed into when secondary measurement, into line shift register respectively to determine to participate in compressed transform during one-shot measurement
Row, the compression summing circuit of each column can sum to institute's selected line pixel at the same time, i.e., completion linear transform process.Entirely
The generation of random sequence is only row service, is arranged then unrelated with random sequence.Therefore the compressed sensing of this imaging only embodies
Be expert at rather than entire block of pixels.
Fig. 2 is shown as the whole of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
Body electrical block diagram.
Fig. 3 is shown as the row of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
Linear feedback shift register/linear feedback shift register structural schematic diagram.
Fig. 4 is shown as a kind of 3 specific knots of row linear feedback shift register/linear feedback shift register
Structure, Fig. 5 are shown as the corresponding sequence transformation situation of structure shown in Fig. 4.
Fig. 6 is shown as the mould of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
Block structure schematic diagram, the random sequence generation circuit of each module is by m × n d type flip flop (m line trigger and n column triggering
Device, FF) and m × n two input gates composition, the input of each gate circuit provided by d type flip flop.
Fig. 7 is shown as the row of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
Sequence circuit structure, RLFSR are used to generate row random number, each column trigger in figure, the FFs of corresponding one of module, column
Sequence circuit result is consistent with Fig. 7, need to only change m and make n.
Fig. 8 is shown as the one of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
The step flow diagram of kind working method.
Fig. 9 is shown as the another of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
A kind of step flow diagram of working method.
Figure 10 is shown as the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention
The timing diagram of working method.
Component label instructions
RLFSR row linear feedback shift register
The linear feedback shift register of CLFSR
The d type flip flop of FFs trigger group
LG logic gate
The selector of Mux alternative
The first step of S11~S17 embodiment 1~the 7th step
The first step of S21~S28 embodiment 2~the 8th step
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 2~Fig. 8.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in diagram then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
As shown in Fig. 2, the present embodiment provides a kind of two-dimensional random sequence productions for compressed sensing cmos image sensor
Raw circuit, the two-dimensional random Sequence Generation circuit includes: row linear feedback shift register, for generating pixel column random number
And the method by shifting passes to trigger group；Linear feedback shift register, for generating pixel column random number and leading to
The method for crossing displacement passes to trigger group；Trigger group, based on the pixel column random number and/or pixel column random number received
Input signal is provided for logic gate；Logic gate realizes corresponding Digital Logic based on the input signal, for entire pixel battle array
Column generate all random numbers.
As an example, the row linear feedback shift register includes multiple d type flip flops and multiple XOR gates, the D touching
The period of change for sending out device is 2m-1, makes it possible to and takes all over 1 to 2m- 1, wherein the m is positive integer.Further, the row
The value of linear feedback shift register is discontinuous variation, and is taken at random based on the XOR gate all over 2m- a kind of situation.
As an example, the linear feedback shift register includes multiple d type flip flops and multiple XOR gates, the D touching
The period of change for sending out device is 2n-1, makes it possible to and takes all over 1 to 2n- 1, wherein the n is positive integer.Preferably, the alignment
Property feedback shift register value be discontinuous variation, and taken at random based on the XOR gate all over 2n- a kind of situation.
As an example, the logic gate includes in NOT gate and door or door, NAND gate, nor gate, XOR gate and same or door
One kind.
As an example, the compressed sensing cmos image sensor is divided into multiple blocks of pixels, the trigger group quilt
It is divided into igniter module corresponding with each block of pixels, the igniter module includes multiple d type flip flops, and each d type flip flop is first
Tail is connected to form a circulating register, and when received when clock signal, the value of the latter trigger can be previous
Replaced value in trigger, and the value in first trigger is then replaced the value in the last one trigger.
Preferably, the d type flip flop between each igniter module is mutually not attached to.Specifically, the pixel array of the cmos image sensor
Size is M × N, is divided into K × K block of pixels, and the size of each block of pixels is m × n, wherein m=M/K, n=N/K,
The length of the row linear feedback shift register is m, includes m d type flip flop；The linear feedback shift register
Length is n, includes n d type flip flop, wherein M, N, K, m, n are positive integer.Line corresponding to each block of pixels is anti-
Presenting shift register includes m d type flip flop and m XOR gate, and the linear feedback shift corresponding to each block of pixels is posted
Storage includes n d type flip flop and n XOR gate, and the row/column input signal of first igniter module is by corresponding line
Feedback shift register/linear feedback shift register is provided by the last one igniter module, and by an alternative
Selector determine.
As shown in Figure 2 to 7, specifically, cmos image sensor (CIS) main pixel array, reading circuit and timing
The modules such as control composition.Conventional CMOS image sensor can sequential read out the value of each pixel after exposition.And it compresses
Perceptual image sensor is then that random write is rounded value of the certain pixels in arranging after linear transformation, wherein most typical change
It changes and exactly sums to the pixel chosen at random.Therefore, the task of random sequence generation circuit is which pixel needs determined
Linear transformation is carried out in one-shot measurement.
As shown in Fig. 2, the present embodiment proposes that a kind of two-dimensional random sequence for compressed sensing cmos image sensor produces
Raw circuit, overall structure are as shown in Figure 2.The random sequence generation circuit mainly by row linear feedback shift register RLFSR,
Linear feedback shift register CLFSR, trigger group (Flip-Flop, FFs) and logic gate (Logic Gate, LG) composition.
The row linear feedback shift register/linear feedback shift register is by a series of d type flip flops and different
Or Men Zucheng, it is as shown in Figure 3 respectively.Wherein d type flip flop Q1, Q2 ... Qn will take all over 1 to 2n- 1, that is to say, that Q1, Q2,
... the period of change of Qn is 2n-1.But the row linear feedback shift register/linear feedback shift register difference
In general accumulator, value is not consecutive variations, but is taken at random all over 2n- a kind of situation.The driving signal g1 of XOR gate,
G2 ... gn just determine Q1, Q2 ... Qn is how to take at random all over these values, and it is anti-that Fig. 4 is shown as a kind of 3 lines
Shift register/linear feedback shift register specific structure is presented, Fig. 5 is shown as the corresponding sequence of structure shown in Fig. 4 and becomes
Change situation.
Trigger group FFs is made of a series of d type flip flops.For each igniter module, d type flip flop is mutual
It is disjunct, and the corresponding d type flip flop of each igniter module be it is end to end, as shown in Figure 7.Particularly, when first
When the input of a trigger is provided by the last one trigger, a circulating register (Circulating will be formed
Shift Register, CSR).Whenever there is a clock to arrive, the value of the latter trigger will be by previous trigger
Value replaced, the value in first trigger is then replaced the value in the last one trigger.
LG is the basic unit in digital circuit, mainly includes NOT gate and door or door, NAND gate, nor gate, XOR gate
With with or door etc..By these gate circuits, corresponding Digital Logic may be implemented.
The entirety for the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor that the present embodiment proposes
Structure is as shown in Figure 2.First, it is assumed that the pixel array sized of cmos image sensor is M × N, array is then divided into K × K
A block of pixels (Block), the size of each block of pixels are m × n, then m=M/K, n=N/K.At the same time, the line
Property feedback shift register/linear feedback shift register be used to generate required random sequence, row linear feedback shift register
The length of device is m, that is, has m d type flip flop；The length of linear feedback shift register is n, that is, has n d type flip flop.
On the other hand, the random sequence generation circuit of each module is by m × n d type flip flop (m line trigger and n column
Trigger) and m × n two input gates composition, the input of each gate circuit provided by d type flip flop, as shown in Figure 6.In addition, all
The corresponding row, column trigger of module is respectively connected together, as shown in Figure 7.Also, the trigger of first igniter module is defeated
Enter by row linear feedback shift register/linear feedback shift register or provided by the last one input module, this by
The selector decision of one alternative, as shown in Figure 7.When the trigger input of first igniter module is by the last one triggering
When the trigger of device module provides, structure shown in Fig. 7 actually just constitutes a circulating register.It can be seen that
The number of CSR is that (m+n) is a, and length is K × K.Fig. 7 is that row sequence generates structure chart, and column sequence is consistent therewith, and only number is omited
(behavior m, is classified as n) micro- difference.
Each parameter of one specific two-dimensional random Sequence Generation circuit is exemplified below shown in table.
As shown in figure 8, the present embodiment also provides a kind of two-dimensional random sequence for compressed sensing cmos image sensor
The working method of generation circuit, comprising steps of
First step S11, respectively row linear feedback shift register and linear feedback shift register distribute different
Driving signal g1、g2、...gn；
Row linear feedback shift register and linear feedback shift register are initialized as complete 1 by second step S12；
Third step S13 runs the i clock cycle, so that row linear feedback shift register and linear feedback shift register
Device generates an initialization random sequence, wherein i >=1；
The selector of alternative is gated row linear feedback shift register and linear feedback shift is posted by the 4th step S14
The trigger of storage, i.e., first igniter module is inputted by row linear feedback shift register and linear feedback shift register
Device provides；
5th step S15 runs multiple clock cycle, so that row linear feedback shift register and linear feedback shift are posted
All d type flip flops of storage obtain a numerical value, and corresponding all gate circuits also obtain corresponding value, output composition
The random sequence to be generated；Specifically, K × K clock cycle is run, d type flip flops all in this way will obtain a number
Value.All gate circuits can also obtain corresponding value, and output just constitutes the random sequence to be generated, i.e. K × K length
For the random sequence of m × n.
6th step S16 judges whether the matrix of random sequence composition is non-singular matrix, then carries out the 7th if non-singular matrix
Otherwise step returns to second step and the value of i is added 1 in the third step；Specifically, judge above-mentioned K × K random sequence composition
Matrix whether be non-singular matrix, then carry out the 7th step if non-singular matrix, otherwise return to second step S12 and in third step S13
It is middle that the value of i is added one, guarantee that the matrix full rank of random sequence composition is to avoid the occurrence of two to remove redundancy condition here
Identical random sequence.
7th step S17, on the whole apparently, in pixel array, all pixels have all had been assigned to a random code.
Based on the random code that each pixel of pixel array is assigned, cmos image sensor is once observed, and is once observing
At later, sequence generation process will return to third step S13, and after i clock cycle, all pixels will be assigned to newly
Random code, and then start observe next time.
Wherein, in the 7th step S17, it is I0 that total observation frequency, which can be set, and it is I that random sequence, which generates number, when I is less than
Then continue step when I0 back to third step S13, otherwise stops random sequence and generate.
The working method of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the present embodiment
System sequence it is as shown in Figure 10, wherein the present embodiment corresponds to the shared timing of Mux signal-off sequence.
As shown in figure 9, in order to further decrease, circuit is realized and the complexity of control, the present embodiment also provide another use
In the working method of the two-dimensional random Sequence Generation circuit of compressed sensing cmos image sensor, comprising steps of
First step S21, respectively row linear feedback shift register and linear feedback shift register distribute different
Driving signal g1、g2、...gn；
Row linear feedback shift register and linear feedback shift register are initialized as complete 1 by second step S22；
Third step S23 runs the i clock cycle, so that row linear feedback shift register and linear feedback shift register
Device generates an initialization random sequence, wherein i >=1；
The selector of alternative is gated row linear feedback shift register and linear feedback shift is posted by the 4th step S24
The trigger of storage, i.e., first igniter module is inputted by row linear feedback shift register and linear feedback shift register
Device provides；
5th step S25 runs multiple clock cycle, so that row linear feedback shift register and linear feedback shift are posted
All d type flip flops of storage obtain a numerical value, and corresponding all gate circuits also obtain corresponding value, output composition
The random sequence to be generated；Specifically, K × K clock cycle is run, d type flip flops all in this way will obtain a number
Value.All gate circuits can also obtain corresponding value, and output just constitutes the random sequence to be generated, i.e. K × K length
For the random sequence of m × n.
6th step S26 judges whether the matrix of random sequence composition is non-singular matrix, then carries out the 7th if non-singular matrix
Otherwise step returns to second step and the value of i is added 1 in the third step；Specifically, judge above-mentioned K × K random sequence composition
Matrix whether be non-singular matrix, then carry out the 7th step if non-singular matrix, otherwise return to second step S22 and in third step S23
It is middle that the value of i is added one, guarantee that the matrix full rank of random sequence composition is to avoid the occurrence of two to remove redundancy condition here
Identical random sequence.
7th step S27, line trigger and column by the selector gating of alternative in the last one igniter module trigger
On device, circulating register structure is formed；
8th step S28, one clock cycle of every experience, circulating register moves backward one, so that the latter picture
Plain module next time random sequence used in observed result be used by previous block of pixels last time observed result with
Machine sequence.
Wherein, in the 8th step S28, it is I0 that total observation frequency, which is arranged, and it is I that random sequence, which generates number, when I is less than I0
Then repeat the 8th step, otherwise stops random sequence and generate.
The working method of the two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the present embodiment
System sequence it is as shown in Figure 10, wherein the present embodiment corresponds to Mux signal and opens the shared timing of sequence.
As described above, two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor of the invention and its
Working method has the advantages that
The invention proposes a kind of two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor and its
Working method, realizing a kind of sequence using the method that linear feedback shift register and common shift register combine can
It adjusts, mode is optional, (two dimension), complexity are low convenient for hard-wired random number generation circuit at random for ranks.Structure of the invention
Simply, it is with a wide range of applications in compressed sensing cmos image sensor design field.
So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (12)
1. a kind of two-dimensional random Sequence Generation circuit for compressed sensing cmos image sensor, which is characterized in that described two
Tieing up random sequence generation circuit includes:
Row linear feedback shift register, for generating pixel column random number and passing to trigger group by the method for displacement；
Linear feedback shift register, for generating pixel column random number and passing to trigger group by the method for displacement；
Trigger group provides input signal based on the pixel column random number and/or pixel column random number received for logic gate；
Logic gate realizes corresponding Digital Logic based on the input signal, all random to generate for entire pixel array
Number；
The row linear feedback shift register includes multiple d type flip flops and multiple XOR gates, the period of change of the d type flip flop
For 2m-1, makes it possible to and take all over 1 to 2m- 1, wherein the m is d type flip flop in the row linear feedback shift register
Number；
The linear feedback shift register includes multiple d type flip flops and multiple XOR gates, the period of change of the d type flip flop
For 2n-1, makes it possible to and take all over 1 to 2n- 1, wherein the n is d type flip flop in the linear feedback shift register
Number.
2. the two-dimensional random Sequence Generation circuit according to claim 1 for compressed sensing cmos image sensor,
Be characterized in that: the value of the row linear feedback shift register is discontinuous variation, and is taken at random time based on the XOR gate
2n- a kind of situation.
3. the two-dimensional random Sequence Generation circuit according to claim 1 for compressed sensing cmos image sensor,
Be characterized in that: the value of the linear feedback shift register is discontinuous variation, and is taken at random time based on the XOR gate
2n- a kind of situation.
4. the two-dimensional random Sequence Generation circuit according to claim 1 for compressed sensing cmos image sensor,
Be characterized in that: the logic gate includes one of NOT gate and door or door, NAND gate, nor gate, XOR gate and same or door.
5. the two-dimensional random Sequence Generation circuit according to claim 1 for compressed sensing cmos image sensor,
Be characterized in that: the compressed sensing cmos image sensor is divided into multiple blocks of pixels, the trigger group be divided into often
The corresponding igniter module of a block of pixels, the igniter module include multiple d type flip flops, and each d type flip flop joins end to end shape
At a circulating register, when received when clock signal, the value of the latter trigger can be by previous trigger
Value replaced, and the value in first trigger is then replaced the value in the last one trigger.
6. the two-dimensional random Sequence Generation circuit according to claim 5 for compressed sensing cmos image sensor,
Be characterized in that: the d type flip flop between each igniter module is mutually not attached to.
7. the two-dimensional random Sequence Generation circuit according to claim 5 for compressed sensing cmos image sensor,
Be characterized in that: the pixel array sized of the cmos image sensor is M × N, is divided into K × K block of pixels, each pixel
The size of module is m × n, wherein the length of m=M/K, n=N/K, the row linear feedback shift register are m, include m
A d type flip flop；The length of the linear feedback shift register is n, includes n d type flip flop, wherein M, N, K, m, n are
Positive integer.
8. the two-dimensional random Sequence Generation circuit according to claim 7 for compressed sensing cmos image sensor,
Be characterized in that: the row linear feedback shift register corresponding to each block of pixels includes m d type flip flop and m XOR gate,
Linear feedback shift register corresponding to each block of pixels includes n d type flip flop and n XOR gate, first touching
Send out device module row/column input signal by corresponding row linear feedback shift register/linear feedback shift register or by
The last one igniter module provides, and is determined by the selector of an alternative.
9. a kind of two-dimensional random sequence for compressed sensing cmos image sensor as described in claim 1~8 any one
The working method of column generation circuit, which is characterized in that comprising steps of
The first step, respectively row linear feedback shift register and linear feedback shift register distribute different driving letters
Number；
Row linear feedback shift register and linear feedback shift register are initialized as complete 1 by second step；
Third step runs the i clock cycle, so that row linear feedback shift register and linear feedback shift register generate
One initialization random sequence, wherein i >=1；
The selector of alternative is gated row linear feedback shift register and linear feedback shift register by the 4th step；
5th step runs multiple clock cycle, so that row linear feedback shift register and linear feedback shift register
All d type flip flops obtain a numerical value, and corresponding all gate circuits also obtain corresponding value, and output composition to be produced
Raw random sequence；
6th step judges whether the matrix of random sequence composition is non-singular matrix, then carries out the 7th step if non-singular matrix, otherwise
It returns to second step and the value of i is added 1 in the third step；
7th step once observes cmos image sensor based on the random code that each pixel of pixel array is assigned, and
After primary observation is completed, sequence generation process will return to third step, and after i clock cycle, all pixels will be by
It is assigned to new random code, and then starts to observe next time.
10. the two-dimensional random Sequence Generation circuit according to claim 9 for compressed sensing cmos image sensor
Working method, it is characterised in that: in the 7th step, it is I0 that total observation frequency, which is arranged, and it is I that random sequence, which generates number, when I is less than
Then continue step when I0 back to third step, otherwise stops random sequence and generate.
11. a kind of two-dimensional random sequence for compressed sensing cmos image sensor as described in claim 1~8 any one
The working method of column generation circuit, which is characterized in that comprising steps of
The first step, respectively row linear feedback shift register and linear feedback shift register distribute different driving letters
Number；
Row linear feedback shift register and linear feedback shift register are initialized as complete 1 by second step；
Third step runs the i clock cycle, so that row linear feedback shift register and linear feedback shift register generate
One initialization random sequence, wherein i >=1；
The selector of alternative is gated row linear feedback shift register and linear feedback shift register by the 4th step；
5th step runs multiple clock cycle, so that row linear feedback shift register and linear feedback shift register
All d type flip flops obtain a numerical value, and corresponding all gate circuits also obtain corresponding value, and output composition to be produced
Raw random sequence；
6th step judges whether the matrix of random sequence composition is non-singular matrix, then carries out the 7th step if non-singular matrix, otherwise
It returns to second step and the value of i is added 1 in the third step；
The selector of alternative is gated the shape on the line trigger and column trigger of the last one igniter module by the 7th step
At circulating register structure；
8th step, one clock cycle of every experience, circulating register moves backward one, so that under the latter block of pixels
Random sequence used in observed result is random sequence used by previous block of pixels last time observed result.
12. the two-dimensional random Sequence Generation circuit according to claim 11 for compressed sensing cmos image sensor
Working method, it is characterised in that: in the 8th step, it is I0 that total observation frequency, which is arranged, and it is I that random sequence, which generates number, when I is less than
Then repeat the 8th step when I0, otherwise stops random sequence and generate.
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