CN103311272B - 具有介电隔离沟槽的横向mosfet - Google Patents

具有介电隔离沟槽的横向mosfet Download PDF

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CN103311272B
CN103311272B CN201210202711.8A CN201210202711A CN103311272B CN 103311272 B CN103311272 B CN 103311272B CN 201210202711 A CN201210202711 A CN 201210202711A CN 103311272 B CN103311272 B CN 103311272B
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drift region
substrate
semiconductor device
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CN103311272A (zh
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陈柏羽
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开的一种横向沟槽MOSFET包括在绝缘体上硅衬底上方形成的介电隔离沟槽。横向沟槽MOSFET还包括在漏极/源极区和绝缘体之间形成的第一漂移区，以及在介电隔离沟槽与绝缘体之间形成的第二漂移区。介电沟槽和绝缘体有助于完全耗尽漂移区。被耗尽的区域可提高横向沟槽MOSFET的击穿电压和导通电阻。本发明还公开了具有介电隔离沟槽的横向MOSFET。

Description

具有介电隔离沟槽的横向MOSFET
技术领域
本发明涉及半导体技术领域，更具体地，涉及具有介电隔离沟槽的横向MOSFET。
背景技术
半导体工业由于各种电子元件(即：晶体管、二极管、电阻器、电容器等)的集成密度提高而得到了快迅发展。集成密度的提高在很大程度上得益于半导体工艺节点的尺寸缩减(例如，工艺节点朝亚20nm节点缩减)。由于半导体器件按比例缩小，因此需要新的技术来保持电子元件在更新换代后的性能。例如，大功率应用需要晶体管具有低的栅极与漏极之间的电容、低的导通电阻以及高击穿电压。
随着半导体技术的发展，金属氧化物半导体场效晶体管(MOSFET)在现今的集成电路中得到了广泛的应用。MOSFET是压控器件。当控制电压施加于MOSFET的栅极并且该控制电压大于MOSFET的阈值时，会在MOSFET的漏极和源极之间建立导电沟道。结果，MOSFET的漏极和源极之间将有电流通过。另一方面，当控制电压小于MOSFET的阈值时，则MOSFET将相应地截止。
MOSFET可包括两个大类。一类是n沟道MOSFET；另一类是p沟道MOSFET。根据结构的不同，MOSFET可进一步分为三个子类，即平面型MOSFET、横向双扩散型MOS(LDMOS)FET和纵向双扩散型MOSFET。与其他MOSFET相比，LDMOS单位面积内通过的电流更大，这是因为其不对称结构在LDMOS的漏极和源极之间提供了短沟道。
为了进一步提高LDMOS的性能，可在横向MOSFET中加入隔离沟槽，以此增大横向MOSFET的击穿电压。特别地，横向MOSFET的栅极区、沟道区和漂移区沿隔离沟槽的侧壁形成。这种横向沟槽MOSFET结构有助于减小导通电阻以及增大横向MOSFET的击穿电压。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种半导体器件，包括：
具有第一导电性的衬底，所述衬底包括埋在所述衬底中的绝缘层；
形成在所述衬底中的具有第二导电性的体区域；
形成在所述衬底中的隔离区；
形成在所述体区域中的具有所述第一导电性的第一有源区；
形成所述衬底中的具有所述第一导电性的第二有源区，其中所述第一有源区和所述第二有源区形成在所述隔离区的相对侧；
漂移区，包括：形成在所述第二有源区和所述绝缘层之间的具有所述第一导电性和第一掺杂密度的第一漂移区；和形成在所述隔离区和所述绝缘层之间的具有所述第一导电性和第二掺杂密度的第二漂移区；
形成在所述衬底上方的第一介电层；以及
形成在所述第一介电层上方的栅极。
在可选实施例中，所述第一介电层形成在所述栅极与所述第一有源区之间。
在可选实施例中，所述第一导电性为N型；以及所述第二导电性为P型。
在可选实施例中，所述绝缘层包括二氧化硅；以及所述隔离区包括二氧化硅。
在可选实施例中，所述第一有源区为源极；以及所述第二有源区为漏极。
在可选实施例中，所述隔离区与所述绝缘层之间的距离在约0.05um到约0.3um的范围内。
在可选实施例中，所述体区域具有在约1017/cm3到约3×1018/cm3的范围内的掺杂密度。
在可选实施例中，所述第一有源区和所述第二有源区具有在约1019/cm3到约5×1019/cm3范围内的掺杂密度。
在可选实施例中，所述第一漂移区的所述第一掺杂密度在约1017/cm3到5×1017/cm3的范围内；以及所述第二漂移区的所述第二掺杂密度在约1017/cm3到5×1017/cm3的范围内。
根据本发明的另一个方面，还提供了一种器件，包括：
埋在具有第一导电类型的衬底中的绝缘层；
形成在所述绝缘层上方的具有所述第一导电类型的漂移区；
形成所述漂移区上方的隔离区；
形成在所述漂移区上方的具有所述第一导电类型的漏极区；
形成所述衬底中的具有第二导电类型的体区域；
形成在所述体区域中的具有所述第一导电类型的源极区，其中所述源极区和所述漏极区形成在所述隔离区的相对侧；以及
邻近所述源极区形成的栅极。
在可选实施例中，所述第一导电类型为n型导电性；以及所述第二导电类型为p型导电性。
在可选实施例中，所述第一导电类型为p型导电性；以及所述第二导电类型为n型导电性。
在可选实施例中，所述漂移区包括：形成在所述漏极区与所述绝缘层之间的第一漂移区；以及形成在所述隔离区与所述绝缘层之间的第二漂移区。
在可选实施例中，所述器件进一步包括：形成在所述栅极与所述源极区之间的第一介电层；以及形成在所述栅极与所述衬底之间的第二介电层。
在可选实施例中，所述衬底是包括二氧化硅绝缘层的绝缘体上硅衬底。
根据本发明的又一个方面，还提供了一种方法，包括：
提供具有第一导电类型的衬底；
在所述衬底中埋入绝缘层；
在所述绝缘层上方形成隔离区；
在所述衬底中的所述绝缘层上方形成具有第二导电类型的体区域；
注入具有所述第一导电类型的离子以形成第一漂移区，其中所述第一漂移区位于所述绝缘层与所述隔离区之间；
注入具有所述第一导电类型的离子以形成第二漂移区；
注入具有所述第一导电类型的离子以形成漏极区，其中所述第二漂移区位于所述漏极区与所述绝缘层之间；
注入具有所述第一导电类型的离子以在所述体区域中形成源极区，其中所述源极区和所述漏极区位于所述隔离区的相对侧；以及
邻近所述源极区形成栅极结构。
在可选实施例中，所述方法进一步包括：形成位于所述栅极与所述源极区之间的第一介电层；以及形成位于所述栅极与所述衬底之间的第二介电层。
在可选实施例中，所述方法进一步包括：在所述衬底中的沟槽中形成所述隔离区，其中所述沟槽的底部与所述绝缘层的顶面之间的距离在0.05um到0.3um的范围内。
在可选实施例中，所述方法进一步包括：在所述衬底中形成二氧化硅绝缘层；以及在所述二氧化硅绝缘层上方形成二氧化硅隔离区。
在可选实施例中，所述方法进一步包括：形成位于所述二氧化硅绝缘层与所述二氧化硅隔离区之间的漂移区，其中所述漂移区的厚度在0.05um到0.3um的范围内。
附图说明
为更完整的理解实施例及其优点，现将结合附图所进行的以下描述作为参考，其中：
图1示出了根据一实施例的横向沟槽MOSFET的简化截面图；
图2出了根据一实施例的介电层应用于衬底后的半导体器件的截面图；
图3示出了根据一实施例的对图2所示的半导体器件实施蚀刻工艺后的截面图；
图4示出了根据一实施例的对于图3所示的半导体器件在沟槽302和沟槽304中形成薄介电层后的的截面图；
图5A示出了根据一实施例的对于图4所示的半导体器件在对沟槽302和沟槽304实施各向异性蚀刻工艺后的截面图；
图5B示出了根据一实施例的对于图5A所示的半导体器件在对沟槽302和沟槽304实施另外的各向异性蚀刻工艺后的截面图；
图6示出了根据一实施例的对于图5B所示的半导体器件在沟槽302和沟槽304的底部分别形成底部介电层后的截面图；
图7示出了根据一实施例的对于图6所示的半导体器件在对沟槽302和沟槽304分别实施各向同性蚀刻工艺后的截面图；
图8示出了根据一实施例的对于图7所示的半导体器件在将介电材料填充到图7所示沟槽中后的截面图；
图9示出了根据一实施例的在对图8所示半导体器件实施各向异性蚀刻工艺后图8所示的半导体器件的截面图；
图10示出了根据一实施例的在图9所示沟槽的侧壁上形成薄氧化物衬层后图9所示的半导体器件的截面图；
图11示出了根据一实施例的对于图10所示的半导体器件将栅电极材料填充到沟槽中后的截面图；
图12示出了根据一实施例的对于图11所示的半导体器件在对图11所示顶面实施化学机械抛光(CMP)工艺或回蚀刻工艺后的截面图；
图13示出了根据一实施例的对于图12所示的半导体器件在对半导体器件的顶面实施各向异性蚀刻工艺后的截面图；
图14示出了根据一实施例的对于图13所示的半导体器件在衬底中形成体区域后的截面图；
图15示出了根据一实施例的对于图14所示的半导体器件在衬底上方形成漏极/源极区后的截面图。
除非另有说明，不同附图中的相应标号和符号通常指相应部件。将附图绘制成清楚地示出各实施例的相关方面而不必须成比例绘制。
具体实施方式
下面详细讨论本发明的制造和使用。然而，应该理解，本发明提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制不同实施方式的范围。
将结合具体环境描述实施方式，即具有介电隔离沟槽的金属氧化层半导体场效晶体管(MOSFET)。然而，本发明的实施例也可以应用于各种不同的金属氧化物半导体晶体管。
图1示出了根据一实施例的横向沟槽MOSFET的简化截面图。横向沟槽MOSFET 100包括具有第一导电性的衬底以及埋在衬底中的绝缘层101。更具体地，衬底可分为两部分。如图1所示，上衬底部分102形成在绝缘层101上方；下衬底部分103形成在绝缘层101下方。根据一实施例，绝缘层101由二氧化硅组成。衬底可以是轻掺杂n型衬底，这种衬底通过注入浓度在约5×1016/cm3与约9×1016/cm3之间的n型掺杂剂(如磷)形成。图1所示的衬底通常称为绝缘体上硅衬底。
第一漏极/源极区112和第二漏极/源极区114形成在绝缘层101上方的上衬底部分102中。隔离区104和106形成在两个有源区之间。例如，如图1所示，隔离区104形成在第一漏极/源极区112和第二漏极/源极区114之间。根据一实施例，第一漏极/源极区112是横向沟槽MOSFET 100的漏极，第二漏极/源极区114是横向沟槽MOSFET 100的源极。
第一漏极/源极区112形成在上衬底部分102中。根据一实施例，第一漏极/源极区112用作横向沟槽MOSFET 100的漏极。第一漏极/源极区112可由n型掺杂剂构成。漏极区可通过注入浓度在约1×1019/cm3与约5×1019/cm3之间的n型掺杂剂(如磷)形成。
第二漏极/源极区114形成在体区域(body region)122中。根据一实施例，第二漏极/源极区114可以是横向沟槽MOSFET 100的源极。源极区可通过注入浓度在约1×1019/cm3与约5×1019/cm3之间的n型掺杂剂(如磷)形成。如图1所示，源极区形成邻近隔离区104并且位于漏极(第一漏极/源极区112)的对侧。
横向沟槽MOSFET 100进一步包括形成在绝缘层101上方的上衬底部分102中的具有第二导电性的体区域122。如图1所示，体区域122形成在第二漏极/源极区114的下面。根据一实施例，当衬底是n型时，体区域122是p型体区域。体区域122通过注入p型掺杂材料(如硼、镓、铝、铟及其组合等)形成。根据一实施例，可注入掺杂密度为约1017/cm3到3×1018/cm3的p型材料(如硼)。可选地，体区域122可以采用扩散工艺形成。横向沟槽MOSFET 100的体区域122也可称为沟道区。
横向沟槽MOSFET 100可包括栅极142。如图1所示，栅极142被介电层包围。特别地，介电层将栅极142与第二漏极/源极区114分隔开。根据一实施例，栅极142可连接到控制信号。当控制信号大于横向沟槽MOSFET 100的阈值电压时，横向沟槽MOSFET 100导通。另一方面，当控制信号小于阈值电压，则横向沟槽MOSFET 100相应地截止。
横向沟槽MOSFET 100可包括漂移区，其中漂移区包括在第一漏极/源极区112和绝缘区101之间形成的第一漂移区116以及在隔离区104和绝缘层101之间形成的第二漂移区118。根据一实施例，第一漂移区116是掺杂浓度在约1017/cm3到约5×1017/cm3范围内的n型区。第二漂移区118是掺杂浓度在约1016/cm3到约3×1017/cm3范围内的n型区。
隔离区104的深度以及隔离区104与绝缘层101之间的间隙的尺寸如图1所示。特别地，隔离区104的深度定义为H1。隔离区104与绝缘层101之间的间隙定义为H2。根据一实施例，H1约等于1um。H2在约0.05um到约0.3um的范围内。
本领域技术人员会意识到图1示出了理想情况下的剖面图。H1和H2的尺寸经过后续的制造工艺后可能会发生改变。图1所示的H1和H2用于说明各种实施例的发明方面。本发明不限于H1和H2的任何特定尺寸。
隔离区(如隔离区104)用于提高横向沟槽MOSFET 100的击穿电压。特别地，如图1所示，隔离区104的底面邻近绝缘层101。绝缘层101和隔离区104都由介电材料(如二氧化硅)形成。由于两个二氧化硅层之间较近，可能导致第二漂移区118被完全耗尽。这样的被完成耗尽的漂移区有助于在截止期间降低在横向沟槽MOSFET 100表面的电场。类似地，由于第一漂移区116位于两个二氧化硅区104和106之间，因此其也可能被完全耗尽。如此，被完全耗尽的第一漂移区116有助于降低在横向沟槽MOSFET 100表面的电场。
被完全耗尽的漂移区(如第二漂移区118)的影响类似于降低表面电场(reduced surface field，RESURF)的效应。RESURF是众所周知的一种提高高压MOSFET的击穿电压的方法。如此，被完全耗尽的漂移区有助于提高横向沟槽MOSFET 100的击穿电压。而且，由于提高了横向沟槽MOSFET 100的击穿电压，可使用高度掺杂的漂移区以进一步降低横向沟槽MOSFET 100的导通电阻。总之，被完全耗尽的漂移区118有助于提高横向沟槽MOSFET 100的击穿电压和导通电阻。
具有介电隔离沟槽(如隔离区104)的横向沟槽MOSFET的一个有利特点是图1所示的沟槽结构有助于提高横向沟槽MOSFET 100的击穿电压和导通电阻。换言之，沟槽结构有助于保持横向沟槽MOSFET的击穿电压。此外，沟槽结构还可以降低横向沟槽MOSFET 100的导通电阻，以便可减少横向沟槽MOSFET 100的功率损耗。而且，图1的横向沟槽结构有助于减小横向沟槽MOSFET 100的节距。减小的节距有助于减小横向沟槽MOSFET 100的沟道长度和导通电阻。
图2-图15示出了根据一实施例的制造横向沟槽MOSFET的中间步骤的截面图。图2示出了根据一实施例的介电层应用于衬底后的半导体器件的截面图。如图2所示，介电层132形成在绝缘层101上方的上衬底部分102的顶部上。如参考图1所示，衬底可以是n型SOI衬底。
介电层132可由集成电路制造中各种常用的介电材料制成。例如，介电层132可由二氧化硅、氮化硅或掺杂的玻璃层(如硼硅玻璃等)制成。可选地，介电层也可以由氮化硅、氮氧化硅层、聚酰胺层、低介电常数绝缘体等制成。此外，上述介电材料的组合也可以用于形成介电层132。根据一实施例，介电层132可采用合适的技术形成，如溅射、氧化和/或化学气相沉积(CVD)。
图3示出了根据一实施例的对半导体器件实施蚀刻工艺后图2所示的半导体器件的截面图。根据一实施例，使用沉积和光刻技术将诸如光刻胶掩模和/或硬掩膜的图案化掩模(未示出)形成在介电层132上。之后，进行蚀刻工艺以形成沟槽302和304，蚀刻工艺可以是例如反应离子蚀刻(RIE)或其他干蚀刻、各向异性湿蚀刻或任何其他合适的各向异性蚀刻或图案化工艺。
图4示出了根据一实施例的对于图3所示的半导体器件在沟槽302和沟槽304中形成薄介电层后的截面图。薄介电层402和404可以是分别在沟槽302和沟槽304中热生长的氧化物层。可选地，薄介电层402和404也可以采用其他合适的技术来形成，如溅射、氧化和/或CVD。
图5A示出了根据一实施例的对于图4所示的半导体器件在对沟槽302和沟槽304实施各向异性蚀刻工艺后的截面图。对沟槽302和沟槽304实施各向异性蚀刻工艺。通过控制蚀刻工艺的强度和方向，结果去除了薄介电层402和404的底部。
图5B示出了根据一实施例的对于图5所示的半导体器件在对沟槽302和沟槽304实施另外的各向异性蚀刻工艺后的截面图。对沟槽302和沟槽304实施另外的各向异性蚀刻工艺。通过控制另外的蚀刻工艺的强度和方向，如图5B所示，结果去除了沟槽302和沟槽304的介电侧壁的底部部分。
图6示出了根据一实施例的对于图5B所示的半导体器件在沟槽302和沟槽304的底部分别形成底部介电层后的截面图。底部介电层602和604可以是分别在沟槽302和304中热生长的氧化物层。应注意，底介电层602和604可以采用其他合适的技术来形成，如CVD。
图7示出了根据一实施例的对于图6所示的半导体器件在分别对沟槽302和沟槽304实施各向同性蚀刻工艺后的截面图。对沟槽302和沟槽304实施各向异性蚀刻工艺。结果去除了沟槽302和沟槽304侧壁上的薄介电衬层。
图8示出了根据一实施例的对于图7所示的半导体器件用介电材料填充到图7所示沟槽中后的截面图。根据一实施例，可通过首先形成沟槽然后用介电材料填充沟槽来形成隔离区802和804。为了抛光图8所示的半导体器件的表面，可实施诸如CMP或回蚀刻步骤的平坦化工艺以平坦化隔离区802和804的上表面。
沟槽(如图7所示)填充有介电材料，从而形成了如图8所示的隔离区802和804。介电材料可包括例如热氧化、CVD氧化硅等。其也可包括材料的组合，材料例如是氮化硅、氮氧化硅、高K电介质、低K电介质、CVD多晶硅或其他介电材料。
图9示出了根据一实施例的对于图8所示的半导体器件在对图8所示半导体器件实施各向异性蚀刻工艺后的截面图。采用沉积和光刻技术将诸如光刻胶掩模和/或硬掩膜的图案化掩模(未示出)形成在半导体器件的顶面上。实施各向异性蚀刻工艺以形成沟槽902和904。
图10示出了根据一实施例的对于图9所示的半导体器件在薄氧化物衬层形成在图9所示沟槽的侧壁上后的截面图。可在沟槽902和904中热生长薄氧化物层。顶面上的介电层可阻止在半导体器件的顶面的额外氧化。
图11示出了根据一实施例的对于图11所示的半导体器件在栅电极材料填充到沟槽中后的截面图。栅电极层1102可由多晶硅制成。栅电极层1102也可由其他常用导电材料形成，例如金属(如钽、钛、钼、钨、铂、铝、铪、钌)；金属硅化物(如硅化钛、硅化钴、硅化镍、硅化钽)；金属氮化物(如氮化钛、氮化钽)；掺杂的多晶硅；其他导电材料；它们的组合或类似材料。
图12示出了根据一实施例的对于图11所示的半导体器件在对图11所示的顶面实施化学机械抛光(CMP)工艺或回蚀刻工艺后的截面图。可进行平坦化工艺(如CMP或回蚀刻步骤)以平坦化栅电极层1102的上表面。如图12所示，结果去除了栅电极层1102的一部分。如图12所示，CMP工艺过后，可能存在两个栅极，即第一栅极1202和第二栅极1204。
图13示出了根据一实施例的对于图12所示的半导体器件在对半导体器件的顶面实施各向异性蚀刻工艺后的截面图。根据一实施例，对顶面实施各向异性蚀刻工艺。结果，去除了介电层132(图2中未示出但有说明)。
图14示出了根据一实施例的对于图13所示的半导体器件在衬底中形成体区域后的截面图。体区域122和124可形成在上衬底部分102中。根据一实施例，当上衬底部分102是轻掺杂的n型衬底时，可通过注入合适的p型掺杂剂(如硼、镓、铟等)来形成体区域122和124。可选地，在衬底103是n型衬底的实施例中，可通过注入合适的p型掺杂剂(如磷、砷等)来形成体区域122和124。根据一实施例，体区域122和124的掺杂密度在约1017/cm3到约3×1018/cm3的范围内。
图15示出了根据一实施例的对于图14所示的半导体器件在衬底上方形成漏极/源极区后的截面图。漏极/源极区112和114可形成在隔离区(如隔离区802)的相对侧。根据一实施例，漏极/源极区(如漏极/源极区112)可通过注入合适的n型掺杂剂(如磷、砷等)来形成。根据一实施例，漏极/源极区(如漏极/源极区112)的掺杂密度在约1019/cm3到约5×1019/cm3的范围内。
尽管已经详细地描述了本发明及其优势，但应该理解，可以在不背离所附权利要求限定的本发明主旨和范围的情况下，做各种不同的改变，替换和更改。
而且，本申请的范围并不仅限于本说明书中描述的工艺、机器、制造、材料组分、装置、方法和步骤的特定实施例。作为本领域普通技术人员应理解，通过本发明，现有的或今后开发的用于执行与根据本发明采用的相应实施例基本相同的功能或获得基本相同结果的工艺、机器、制造，材料组分、装置、方法或步骤根据本发明可以被使用。因此，将这样的工艺、机器、制造、材料组分、装置、方法或步骤应该包括在所附权利要求的范围内。

Claims (16)

1.一种半导体器件，包括：
具有第一导电性的衬底，所述衬底包括埋在所述衬底中的绝缘层；
形成在所述衬底中的具有第二导电性的体区域；
形成在所述衬底中的隔离区；
形成在所述体区域中的具有所述第一导电性的第一有源区；
形成所述衬底中的具有所述第一导电性的第二有源区，其中所述第一有源区和所述第二有源区形成在所述隔离区的相对侧；
漂移区，包括：
形成在所述第二有源区和所述绝缘层之间的具有所述第一导电性和第一掺杂密度的第一漂移区，所述第一漂移区延伸穿过所述隔离区；和
形成在所述隔离区和所述绝缘层之间的具有所述第一导电性和第二掺杂密度的第二漂移区；
形成在所述衬底上方的第一介电层；以及
形成在所述第一介电层上方的栅极，其中，所述第一有源区形成在所述栅极和所述隔离区之间，并且所述第一有源区与所述隔离区的侧壁直接接触；
其中，所述第一介电层形成在所述栅极与所述第一有源区之间。
2.根据权利要求1所述的半导体器件，其中：
所述第一导电性为N型；以及
所述第二导电性为P型。
3.根据权利要求1所述的半导体器件，其中：
所述绝缘层包括二氧化硅；以及
所述隔离区包括二氧化硅。
4.根据权利要求1所述的半导体器件，其中：
所述第一有源区为源极；以及
所述第二有源区为漏极。
5.根据权利要求1所述的半导体器件，其中，所述隔离区与所述绝缘层之间的距离在0.05um到0.3um的范围内。
6.根据权利要求1所述的半导体器件，其中，所述体区域具有在1017/cm3到3×1018/cm3的范围内的掺杂密度。
7.根据权利要求1所述的半导体器件，其中：
所述第一有源区和所述第二有源区具有在1019/cm3到5×1019/cm3范围内的掺杂密度。
8.根据权利要求1所述的半导体器件，其中：
所述第一漂移区的所述第一掺杂密度在1017/cm3到5×1017/cm3的范围内；以及
所述第二漂移区的所述第二掺杂密度在1017/cm3到5×1017/cm3的范围内。
9.一种半导体器件，包括：
埋在具有第一导电类型的衬底中的绝缘层；
形成在所述绝缘层上方的漂移区；
形成在所述漂移区上方的隔离区；
形成在所述漂移区上方的具有所述第一导电类型的漏极区；
形成在所述衬底中的具有第二导电类型的体区域；
形成在所述体区域中的具有所述第一导电类型的源极区，其中所述源极区和所述漏极区形成在所述隔离区的相对侧；
邻近所述源极区形成的栅极，
形成在所述栅极与所述源极区之间的第一介电层；以及
形成在所述栅极与所述衬底之间的第二介电层；
其中，所述源极区形成在所述栅极和所述隔离区之间，并且所述源极区与所述隔离区的侧壁直接接触，
其中，所述漂移区包括第一漂移区和第二漂移区，所述第一漂移区形成在所述漏极区和所述绝缘层之间并且具有第一导电类型和第一掺杂密度；所述第二漂移区形成在所述隔离区和所述绝缘层之间并且具有所述第一导电类型和第二掺杂密度，并且
所述第一漂移区延伸穿过所述隔离区。
10.根据权利要求9所述的半导体器件，其中：
所述第一导电类型为n型导电性；以及
所述第二导电类型为p型导电性。
11.根据权利要求9所述的半导体器件，其中：
所述第一导电类型为p型导电性；以及
所述第二导电类型为n型导电性。
12.根据权利要求9所述的半导体器件，其中，所述衬底是包括二氧化硅绝缘层的绝缘体上硅衬底。
13.一种制造半导体器件的方法，包括：
提供具有第一导电类型的衬底；
在所述衬底中埋入绝缘层；
在所述绝缘层上方形成隔离区；
在所述衬底中的所述绝缘层上方形成具有第二导电类型的体区域；
注入具有所述第一导电类型的离子以形成第一漂移区，其中所述第一漂移区位于所述绝缘层与所述隔离区之间；
注入具有所述第一导电类型的离子以形成第二漂移区；
注入具有所述第一导电类型的离子以形成漏极区，其中所述第二漂移区位于所述漏极区与所述绝缘层之间，所述第二漂移区延伸穿过所述隔离区；
注入具有所述第一导电类型的离子以在所述体区域中形成源极区，其中所述源极区和所述漏极区位于所述隔离区的相对侧；
邻近所述源极区形成栅极结构，其中，所述源极区形成在所述栅极结构和所述隔离区之间，并且所述源极区与所述隔离区的侧壁直接接触；
形成位于所述栅极结构与所述源极区之间的第一介电层；以及
形成位于所述栅极结构与所述衬底之间的第二介电层。
14.根据权利要求13所述的方法，进一步包括：
在所述衬底中的沟槽中形成所述隔离区，其中所述沟槽的底部与所述绝缘层的顶面之间的距离在0.05um到0.3um的范围内。
15.根据权利要求13所述的方法，进一步包括：
在所述衬底中形成二氧化硅绝缘层；以及
在所述二氧化硅绝缘层上方形成二氧化硅隔离区。
16.根据权利要求15所述的方法，进一步包括：
形成位于所述二氧化硅绝缘层与所述二氧化硅隔离区之间的漂移区，其中所述漂移区的厚度在0.05um到0.3um的范围内。
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