CN103311223A - Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product - Google Patents
Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product Download PDFInfo
- Publication number
- CN103311223A CN103311223A CN2013102348113A CN201310234811A CN103311223A CN 103311223 A CN103311223 A CN 103311223A CN 2013102348113 A CN2013102348113 A CN 2013102348113A CN 201310234811 A CN201310234811 A CN 201310234811A CN 103311223 A CN103311223 A CN 103311223A
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer
- nickel
- electrogilding
- electronickelling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Electroplating Methods And Accessories (AREA)
Abstract
The invention discloses a nickel and gold electroplating product of a wafer. The nickel and gold electroplating product is applicable to RDL (redistribution layer) and TSV (through silicon via) processes, and comprises a substrate. A conductive region and a non-conductive region are arranged on the surface of the substrate, and a seed layer, a copper electroplating layer, a nickel electroplating layer and a gold electroplating layer are sequentially arranged on the surface of the conductive region of the substrate. The nickel and gold electroplating product has the advantages that strict requirements on the line widths and the line spacing are omitted in a process for manufacturing the nickel and gold electroplating product; the requirement on the quality of the product can be met completely by means of controlling parameters such as current density and time even if the line widths and the line spacing are 1 micrometer; nickel smear and nickel corrosion conditions of traditional nickel and gold chemical plating are prevented owing to nickel and gold electroplating, and the reliability of the product can be further improved.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of wafer electronickelling gold product and preparation method thereof.
Background technology
Wafer (Wafer) refers to the silicon wafer that the Si semiconductor production of integrated circuits is used, because it is shaped as circle, therefore be called wafer; On silicon wafer, can manufacture various circuit component structures, and become the IC of certain electric sexual function product be arranged.The IC product is the substantially former device that advanced information society be unable to do without, and is widely used in the various aspects of our life.
Along with the function of chip is increasing with highly integrated demand, present semiconductor packages industry forward wafer-level packaging future development.It is a kind of method of raising silicon chip integrated level commonly used, has the test of reduction and packaging cost, reduces lead-in inductance, improves capacitance characteristic, and the improved heat radiation passage reduces advantages such as mounting height.
Along with the chip design benefit becomes complicated, the encapsulation procedure difficulty of arranging in pairs or groups also improves synchronously; Traditional 2D technology can not satisfy high integrated, lightness, the demand of low-power consumption.Therefore Foundry and envelope survey dealer allow wafer under the prerequisite that does not affect footprint, stacking and Collaboration smoothly makes progress, thereby allow chip the I/O possibility is provided, provide widely, dwindled package dimension at arise at the historic moment RC that the .3D integrated technology reduced chip of the upper integrated concept of three-dimensional (3D), thereby improved the overall performance of chip.
In the 3D of wafer encapsulation, RDL(connects up again) and TSV(silicon through hole) technology is very important two links, because development and the raising of integrated level, the chip stack constantly increases, and the density of circuit is also increasing, and the live width line-spacing is more and more less.Traditional technique uses chemical nickel plating gold processing procedure to finish the part processing procedure of RDL processing procedure or TSV, but along with the live width line-spacing constantly dwindles, the quality problem of the short circuit (short) that the easy plating of chemical nickel plating gold causes highlights, the chemical nickel plating gold is fit to the above live width line-spacing of 25 μ m at present, along with constantly dwindling of live width line-spacing, easily cause circuit to put up a bridge, short circuit occurs, product yield is greatly affected.In addition, itself there is the nickel corrosion condition in the chemical nickel plating gold, easily produces black nickel or black pad, has affected greatly welding performance, and the property of fine qualities of product is not good.
The electronickelling gold is used more at other field, print such as PCB() field, but the PCB field is not high to the uniformity requirement of whole plate face thickness of coating, and aspect wafer electronickelling gold product coating, the poor requirement of thickness of coating is that the traditional electrical plating nickel golds such as PCB can't reach technical indicator less than 5% on the whole wafer.Because (perhaps NiPdAu) technical development of chemical nickel plating gold is ripe, need not special equipment requirement, the coating uniformity that obtains is good, so the mode of the technology utilization chemical plating of plating nickel gold is carried out on the in the past wafer electronickelling gold product.Yet along with the electronic product integrated level is more and more higher, the live width line-spacing above the wafer is more and more less, and the mode drawback of the easy plating of chemical plating highlights, and the mode of plating has entered again those skilled in the art's the visual field.
Summary of the invention
Based on this, the purpose of this invention is to provide a kind of wafer electronickelling gold product and preparation technology thereof, this technique is applicable to RDL and the TSV processing procedure of wafer scale 3D encapsulation.
Concrete technical scheme is as follows:
A kind of wafer electronickelling gold product, described substrate surface is provided with conduction region and non-conductive district, is provided with successively Seed Layer, copper electroplating layer, electroless nickel layer, electrogilding layer on the substrate surface of described conduction region.
Among embodiment, described Seed Layer is vacuum copper plate or the Vacuum Deposition titanium layer of 0.2-0.5 μ m therein.
Among embodiment, the thickness of described copper electroplating layer is 0.5-30 μ m therein; The thickness of described electroless nickel layer is 0.3-10 μ m; The thickness of described electrogilding layer is 0.01-2 μ m.
Among embodiment, the thickness of described copper electroplating layer is 2-20 μ m therein; The thickness of described electroless nickel layer is 0.5-10 μ m; The thickness of described electrogilding layer is 0.01-0.8 μ m.
Among embodiment, also be provided with welding resistance district and non-welding resistance district on the described electrogilding floor therein, also be provided with soldering-resistance layer on the electrogilding floor in described welding resistance district.
Another object of the present invention provides the preparation method of above-mentioned wafer electronickelling gold product.
Concrete technical scheme is as follows:
The preparation method of above-mentioned wafer electronickelling gold product comprises the steps:
(1) base material forms the Seed Layer of 0.2-0.5 μ m, then in Seed Layer surface coverage one deck photosensitive-ink through Vacuum Deposition at substrate surface;
(2) method of employing exposure imaging is removed the printing ink on conduction region Seed Layer surface;
(3) adopt electric plating method to electroplate one deck copper electroplating layer in the conduction region Seed Layer that step (2) obtains, the technological parameter of electro-coppering is: current density is 0.5-10A/dm
2, temperature is 10-40 ℃;
(4) adopt electric plating method to electroplate one deck electroless nickel layer at the copper electroplating layer that step (3) obtains, the technological parameter of electronickelling is: current density is 0.5-10A/dm
2, temperature is 30-70 ℃;
(5) electroless nickel layer that adopts electric plating method to obtain in step (4) is electroplated one deck electrogilding layer, and the technological parameter of electrogilding is: current density is 0.1-1.0A/dm
2, temperature is 20-70 ℃;
(6) photosensitive-ink in the non-conductive district of removal base material;
(7) adopt etching method to remove the Seed Layer in the non-conductive district of base material, namely get described wafer electronickelling gold product.
Among embodiment, the technological parameter of the electro-coppering in the step (3) is: current density is 1.0-3.0A/dm therein
2, temperature is 20-35 ℃; The technological parameter of electronickelling is in the step (4): current density is 1.0-3.0A/dm
2, temperature is 40-60 ℃; The technological parameter of electrogilding is in the step (5): current density is 0.2-0.5A/dm
2, temperature is 40-60 ℃.
Therein among embodiment, described step (7) afterwards, the welding resistance district that also is included in the electrogilding floor covers the last layer soldering-resistance layer.
Therein among embodiment, described each step also comprises one or more in washing, wetting, preimpregnation or the baking step as required.
Beneficial effect of the present invention:
1, the preparation method of wafer electronickelling gold product of the present invention adopts nickel-gold electroplating process, has overcome the following defective that traditional chemical plating nickel gold technique exists:
(1) the activation palladium in the traditional chemical plating nickel gold technology processing procedure is difficult to clean, or the active problem such as high of nickel and produce the technological deficiency (as shown in Figure 1) of plating, causes independently that two circuits link together again, makes product produce the electric property defective.The chemical nickel plating gold is because the nickel etching problem also can cause soldering reliability to descend in addition.
(2) the minimum feature line-spacing of chemical nickel plating gold can only be accomplished 25 μ m at present, is difficult to adapt to RDL or the TSV processing procedure of live width line-spacing less (being low to moderate 1 μ m).
2, adopt preparation technology of the present invention, the live width line-spacing is not strict with.Even the live width line-spacing at 1 μ m, also can by parameters such as control current density times, can satisfy the quality demand fully.
3, because there is not the nickel corrosion condition of chemical nickel plating gold in the electronickelling gold, can further improve the reliability of product.
Description of drawings
Fig. 1 is the technological deficiency figure that traditional chemical plating nickel gold technology processing procedure produces plating;
Fig. 2 is the wafer electronickelling gold product structure schematic diagram of the embodiment of the invention;
Fig. 3 is wafer electronickelling gold product preparation flow schematic diagram of the present invention;
Fig. 4 is the schematic flow sheet that the traditional chemical plating nickel gold prepares wafer electronickelling gold product.
Description of reference numerals:
101, base material; 102, Seed Layer; 103, copper electroplating layer; 104, electroless nickel layer; 105, electrogilding layer.
Embodiment
Various electroplate liquid used in the present invention all can be buied by commercially available.
The employed equipment of electroplating technology of the present invention is: vertical or cup type wafer electronickelling gold product Special electric coating apparatus.
Below the present invention is further elaborated by specific embodiment.
With reference to figure 2, a kind of wafer electronickelling gold of embodiment of the invention product, comprise base material 101, described substrate surface is provided with conduction region and non-conductive district, is provided with successively Seed Layer 102, copper electroplating layer 103, electroless nickel layer 104, electrogilding layer 105 on the substrate surface of described conduction region.
Described Seed Layer is vacuum copper plate or the Vacuum Deposition titanium layer of 0.3-0.5 μ m.
The thickness of described copper electroplating layer is 5 μ m; The thickness of described electroless nickel layer is 2 μ m; The thickness of described electrogilding layer is 0.1 μ m.
Also be provided with welding resistance district and non-welding resistance district on the described electrogilding floor, also be provided with soldering-resistance layer on the electrogilding floor in described welding resistance district.
With reference to figure 3, the preparation method of above-mentioned wafer electronickelling gold product comprises the steps:
(1) adopt according to a conventional method the mode of Vacuum Deposition in the Seed Layer of substrate surface formation 0.3-0.5 μ m, then in Seed Layer surface coverage one deck photosensitive-ink;
The method of the exposure imaging of (2) employing routine is removed the printing ink (usually using sodium carbonate, potash, NaOH, the mixed aqueous solution of one or more in the potassium hydroxide) on conduction region Seed Layer surface;
(3) adopt electric plating method to electroplate one deck copper electroplating layer in the conduction region Seed Layer that step (2) obtains; The technological parameter of electro-coppering is: at 25 ℃ and 2.0A/dm
2Current density under electroplate 12min, the copper electroplating layer that gets 5 μ m (is 1.0-3.0A/dm in current density
2And temperature is also all can obtain under the 20-35 ℃ of condition);
(4) adopt electric plating method to electroplate one deck electroless nickel layer at the copper electroplating layer that step (3) obtains; The technological parameter of electronickelling is: at 60 ℃ and 2.0A/dm
2Current density under electroplate 5min, the electroless nickel layer that obtains 2 μ m (is 1.0-3.0A/dm in current density
2And temperature is also all can obtain under the 40-60 ℃ of condition);
(5) electroless nickel layer that adopts electric plating method to obtain in step (4) is electroplated one deck electrogilding layer; The technological parameter of electrogilding is: at 50 ℃ and 0.3A/dm
2Current density under electroplate 2min, the electrogilding layer that obtains 0.1 μ m (is 0.2-0.5A/dm in current density
2And temperature is also all can obtain under the 40-60 ℃ of condition);
(6) remove according to a conventional method the photosensitive-ink in the non-conductive district of base material;
(7) routinely engraving method is removed the Seed Layer in the non-conductive district of base material;
(8) cover the last layer soldering-resistance layer in the welding resistance district of electrogilding floor, and get final product.
Above steps also comprises one or more in the complementary steps such as washing, wetting, preimpregnation or oven dry as required.
As a comparison, with reference to figure 4, the step that employing traditional chemical plating nickel gold technique prepares wafer electronickelling gold product is as follows:
(1) base material forms the Seed Layer of 0.3-0.5 μ m, then in Seed Layer surface coverage one deck photosensitive-ink through Vacuum Deposition at substrate surface;
(2) method of employing exposure imaging is removed the printing ink on conduction region Seed Layer surface;
(3) adopt electric plating method to electroplate one deck copper electroplating layer in the conduction region Seed Layer that step (2) obtains;
(4) photosensitive-ink in the non-conductive district of removal base material;
(5) adopt etching method to remove the Seed Layer in the non-conductive district of base material;
(6) adopt the method for conventional chemical plating to cover one deck chemical Ni-plating layer at the copper electroplating layer that step (3) obtains;
The chemical Ni-plating layer that the method for the chemical plating of (7) employing routine obtains in step (6) covers one deck chemical gilding layer;
(8) carry out successive process, as above welding resistance etc.
The preparation method of wafer electronickelling gold product of the present invention adopts nickel-gold electroplating process, has overcome the following defective that traditional chemical plating nickel gold technique exists:
(1) the activation palladium in the traditional chemical plating nickel gold technology processing procedure is difficult to clean, or the active problem such as high of nickel and produce the technological deficiency (as shown in figs. 1 and 4) of plating, causes independently that two circuits link together again, makes product produce the electric property defective.The chemical nickel plating gold is because the nickel etching problem also can cause soldering reliability to descend in addition.
(2) the minimum feature line-spacing of chemical nickel plating gold can only be accomplished 25 μ m at present, is difficult to adapt to RDL or the TSV processing procedure of live width line-spacing less (being low to moderate 1 μ m).
Adopt preparation technology of the present invention, the live width line-spacing is not strict with.Even the live width line-spacing at 1 μ m, also can by parameters such as control current density times, can satisfy the quality demand fully.
Because there is not the nickel corrosion condition of chemical nickel plating gold in the electronickelling gold, can further improve the reliability of product.
The above embodiment has only expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (9)
1. a wafer electronickelling gold product comprises base material, it is characterized in that, described substrate surface is provided with conduction region and non-conductive district, is provided with successively Seed Layer, copper electroplating layer, electroless nickel layer, electrogilding layer on the substrate surface of described conduction region.
2. wafer electronickelling gold product according to claim 1 is characterized in that, described Seed Layer is vacuum copper plate or the Vacuum Deposition titanium layer of 0.3-0.5 μ m.
3. wafer electronickelling gold product according to claim 1 is characterized in that, the thickness of described copper electroplating layer is 0.5-30 μ m; The thickness of described electroless nickel layer is 0.2-10 μ m; The thickness of described electrogilding layer is 0.001-2 μ m.
4. wafer electronickelling gold product according to claim 3 is characterized in that, the thickness of described copper electroplating layer is 2-20 μ m; The thickness of described electroless nickel layer is 0.5-10 μ m; The thickness of described electrogilding layer is 0.1-0.8 μ m.
5. each described wafer electronickelling gold product is characterized in that according to claim 1-4, also is provided with welding resistance district and non-welding resistance district on the described electrogilding floor, also is provided with soldering-resistance layer on the electrogilding floor in described welding resistance district.
6. the preparation method of each described wafer electronickelling gold product of claim 1-5 is characterized in that, comprises the steps:
(1) base material forms the Seed Layer of 0.2-0.5 μ m, then in Seed Layer surface coverage one deck photosensitive-ink through Vacuum Deposition at substrate surface;
(2) method of employing exposure imaging is removed the printing ink on conduction region Seed Layer surface;
(3) adopt electric plating method to electroplate one deck copper electroplating layer in the conduction region Seed Layer that step (2) obtains, the technological parameter of electro-coppering is: current density is 0.5-10A/dm
2, temperature is 10-40 ℃;
(4) adopt electric plating method to electroplate one deck electroless nickel layer at the copper electroplating layer that step (3) obtains, the technological parameter of electronickelling is: current density is 0.5-10A/dm
2, temperature is 20-70 ℃;
(5) electroless nickel layer that adopts electric plating method to obtain in step (4) is electroplated one deck electrogilding layer, and the technological parameter of electrogilding is: current density is 0.1-1.0A/dm
2, temperature is 20-70 ℃;
(6) photosensitive-ink in the non-conductive district of removal base material;
(7) adopt etching method to remove the Seed Layer in the non-conductive district of base material, namely get described wafer electronickelling gold product.
7. the preparation method of wafer electronickelling gold product according to claim 6 is characterized in that, the technological parameter of the electro-coppering in the step (3) is: current density is 1.0-3.0A/dm
2, temperature is 20-35 ℃; The technological parameter of electronickelling is in the step (4): current density is 1.0-3.0A/dm
2, temperature is 40-60 ℃; The technological parameter of electrogilding is in the step (5): current density is 0.2-0.5A/dm
2, temperature is 40-60 ℃.
8. the preparation method of each described wafer electronickelling gold product is characterized in that according to claim 6-7, and described step (7) also is included in the welding resistance district covering last layer soldering-resistance layer of electrogilding floor afterwards.
9. the preparation method of each described wafer electronickelling gold product is characterized in that according to claim 6-7, and described each step also comprises one or more in washing, wetting, preimpregnation or the baking step.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102348113A CN103311223A (en) | 2013-06-14 | 2013-06-14 | Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product |
| TW102130741A TW201448141A (en) | 2013-06-14 | 2013-08-28 | Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102348113A CN103311223A (en) | 2013-06-14 | 2013-06-14 | Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103311223A true CN103311223A (en) | 2013-09-18 |
Family
ID=49136272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013102348113A Pending CN103311223A (en) | 2013-06-14 | 2013-06-14 | Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN103311223A (en) |
| TW (1) | TW201448141A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576521A (en) * | 2015-01-27 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | TSV hole manufacturing technology |
| CN111636077A (en) * | 2020-06-05 | 2020-09-08 | 成都宏明双新科技股份有限公司 | Process for preventing ceramic chip from being plated with nickel or gold by creeping plating |
| CN112382579A (en) * | 2020-05-21 | 2021-02-19 | 深圳市创智成功科技有限公司 | Coating manufacturing process for wafer under bump metallization and coating structure thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07307550A (en) * | 1994-05-11 | 1995-11-21 | Toshiba Corp | Manufacture of electronic component |
| CN1542908A (en) * | 2003-04-17 | 2004-11-03 | �����ɷ� | Crystal circular/ chip distribution layer protecting method |
| CN101740420A (en) * | 2008-11-05 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Process for manufacturing copper strut |
| CN102548231A (en) * | 2010-12-23 | 2012-07-04 | 北大方正集团有限公司 | Method for manufacturing PCB (Printed Circuit Board) |
| CN102569236A (en) * | 2010-12-24 | 2012-07-11 | 三星电机株式会社 | Substrate for package and method for manufacturing the same |
-
2013
- 2013-06-14 CN CN2013102348113A patent/CN103311223A/en active Pending
- 2013-08-28 TW TW102130741A patent/TW201448141A/en unknown
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07307550A (en) * | 1994-05-11 | 1995-11-21 | Toshiba Corp | Manufacture of electronic component |
| CN1542908A (en) * | 2003-04-17 | 2004-11-03 | �����ɷ� | Crystal circular/ chip distribution layer protecting method |
| CN101740420A (en) * | 2008-11-05 | 2010-06-16 | 中芯国际集成电路制造(上海)有限公司 | Process for manufacturing copper strut |
| CN102548231A (en) * | 2010-12-23 | 2012-07-04 | 北大方正集团有限公司 | Method for manufacturing PCB (Printed Circuit Board) |
| CN102569236A (en) * | 2010-12-24 | 2012-07-11 | 三星电机株式会社 | Substrate for package and method for manufacturing the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104576521A (en) * | 2015-01-27 | 2015-04-29 | 华进半导体封装先导技术研发中心有限公司 | TSV hole manufacturing technology |
| CN112382579A (en) * | 2020-05-21 | 2021-02-19 | 深圳市创智成功科技有限公司 | Coating manufacturing process for wafer under bump metallization and coating structure thereof |
| CN112382579B (en) * | 2020-05-21 | 2022-02-15 | 深圳市创智成功科技有限公司 | Coating manufacturing process for wafer under bump metallization and coating structure thereof |
| CN111636077A (en) * | 2020-06-05 | 2020-09-08 | 成都宏明双新科技股份有限公司 | Process for preventing ceramic chip from being plated with nickel or gold by creeping plating |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI515853B (en) | 2016-01-01 |
| TW201448141A (en) | 2014-12-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101615789B1 (en) | Method of producing substrate for semiconductor element, and semiconductor device | |
| CN102263192B (en) | Light-emitting diode time substrate, LED package and manufacture method thereof | |
| CN103547063B (en) | Printed wiring board | |
| CN102468186A (en) | Manufacturing method of substrate and packaging method of semiconductor chip | |
| TWI831944B (en) | Lead frame | |
| US20050142836A1 (en) | Method of forming bump pad of flip chip and structure thereof | |
| CN100508148C (en) | Semiconductor package with contact support layer and method to produce the package | |
| CN103311223A (en) | Nickel and gold electroplating product of wafer and method for manufacturing nickel and gold electroplating product | |
| JP2017036501A5 (en) | ||
| CN102373492A (en) | Method for carrying out selective electroplating on surface of circuit board, and circuit board | |
| CN201887040U (en) | QFN/DFN (quad flat non-lead/dual flat non-lead) packaged integrated circuit using PCB (printed circuit board) as substrate | |
| CN105140140A (en) | Novel wafer level tin solder micro bump manufacturing method | |
| KR20170113180A (en) | Plating method | |
| TWI811532B (en) | Lead frame | |
| CN103400775B (en) | First it is honored as a queen and loses three-dimensional systematic flip-chip bump packaging structure and process | |
| CN203288585U (en) | A wafer electroplated nickel gold product | |
| US10312187B2 (en) | Multi-row wiring member for semiconductor device and method for manufacturing the same | |
| CN101908516B (en) | Tin-silver convex block structure of flip chip and manufacturing method thereof | |
| JP6616637B2 (en) | Method for forming conductive film on transparent conductive film | |
| US7442634B2 (en) | Method for constructing contact formations | |
| CN103547079B (en) | Method for manufacturing soft dielectric circuit | |
| KR20100033247A (en) | Structure for multi-row leadless lead frame and semiconductor package thereof and manufacture method thereof | |
| JP2015229775A (en) | Contact jig for electroplating, semiconductor production apparatus and production method of semiconductor device | |
| CN211654853U (en) | Ceramic substrate for UVLED packaging | |
| CN220934113U (en) | Micro LED packaging structure and display screen |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130918 |