CN103299291B - 分布式共享存储器多处理器中的分裂流量路由 - Google Patents

分布式共享存储器多处理器中的分裂流量路由 Download PDF

Info

Publication number
CN103299291B
CN103299291B CN201180064930.8A CN201180064930A CN103299291B CN 103299291 B CN103299291 B CN 103299291B CN 201180064930 A CN201180064930 A CN 201180064930A CN 103299291 B CN103299291 B CN 103299291B
Authority
CN
China
Prior art keywords
processor
node
flow
link
sacrifice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201180064930.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN103299291A (zh
Inventor
威廉·A·休斯
杨晨平
迈克尔·K·费尔蒂格
凯文·M·莱帕克
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN103299291A publication Critical patent/CN103299291A/zh
Application granted granted Critical
Publication of CN103299291B publication Critical patent/CN103299291B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306Intercommunication techniques
    • G06F15/17312Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
CN201180064930.8A 2010-12-15 2011-12-06 分布式共享存储器多处理器中的分裂流量路由 Active CN103299291B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/968,857 2010-12-15
US12/968,857 US20120155273A1 (en) 2010-12-15 2010-12-15 Split traffic routing in a processor
PCT/US2011/063463 WO2012082460A1 (en) 2010-12-15 2011-12-06 Split traffic routing in a distributed shared memory multiprocessor

Publications (2)

Publication Number Publication Date
CN103299291A CN103299291A (zh) 2013-09-11
CN103299291B true CN103299291B (zh) 2017-02-15

Family

ID=45406872

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201180064930.8A Active CN103299291B (zh) 2010-12-15 2011-12-06 分布式共享存储器多处理器中的分裂流量路由

Country Status (6)

Country Link
US (1) US20120155273A1 (ko)
EP (1) EP2652636B1 (ko)
JP (1) JP5795385B2 (ko)
KR (1) KR101846485B1 (ko)
CN (1) CN103299291B (ko)
WO (1) WO2012082460A1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9152595B2 (en) * 2012-10-18 2015-10-06 Qualcomm Incorporated Processor-based system hybrid ring bus interconnects, and related devices, processor-based systems, and methods
CN105594169A (zh) * 2013-11-07 2016-05-18 华为技术有限公司 用于流量分割的系统及方法
WO2015109010A1 (en) 2014-01-14 2015-07-23 Huawei Technologies Co., Ltd. System and method for device-to-device communications
CN112054961B (zh) * 2016-04-21 2023-12-08 华为技术有限公司 数据传输系统、方法及装置
CN106526461B (zh) * 2016-12-30 2018-12-28 盛科网络(苏州)有限公司 针对流量控制的嵌入式实时反压验证的方法
US10481915B2 (en) 2017-09-20 2019-11-19 International Business Machines Corporation Split store data queue design for an out-of-order processor
US11064418B2 (en) * 2019-09-09 2021-07-13 Analog Devices International Unlimited Company Two-hop wireless network communication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1988500A (zh) * 2005-12-19 2007-06-27 北京三星通信技术研究有限公司 分布式带宽管理方法
US7590090B1 (en) * 2007-01-17 2009-09-15 Lockhead Martin Corporation Time segmentation sampling for high-efficiency channelizer networks

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5859983A (en) * 1996-07-01 1999-01-12 Sun Microsystems, Inc Non-hypercube interconnection subsystem having a subset of nodes interconnected using polygonal topology and other nodes connect to the nodes in the subset
US5893153A (en) * 1996-08-02 1999-04-06 Sun Microsystems, Inc. Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control
US7103065B1 (en) * 1998-10-30 2006-09-05 Broadcom Corporation Data packet fragmentation in a cable modem system
US20020021745A1 (en) * 2000-04-07 2002-02-21 Negus Kevin J. Multi-channel-bandwidth frequency-hopping system
US6795875B2 (en) * 2000-07-31 2004-09-21 Microsoft Corporation Arbitrating and servicing polychronous data requests in direct memory access
US6738836B1 (en) * 2000-08-31 2004-05-18 Hewlett-Packard Development Company, L.P. Scalable efficient I/O port protocol
US7707305B2 (en) 2000-10-17 2010-04-27 Cisco Technology, Inc. Methods and apparatus for protecting against overload conditions on nodes of a distributed network
US7444404B2 (en) 2001-02-05 2008-10-28 Arbor Networks, Inc. Network traffic regulation including consistency based detection and filtering of packets with spoof source addresses
US20040114536A1 (en) * 2002-10-16 2004-06-17 O'rourke Aidan Method for communicating information on fast and slow paths
US7600023B2 (en) * 2004-11-05 2009-10-06 Hewlett-Packard Development Company, L.P. Systems and methods of balancing crossbar bandwidth
US7395361B2 (en) * 2005-08-19 2008-07-01 Qualcomm Incorporated Apparatus and methods for weighted bus arbitration among a plurality of master devices based on transfer direction and/or consumed bandwidth
US20080298246A1 (en) * 2007-06-01 2008-12-04 Hughes William A Multiple Link Traffic Distribution
US20090109969A1 (en) * 2007-10-31 2009-04-30 General Instrument Corporation Dynamic Routing of Wideband and Narrowband Audio Data in a Multimedia Terminal Adapter
US7958314B2 (en) * 2007-12-18 2011-06-07 International Business Machines Corporation Target computer processor unit (CPU) determination during cache injection using input/output I/O) hub/chipset resources
CN101751361B (zh) * 2008-12-16 2012-10-10 联想(北京)有限公司 控制移动终端中数据传输接口的切换方法及终端设备
US8565234B1 (en) * 2009-01-08 2013-10-22 Marvell Israel (M.I.S.L) Ltd. Multicast queueing in a switch
US8103809B1 (en) * 2009-01-16 2012-01-24 F5 Networks, Inc. Network devices with multiple direct memory access channels and methods thereof
US20110161592A1 (en) * 2009-12-31 2011-06-30 Nachimuthu Murugasamy K Dynamic system reconfiguration
US8250253B2 (en) * 2010-06-23 2012-08-21 Intel Corporation Method, apparatus and system for reduced channel starvation in a DMA engine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1988500A (zh) * 2005-12-19 2007-06-27 北京三星通信技术研究有限公司 分布式带宽管理方法
US7590090B1 (en) * 2007-01-17 2009-09-15 Lockhead Martin Corporation Time segmentation sampling for high-efficiency channelizer networks

Also Published As

Publication number Publication date
WO2012082460A1 (en) 2012-06-21
EP2652636B1 (en) 2018-10-03
EP2652636A1 (en) 2013-10-23
JP5795385B2 (ja) 2015-10-14
KR101846485B1 (ko) 2018-05-18
CN103299291A (zh) 2013-09-11
KR20140034130A (ko) 2014-03-19
JP2014506353A (ja) 2014-03-13
US20120155273A1 (en) 2012-06-21

Similar Documents

Publication Publication Date Title
CN103299291B (zh) 分布式共享存储器多处理器中的分裂流量路由
US8775764B2 (en) Memory hub architecture having programmable lane widths
TWI444023B (zh) 用於性能及流量知覺的異質互連網路的方法、設備以及系統
US8446824B2 (en) NUMA-aware scaling for network devices
US11494212B2 (en) Technologies for adaptive platform resource assignment
US10608876B2 (en) Software implementation of network switch/router
CN110120915A (zh) 高性能计算的三级成本效益分解和具有在线扩展灵活性的高容量存储器
US8930595B2 (en) Memory switch for interconnecting server nodes
US10749811B2 (en) Interface virtualization and fast path for Network on Chip
US9658960B2 (en) Subcache affinity
US11294850B2 (en) System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit
JP2017211984A (ja) 再構成可能なマルチポートを具備するPCIeストレージシステムのためのQoSを認識した入出力管理方法、管理システム、及び管理装置
CN106095696B (zh) 一种基于自适应路由及调度策略的高速缓存装置
US20190108143A1 (en) Method and Apparatus for In-Band Priority Adjustment Forwarding in a Communication Fabric
US8478920B2 (en) Controlling data stream interruptions on a shared interface
JP2016218635A (ja) 情報処理装置、メモリ制御装置、および情報処理装置の制御方法
JP2016076108A (ja) 情報処理装置、メモリ制御装置及び情報処理装置の制御方法
US9665518B2 (en) Methods and systems for controlling ordered write transactions to multiple devices using switch point networks
US11182325B1 (en) Memory centric computing storage controller system
CN105637483B (zh) 线程迁移方法、装置和系统
KR102517344B1 (ko) 병렬 처리 시스템 및 그 동작 방법
JP6991446B2 (ja) パケット処理装置及びそのメモリアクセス制御方法
US8074054B1 (en) Processing system having multiple engines connected in a daisy chain configuration

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant