CN103278759A - 分离soi器件中两种效应导致阈值电压漂移的方法 - Google Patents
分离soi器件中两种效应导致阈值电压漂移的方法 Download PDFInfo
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Abstract
本发明公开了一种分离HCI直流应力下SOI器件阈值电压漂移量的方法,属于半导体可靠性测试领域。该方法在SOI PMOSFET栅端和漏端同时加应力偏置下将HCI直流应力下HCI效应与NBTI效应对阈值电压漂移量影响分离,分别得到HCI效应和NBTI效应对应的阈值电压漂移量。采用本发明可以有助于更好的理解在VG=VD应力下HCI效应的退化机制,从而更好的对器件建模并更精确的预测器件的寿命。
Description
技术领域
本发明涉及半导体可靠性测试领域,主要针对SOI PMOSFET提出一种分别测出HCI与NBTI两种效应导致的阈值电压漂移的方法。
背景技术
从集成电路的发展来说,高性能和高可靠性是其发展的两个制高点。集成电路技术一方面朝着更大集成度和更高性价比的方向发展;另一方面,来自技术和市场的驱动要求可靠性不断提高,VLSI的可靠性研究日益受到人们的关注。集成电路的可靠性受到器件发展的不断影响,随着集成电路技术的不断进步,器件的特征尺寸不断减小和氧化层不断减薄,这就导致了器件内部电场和电流密度的不断增加,器件特性对缺陷的敏感度增加,使得诸多可靠性问题如热载流子效应(HCI)、负偏置不稳定性(NBTI)、栅氧经时击穿(TDDB)、电迁移(EM)等更加突出。
SOI是英文silicon on Insulator的缩写,指的是绝缘层上的硅。SOI CMOS器件具有功耗低、抗干扰能力强、集成密度高、速度高、工艺简单、抗辐射能力强,并彻底消除了体硅CMOS器件的寄生闩锁效应等优点。但是,由于SOI隐埋氧化层的低热导率,SOI器件存在自热效应,因此SOI器件可靠性研究比体硅复杂的多。
器件进入深亚微米阶段后,SOI器件的最坏应力偏置条件为VG=VD,此时器件性能退化最严重。当SOI PMOSFET加HCI直流应力VG=VD=Vstress时,由于其隐埋氧化层热导率较差,器件沟道温度升高,则在栅电压的垂直电场下会引发NBTI效应,两者共同引起器件阈值电压漂移,导致器件性能退化。因此分离出两种可靠性效应不仅有助于理解HCI直流应力下器件的退化机制,也有利于更精确的预测器件寿命。
发明内容
本发明在于提供一种在SOI PMOSFET栅端和漏端同时加应力偏置下分离出HCI效应与NBTI效应对阈值电压漂移影响的方法。
本方法的技术方案如下:
一种HCI直流应力下SOI器件中两种可靠性效应导致阈值电压漂移量的分离方法,具体方案流程如图1所示:
2)取与SOI PMOS器件A相同工艺及尺寸的SOI PMOS器件B加NBTI应力偏置VG=Vstress,VD=VS=0,应力温度T取器件A自热温度ΔTSH,测出SOI PMOS器件B的阈值电压漂移量该阈值电压漂移量等于SOI PMOS器件A中HCI直流应力下NBTI效应所产生的阈值电压漂移量;
3)用SOI PMOS器件A测出的HCI直流应力下测出的阈值电压漂移量减去SOI PMOS器件B测出的NBTI阈值电压漂移量即可分离出HCI效应导致的阈值电压漂移量,计算公式4如下:
本发明在SOI PMOSFET栅端和漏端同时加应力偏置,将HCI直流应力下HCI效应与NBTI效应对阈值电压漂移量影响分离,分别得到HCI效应和NBTI效应对应的阈值电压漂移量。采用本发明有助于更好的理解在VG=VD应力下HCI效应的退化机制,从而更好的对器件建模并更精确的预测器件的寿命。
附图说明
图1本发明技术方案流程示意图;
图2不同电压偏置下栅电阻随硅片温度的变化曲线;
图3提取自热温度与电压偏置的关系。
具体实施方式
下面通过具体的案例对本发明做进一步解释。
选取工艺为0.18μm的栅电极双引出PDSOI PMOSFET。
本发明采用栅电阻法提取SOI PMOSFET自热温度,假设栅电极温度等同于沟道温度。为防止多晶硅栅内在自热,栅电压选为VG1=VG+ΔVVG2=VG-ΔV,通过测量栅中流过的微小电流提取出栅电阻。公式1即为热阻与自热温度的关系。
ΔTSH=Rth×PdispPdisp=ID×VD (1)
①ΔTSH为器件自热温度,Rth为器件热阻,Pdisp为器件功耗,ID为器件漏端电流,VD为器件工作电压首先测试VG=VD=0没有自热效应时电阻随硅片温度变化的关系,提取出栅电阻变化量随温度的变化系数α,如公式2所示。不同电压偏置下栅电阻随衬底温度的变化曲线,如图2所示。
α为VGS=VDS=0时栅电阻变化量随温度的变化系数,Rg(Thigh)为VGS=VDS=0时高硅片温度下器件栅电阻,Rg(Tref)为VGS=VDS=0参照硅片温度下器件栅电阻,Thigh为高硅片温度,Tref为参照硅片温度
②选取器件A在室温下施加HCI直流应力VG1=-2.8V+20mV,VG2=-2.8V-20mV,VD=-2.8V,VS=0V经过t=6000s应力后撤去应力电压,测得阈值电压漂移量并且测量出器件栅电阻Rth=331.6Ω。根据公式(3)得出自热温度ΔTSH=141℃,其中取参照硅片温度为室温,提取出的室温下自热温度与偏置电压的关系如图3所示。
ΔT(SH)为器件自热温度,Rth为HCI应力参照硅片温度下器件栅电阻,Rg(Tref)为VGS=VDS=0时参照硅片温度下器件栅电阻,α为VGS=VDS=0时栅电阻变化量随温度的变化系数
③选取器件B施加NBTI应力VG=-2.8V,VD=VS=0V,T=ΔTSH=141℃,经过t=6000s应力后,去掉应力电压测量出阈值电压漂移量该阈值电压漂移量约等于器件A中HCI直流应力下NBTI效应产生的阈值电压漂移量。
上面描述的实施例并非用于限定本发明,任何本领域的技术人员,在不脱离本发明的精神和范围内,可做各种的更动和润饰,因此本发明的保护范围视权利要求范围所界定。
Claims (2)
1.一种HCI直流应力下SOI器件中两种可靠性效应导致阈值电压漂移量的分离方法,具体步骤为:
1)在SOI PMOS器件A的栅端和漏端施加HCI直流应力VG=VD=Vstress,VS=0测出阈值电压的漂移量量同时提取出器件的自热温度ΔTSH;
2)取与SOI PMOS器件A相同工艺及尺寸的SOI PMOS器件B加NBTI应力偏置VG=Vstress,VD=VS=0,应力温度T取SOI PMOS器件A自热温度ΔTSH,测出SOI PMOS器件B的阈值电压漂移量该阈值电压漂移量等于SOI PMOS器件A中HCI直流应力下NBTI效应所产生的阈值电压漂移量;
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US14/359,531 US20150219698A1 (en) | 2013-05-02 | 2013-06-05 | Method for separating threshold voltage shifts caused by two effects in soi device |
PCT/CN2013/076748 WO2014176812A1 (zh) | 2013-05-02 | 2013-06-05 | 分离soi器件中两种效应导致阈值电压漂移的方法 |
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CN105388353A (zh) * | 2015-11-26 | 2016-03-09 | 中国工程物理研究院电子工程研究所 | 一种抗噪声soi晶体管光电流测试系统设计 |
CN112560380A (zh) * | 2019-09-25 | 2021-03-26 | 天津大学 | 一种使用基于知识的神经网络的mos晶体管的射频参数退化模型 |
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CN109507560B (zh) * | 2018-11-08 | 2021-02-02 | 上海华力集成电路制造有限公司 | Mos管阈值电压的wat测试方法 |
CN112557734A (zh) * | 2020-12-07 | 2021-03-26 | 广州市耀安实业发展有限公司 | 风机电流检测方法、系统、计算机设备及存储介质 |
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