CN103268875A - 一种多晶片封装结构 - Google Patents

一种多晶片封装结构 Download PDF

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CN103268875A
CN103268875A CN2013102086943A CN201310208694A CN103268875A CN 103268875 A CN103268875 A CN 103268875A CN 2013102086943 A CN2013102086943 A CN 2013102086943A CN 201310208694 A CN201310208694 A CN 201310208694A CN 103268875 A CN103268875 A CN 103268875A
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bonding
wafer
substrate
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window
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CN103268875B (zh
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栗振超
户俊华
孟新玲
刘昭麟
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Poly Chip Technology Changzhou Co Ltd
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SHANDONG HUAXIN MICROELECTRONIC TECHNOLOGY Co Ltd
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Abstract

本发明公开了一种多晶片封装结构，包括具有相对的两面的基板，以及装于该基板上并与基板电路电性连接的两晶片，所述基板相对的两端部各开有一个窗口，且每面各设有一个所述的晶片，其中一个面为键合面，另一个面为外接端子面，从而，位于键合面上的晶片直接通过键合线键合，另一晶片通过穿过所述窗口的键合线键合。依据本发明在提高封装体晶片密度的情况下，工艺实现难度相对较低。

Description

一种多晶片封装结构
技术领域
本发明涉及一种多晶片封装结构。
背景技术
随着电子产业的蓬勃发展，电子科技不断地演进，电子产品也向着轻、薄、短、小的趋势设计。随着微小化以及高运作技术需求的增加，多个晶片会整合在一个封装构造内，以达到两倍以上的容量或者系统性的功能需求，例如在以往的多晶片堆叠封装构造中，其是将多个晶片堆叠并封胶在一封装材料内。
一般而言，在已知的多晶片封装技术之中常见如图1A所示的结构，使两晶片平行堆叠形态，其主要包含一基板10’，在该基板10’上堆叠的第一晶片1’和第二晶片14’，复数个焊线12’用于第一晶片1’及第二晶片14’与基板电路的连接，而在基板上设置复数个外接端子9’用于基板电路与外部电路的连接。
在上述结构中，两晶片均以打线结合技术（Wire Bonding）实现与基板上预设的金手指3’的电气连接。外接端子9’一般为焊锡球，位于基板第二表面10b’上，以供对外连接。该多晶片堆叠封装构造另包含一封胶体11’，形成于该基板第一表面，以密封两晶片。然而，该多晶片封装结构的体积会随着堆叠的晶片的增加而有非常明显增加，未能真正达到提高封装密度的目的。
由此可见，上述习知的多晶片封装技术并不同时具备高I/O密度的高功能与低成本的需求，为进一步减小最终封装厚度，提高晶片封装密度，本领域的技术人员考虑使用如图1B所示封装结构，是一基板10’的第一表面10a’贴第一晶片1’，第二表面10b’贴装第二晶片6’,两晶片均通过凸块3’倒装贴装于基板10’上，在第二晶片6’外围的基板10’上植外接端子9’实现与外界连接，第一晶片1’上方由塑封体11’包覆。
此种封装结构提高了封装密度，但由于凸块生成需要晶元级工艺，设备、技术成本要求较高，并且倒装贴片技术对于贴片（DIE Bond）工艺精度要求较高，均增加了工艺难度，实现成本高。
发明内容
因此，本发明的目的在于提供一种基于基板开窗的多晶片封装结构，在提高封装体晶片密度的情况下，工艺实现难度相对较低。
本发明采用以下技术方案：
一种多晶片封装结构，包括具有相对的两面的基板，以及装于该基板上并与基板电路电性连接的两晶片，所述基板相对的两端部各开有一个窗口，且每面各设有一个所述的晶片，其中一个面为键合面，另一个面为外接端子面，从而，位于键合面上的晶片直接通过键合线键合，另一晶片通过穿过所述窗口的键合线键合。
依据本发明，从上述结构可以看出，在基板上开有专用于打线的窗口，可以使用传统的打线技术，从而避免使用凸块生成及倒装贴片工艺，降低了工艺难度，从而降低了成本。另一方面，由于这种封装结构，两晶片紧贴基板，并以键合线电性连接，使得该封装结构具有较薄的厚度，更轻量化，从而提高了晶片的封装密度。
上述多晶片封装结构，所述基板电路至少具有两层电路布线，两面间开有用于容纳电路布线层间匹配连接电路的通孔。
上述多晶片封装结构，位于键合面上的晶片在开有窗口的两端方向上的宽度小于另一晶片在该方向上的宽度，进而，键合点分居于键合面上晶片安装位置的两侧，所述的一对窗口也分居于该两侧。
上述多晶片封装结构，所述键合点分为两组，一组靠近键合面上的晶片，用于该晶片的键合，另一组则分布于窗口周侧，用于另一晶片的键合。
上述多晶片封装结构，所述窗口为正交于两窗口间方向的长条窗口，匹配每一窗口在窗口间方向的两侧各有一排用于另一晶片键合的键合点。
上述多晶片封装结构，另一晶片在窗口间的方向上覆盖两窗口。
上述多晶片封装结构，另一晶片上用于键合的第一电极嵌埋入对应窗口内。
上述多晶片封装结构，用于键合的键合点为匹配键合线焊接的金手指，同时，所述键合线为金线。
上述多晶片封装结构，位于键合面上的晶片的主动面背向基板，而另一晶片的主动面则面向基板。
上述多晶片封装结构，外接端子面上的晶片的主动面面向基板。
附图说明
图1A是现有的一种多晶片堆叠封装结构示意图。
图1B是已知的一种多晶片堆叠倒装封装结构示意图。
图1C是依据本发明的一种开窗式多晶片堆叠封装结构剖面结构示意图。
图1D是依据本发明的一种开窗式多晶片堆叠封装结构中基板的顶面示意图。
具体实施方式
在一个层次上，如图1C所示，开窗式多晶片封装体是应用开窗式基板的设计，结合了廉价的打线键合技术（Wire Bonding）将至少两层晶片层叠结合设置在一起，且其中一晶片与焊锡球位于基板同侧，即增加了封装体的I/O密度及功能，又沿用了旧有的打金线技术及设备，避开了金属凸块生成及晶片倒装工艺，降低了工艺实现性难度，降低了生产成本。
为进一步阐述本发明为达成预定发明目的所采取的技术手段及功效，以下结合附图及较佳实施例，对依据本发明的多晶片封装结构其具体实施方式、结构、特征及其功效，详细说明如后。
依据本发明的第一具体实施例，揭示一种多晶片封装结构，图1C是该多晶片封装结构的截面示意图，图1D是为该多晶片封装结构中基板的顶面示意图。
首先请参阅附图1C所示，该多晶片封装结构其图示为本发明的较佳实施结构，本发明的开窗式多晶片堆叠封装体，主要包含一基板10，一第一晶片7，一第二晶片15，多数个外接端子—焊锡球9。
需要注意，基板10满足线路板的一般概念，按照通常的理解，其有且只有两个面，且表示为两个板面。
为了能够在以下的内容中明确区分，该基板10具有第一面10a及第二面10b，基板上两侧各有一穿透的开窗5，用于打线，那么金线3通过窗口5实现第一晶片7的电路信号得以传递至基板第一表面焊点金手指13。在图1C所示的结构中可以看出，金线3并不占据全部的窗口5的空间，剩余空间需要有填充物，或者说封装体所填充，保证金线3的键合后的可靠性。
传统的，该基板10内部有多个通孔17（via），以传递导通基板两层电路。
不过在本方案中，通孔17并不能代替窗口5，正如，传统基板都有通孔，仍然需要键合部分的电路、倒装部分的电路、凸块部分的电路一样，两者具有本质区别。
关于第一晶片7，该晶片与用作外接点的焊锡球9位于基板同侧，整体如附图1C和附图1D所示，能够有效利用基板空间。第一晶片7是具有一主动面7a以及复数个在该主动面7a上的第一电极7c，上述第一电极7c是可为焊垫，利用晶片黏着材料8的粘接，使得该第一晶片7的主动面7a是设置于该基板第二表面10b。
请参阅图1C所示，上述第一电极7c是设置于上述基板穿透开窗5内并与金线焊接，电性连接上述第一电极7c至该基板10的第一表面10a上的金手指13，实现与基板线路层的互连。
上述结构中，通过传统的金线焊接即可实现电气互连，故可省略凸块生成及倒装贴片工艺，降低工艺实现难度，降低成本。在本实施例中，该第一晶片7是遮盖上述基板两端开窗5，透过开窗5露出第一晶片7的第一焊点7c，实现在基板第一表面10a上金手指13进行金线焊接。
关于所述第二晶片15是具有一主动面15a以及复数个在该主动面15a上的第二电极15c，上述第二电极可为焊垫。利用一晶片黏着材料14的粘接，使得该第二晶片15的非主动面15b是设置于该基板10的第一表面10a。
请参阅图1C所示，该第二晶片15是可具有小于第一晶片的7的尺寸，以不影响另一晶片金线线弧。该晶片第二电极15c由金线12焊接于基板10a面上的电路布线金手指16上，以作电气连接。
上述外接端子焊锡球9是设置于该基板10，以供对外结合至一外部印刷电路板。在本实施例中，上述外接端子9，其是形成于基板第二表面10b，与第一晶片位于基板同侧，故可缩小封装体体积，增加塑封体的I/O密度。
因此，本实施例利用两晶片，即第一晶片7与第二晶片15分别以主动面及非主动面堆叠在基板10上，并且为简化结构并保证连接的可靠性，用以电性连接的第一电极7c嵌埋于基板10的开窗5内，得到一种全新的多晶片堆叠封装架构。
上述第一晶片7与第二晶片15将紧贴于基板10并以金线焊接匹配电性连接至该基板10的金手指13及金手指16，使该多晶片堆叠封装结构具有较薄厚度，更轻量化。此外，本实施例的结构设计同时沿用既有的封装制程与金线焊接设备，避免凸块生成及倒装贴片工艺，降低工艺实现难度，从而降低成本。
更具体而言，该多晶片堆叠封装结构另包含有一封装体11，其是形成于基板10第一表面10a全部，基板10第二表面10b根据第二晶片尺寸定义包覆尺寸，但不影响外界端子焊锡球9的设置，并填充于两晶片，即第一晶片7、第二晶片15与基板10结合金线3、金线12外围，填充于基板开口5。
以上所述，仅是本发明的较佳实施例而已，并非对本发明做任何形式上的限制，虽然本发明已以较佳实施例揭露如上，然而并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例，但凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (10)

1.一种多晶片封装结构，包括具有相对的两面的基板（10），以及装于该基板（10）上并与基板电路电性连接的两晶片，其特征在于，所述基板（10）相对的两端部各开有一个窗口（5），且每面各设有一个所述的晶片，其中一个面为键合面，另一个面为外接端子面，从而，位于键合面上的晶片直接通过键合线键合，另一晶片通过穿过所述窗口（5）的键合线键合。
2.根据权利要求1所述的多晶片封装结构，其特征在于，所述基板电路至少具有两层电路布线，两面间开有用于容纳电路布线层间匹配连接电路的通孔。
3.根据权利要求1或2所述的多晶片封装结构，其特征在于，位于键合面上的晶片在开有窗口的两端方向上的宽度小于另一晶片在该方向上的宽度，进而，键合点分居于键合面上晶片安装位置的两侧，所述的一对窗口（5）也分居于该两侧。
4.根据权利要求3所述的多晶片封装结构，其特征在于，所述键合点分为两组，一组靠近键合面上的晶片，用于该晶片的键合，另一组则分布于窗口周侧，用于另一晶片的键合。
5.根据权利要求4所述的多晶片封装结构，其特征在于，所述窗口（5）为正交于两窗口间方向的长条窗口，匹配每一窗口在窗口间方向的两侧各有一排用于另一晶片键合的键合点。
6.根据权利要求5所述的多晶片封装结构，其特征在于，另一晶片在窗口（5）间的方向上覆盖两窗口。
7.根据权利要求6所述的多晶片封装结构，其特征在于，另一晶片上用于键合的第一电极（7c）嵌埋入对应窗口（5）内。
8.根据权利要求1所述的多晶片封装结构，其特征在于，用于键合的键合点为匹配键合线焊接的金手指，同时，所述键合线为金线。
9.根据权利要求1所述的多晶片封装结构，其特征在于，位于键合面上的晶片的主动面背向基板（10），而另一晶片的主动面则面向基板（10）。
10.根据权利要求1、8或9所述的多晶片封装结构，其特征在于，外接端子面上的晶片的主动面面向基板。
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