CN103268138A - Pulse position coding synchronous head capture module and pulse position coding synchronous head capture method on basis of field programmable gate array (FPGA) design - Google Patents
Pulse position coding synchronous head capture module and pulse position coding synchronous head capture method on basis of field programmable gate array (FPGA) design Download PDFInfo
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Abstract
The invention discloses a pulse position coding synchronous head capture module and a pulse position coding synchronous head capture method on the basis of field programmable gate array (FPGA) design. The module comprises four functional units: a synchronous head pulse width screening unit, a pulse width cache unit, a synchronous head pulse interval timing unit and a synchronous head pulse width comparison unit. The capture method includes: the synchronous head pulse width screening unit screens a synchronous head P1 conforming to pulse width requirements from a pulse position coding sequence and caches the synchronous head P1 to the pulse width cache unit; and the synchronous head pulse interval timing unit starts up a counter to start timing, the pulse width cache unit outputs the synchronous head P1 and sends the synchronous head P1 to the synchronous head pulse width comparison unit after timing arrives at synchronous head pulse interval time, the synchronous head is compared with a pulse P2 input in real time, if the synchronous head and the pulse P2 can be coincided, and the synchronous head is captured successfully. The pulse position coding synchronous head capture module and the pulse position coding synchronous head capture method on the basis of the FPGA design greatly reduce occupation rate of PFGA logical resources, improve practicability, and optimize the FPGA design in projects.
Description
Technical field
The present invention relates to communicate by letter or the coding and decoding field, arteries and veins position of data transmission system, refer to an a kind of arteries and veins position code synchronism trapping module and catching method based on the FPGA design especially.
Background technology
In the information communication field, the method for data arteries and veins position coding and decoding more and more is subjected to researcher's attention.Data arteries and veins position coding and decoding method just refers to will be divided into the time slot of equal intervals the time earlier, select a fixing time slot to carry out the pulse emission for the data that need transmission, just produce an arteries and veins position coded pulse signal, this pulse signal difference because of the position on the residing time span of time slot represents the different values of information.Arteries and veins position coding is exactly that the pulse signal modulation that will transmit data arrives process with each time slot correspondence position; Decoding then is its inverse process, is solved the value of information of transmission data by the pulse signal position that receives.
Clearly, the take over party will solve arteries and veins position encoded digital information value, just must determine the position of pulse signal in time slot, and its key point is the zero-time position of clear and definite coded pulse.So, proposed before the data coded pulse, to add two fixed pulse width and fixed pulse signal at interval as the decoding synchronous head.Synchronous head is known for decoding side, then its after detecting synchronous head, the reference position of specified data pulse at an easy rate just, thus obtain corresponding transmitting data information.
In the method based on the data arteries and veins position coding and decoding of FPGA realized, pulse train synchronous head catching method was in occupation of consequence very.At present the basic procedure based on the synchronous head catching method of FPGA design is: be under the low level wait situation at signal wire at first, detect the high level of synchronous head P1, high level appears and after, calculate the pulse width of synchronous head P1 by counter; If width satisfies condition, calculate synchronous head interpulse period with counter again; If satisfy condition interval time, calculate the pulse width of synchronous head P2 again with counter, when above-mentioned condition all reaches requirement, show that then the synchronous head of this arteries and veins position coded pulse sequence is hunted down, ensuing pulse is arteries and veins position coded data information.
The loaded down with trivial details part of said method is: need repeatedly usage counter to judge whether synchronous head pulse width and recurrent interval meet the demands, it is more that program integral body takies the fpga logic resource, and trouble is revised and called to method, and transplantability is poor.
Summary of the invention
In order to overcome above-mentioned loaded down with trivial details design, the object of the present invention is to provide a kind of succinct, take the low arteries and veins position code synchronism trapping module based on the FPGA design of logical resource, comprise 4 parts: synchronous head pulsewidth screening unit, the pulsewidth buffer unit, synchronous head recurrent interval timing unit, synchronous head pulsewidth comparing unit; Wherein synchronous head pulsewidth screening unit is used for filtering out the synchronous head P1 that meets the pulsewidth requirement from arteries and veins position coded pulse sequence; Described synchronous head pulsewidth screening unit adopts the shift register pulsewidth of storage pulse sequence synchronous head P1.The pulsewidth buffer unit is used for the pulsewidth of buffer memory synchronous head P1, and when synchronous head reaches interpulse period the pulsewidth of output synchronous head P1; Synchronous head recurrent interval timing unit is used for the enabling counting device and picks up counting, and after timing time arrives the recurrent interval, makes the pulsewidth of pulsewidth buffer unit output synchronous head P1; Synchronous head pulsewidth comparing unit is used for the pulsewidth of synchronous head P1 is compared with the pulse P2 that imports in real time.
The synchronous head catching method of a described arteries and veins position code synchronism trapping module based on FPGA design comprises following steps:
A: synchronous head pulsewidth screening unit filters out from the coded sequence of arteries and veins position and meets the synchronous head P1 that pulsewidth requires, and compares with known synchronous head pulse P0, if identical, step below then continuing as difference, is then carried out this step again;
B: synchronous head P1 buffer memory is to the pulsewidth buffer unit;
C: synchronous head recurrent interval timing unit enabling counting device picks up counting, and timing is to synchronous head interpulse period;
D: pulsewidth buffer unit output synchronous head P1 also sends into synchronous head pulsewidth comparing unit;
E: synchronous head P1 and the pulse P2 of input in real time compare, if both can overlap, realize that then the success of synchronous head is caught.
The invention has the beneficial effects as follows: when realizing original functions of modules, reduced nearly 2/3rds fpga logic resources occupation rate, and promoted module than the practicality of IC circuit to actual engineering by the introducing of actual error scope, make that the FPGA design is optimized in the project.
Description of drawings
Fig. 1 is principle flow chart of the present invention.
Fig. 2 is arteries and veins position coded pulse sequence sequential synoptic diagram.
Embodiment
Below the present invention is described in detail.
Arteries and veins position code synchronism head based on the FPGA design of the present invention is caught and is mainly comprised 4 parts: synchronous head pulsewidth screening unit, pulsewidth buffer unit, synchronous head recurrent interval timing unit, synchronous head pulsewidth comparing unit.
Synchronous head pulsewidth screening unit uses a filter structure to filter out from the coded pulse sequence of arteries and veins position to meet the synchronous head P1 that pulsewidth requires, and with this synchronous head P1 buffer memory to the pulsewidth buffer unit.Described synchronous head pulsewidth screening unit can adopt shift register to catch the also pulsewidth of storage pulse sequence synchronous head P1.
The pulsewidth buffer unit is used for the pulsewidth of buffer memory synchronous head P1, and when synchronous head reaches interpulse period the pulsewidth of output synchronous head P1.Described pulsewidth buffer unit can use the FIFO memory approach to finish.
Synchronous head recurrent interval timing unit is used for the enabling counting device and picks up counting, and after timing time arrives the recurrent interval, makes the pulsewidth of pulsewidth buffer unit output synchronous head P1.Described synchronous head recurrent interval timing unit can utilize the register in the hardware description language to realize from adding counting.
Synchronous head pulsewidth comparing unit is used for the pulsewidth of pulsewidth buffer unit output P1 is compared with the pulse P2 that imports in real time.If both can overlap, the pulse that then shows real-time input is synchronous head P2, shows that namely preceding two pulses of this pulse train are the synchronous head that satisfies condition, thereby the success that realizes synchronous head is caught.
Below in conjunction with Fig. 1 the workflow of an aforesaid arteries and veins position code synchronism trapping module based on FPGA design is elaborated, mainly comprises following steps:
A: synchronous head pulsewidth screening unit uses a filter structure to filter out the synchronous head P1 that meets the pulsewidth requirement from the coded pulse sequence signal of input arteries and veins position, compare with known synchronous head pulse P0, if identical, step below then continuing, as difference, then carry out this step again.
B. with the synchronous head P1 buffer memory that filters out in the steps A to the pulsewidth buffer unit.
C. synchronous head recurrent interval timing unit enabling counting device picks up counting, and timing is to synchronous head interpulse period.
D. the pulsewidth buffer unit is exported synchronous head P1 and is sent into synchronous head pulsewidth comparing unit.
E. synchronous head P1 compares with the pulse P2 of input in real time, if both can overlap, the pulse that then shows real-time input is synchronous head P2, shows that namely preceding two pulses of this pulse train are the synchronous head that satisfies condition, thereby the success that realizes synchronous head is caught.
Described synchronous head pulsewidth screening unit.In the hardware description language design based on FPGA, utilize splicing operational symbol in position the pulse input to be spliced to the lowest order of pulsewidth shift register.After synchronous head P1 pulse signal width all enters shift register, utilize conditional operator to judge whether it is satisfactory synchronous head P1.Synchronous head pulsewidth screening unit can add and can accept the condition that error range is judged pulsewidth and recurrent interval coincidence in the actual engineering in the real work, and method for improving is than the practicality of IC circuit to actual engineering.
The present invention is further described in more detail for following example.
Fig. 2 is arteries and veins position coded pulse sequence sequential synoptic diagram, and P1, P2 are the coded sequence synchronous head pulse of arteries and veins position, D1, D2 ..., DN is the coded data pulse of arteries and veins position, L is the synchronous head pulse width, W
1Be synchronous head interpulse period, W
2Be synchronous head and first data pulse interval time, W
3Be adjacent data interpulse period.
Brilliant frequency M and synchronous head pulse width L that known fpga chip uses, the shift register figure place that the synchronous head that then meets the demands needs is m*K+2.
As, present embodiment supposes that specifically the crystal oscillator that fpga chip uses is 40
Mhz(system clock cycle is 25 ns), synchronous head pulse width L is 0.5us, and synchronous head recurrent interval W1 is 24 (us), and the shift register figure place that the synchronous head that then meets the demands needs is (40*0.5+2=22).Screening to synchronous head P1 is designed to hardware description language: the synchronous head P1 that establishes sign and be a pulse input signal, ruler and be 22 catches shift register (wherein each represents a crystal oscillator clock period, and the figure place of high level then can characterize the pulse input signal time width continuously).In each clock period, sign is loaded into the ruler register, and judges.If the most significant digit of rule and lowest order are high for low and middle 20, expression receives the synchronous head P1 that pulsewidth is 25ns * 20=0.5us, controls this synchronous head of FIFO buffer memory P1 this moment.
More excellent, the error range of accepting that adds actual transmissions is relaxed the judgement pulsewidth, can be designed as with hardware description language: increase the figure place to 24 that synchronous head P1 catches shift register.The same most significant digit and lowest order at rule is that middle 22 is 25ns * 22=0.55us pulse signal for high expression receives pulsewidth under the low situation; Middle higher 19 is 25ns * 19=0.475us pulse signal for high, low 3 for low expression receives pulsewidth.So judge by middle low 3 not stationary state, the front judged the synchronous head P1 of 500ns pulsewidth is loosened to: 475ns≤pulsewidth≤550ns.By this design, the raising method is to the practicality of actual engineering.
FIFO buffer based on the FPGA design can utilize IP kernel to realize.If use Quartus II software, can---MegaWizard Plug-In Manager---Memory Compiler---creates among the FIFO at tools.Also can oneself write respective code realizes.
Based on the synchronous head recurrent interval counter of FPGA design, be designed to hardware description language: establishing cnt is the recurrent interval counter of initial value 0, and FIFO_out is the FIFO output signal.When FIFO buffer memory synchronous head P1 indicates when effective, cnt begins counting, and each clock period is from adding 1.When counting down to 959, cnt (considers that FIFO buffer memory synchronous head P1 sign is owing to the reason of blocking assignment, 1 clock period can be postponed, revising count value is 958), 25ns * 960=24us has been passed through in expression, just synchronous head recurrent interval W1 controls the buffer memory FIFO_out that FIFO exports synchronous head P1 this moment.
Process that FIFO output signal and real-time input pulse are compared based on the FPGA design, be designed to hardware description language: establishing FIFO_out is the FIFO output signal, FIFO_ruler is 2 FIFO output buffers signal shift register, and old_ruler is 2 pulse signal input signal shift register.Same, in each clock period, sign is loaded into the old_ruler register, FIFO_out is loaded into the FIFO_ruler register, and judges.If the FIFO_ruler register equates with the value of old_ruler register, then catch the synchronous head success, otherwise failure.
More excellent, consider the synchronous head scope that interpulse period, error was accepted in the actual transmissions, be designed to hardware description language: increase the figure place to 5 of FIFO output buffers signal shift register FIFO_ruler, increase the figure place to 9 of pulse signal input signal shift register old_ruler.When P1 synchronous head delay 4 cycles (be the error range of 0.1us) of FIFO_ruler most significant digit for high expression FIFO storage, and then judge this moment, whether the synchronous head P2 of input occurred.If the P2 pulse occurs, then must there be continuous height to occur among 9 the old_ruler, so when the FIFO_ruler register equates with the value of old_ruler register, judge whether synchronous head recurrent interval error range under the situation of ± 0.1us, can capture this synchronous head.
Beneficial effect of the present invention is: when realizing original functions of modules, reduced nearly 2/3rds fpga logic resources occupation rate, and promoted module than the practicality of IC circuit to actual engineering by the introducing of actual error scope, make that the FPGA design is optimized in the project.
Exemplary embodiment described herein should only be regarded as descriptive nature, but not the purpose in order to limit.Therefore, it will be appreciated by the skilled addressee that and to carry out various modifications to form and details, and do not depart from the spirit and scope of the present invention of in appended claims and equivalent thereof, setting forth.
Claims (9)
1. arteries and veins position code synchronism trapping module based on FPGA design is characterized in that:
Comprise 4 parts: synchronous head pulsewidth screening unit, pulsewidth buffer unit, synchronous head recurrent interval timing unit, synchronous head pulsewidth comparing unit; Wherein
Synchronous head pulsewidth screening unit is used for filtering out the synchronous head P1 that meets the pulsewidth requirement from arteries and veins position coded pulse sequence;
The pulsewidth buffer unit is used for the pulsewidth of buffer memory synchronous head P1, and when synchronous head reaches interpulse period the pulsewidth of output synchronous head P1;
Synchronous head recurrent interval timing unit is used for the enabling counting device and picks up counting, and after timing time arrives the recurrent interval, makes the pulsewidth of pulsewidth buffer unit output synchronous head P1;
Synchronous head pulsewidth comparing unit is used for the pulsewidth of synchronous head P1 is compared with the pulse P2 that imports in real time.
2. an a kind of arteries and veins position code synchronism trapping module based on the FPGA design according to claim 1 is characterized in that: the pulsewidth of described synchronous head pulsewidth screening unit employing shift register storage pulse sequence synchronous head P1.
3. an a kind of arteries and veins position code synchronism trapping module based on FPGA design according to claim 1 is characterized in that: described synchronous head pulsewidth screening unit uses a filter structure to filter out from the coded pulse sequence of arteries and veins position to meet the synchronous head P1 that pulsewidth requires.
4. an a kind of arteries and veins position code synchronism trapping module based on FPGA design according to claim 1, it is characterized in that: described pulsewidth buffer unit uses the FIFO storer to store.
5. an a kind of arteries and veins position code synchronism trapping module based on FPGA design according to claim 1 is characterized in that: described synchronous head recurrent interval timing unit, can utilize the register in the hardware description language to realize from adding counting.
6. arteries and veins position code synchronism catching method based on the FPGA design that uses an a kind of arteries and veins position code synchronism trapping module based on the FPGA design as claimed in claim 2 is characterized in that: comprise following steps:
A: synchronous head pulsewidth screening unit filters out from the coded sequence of arteries and veins position and meets the synchronous head P1 that pulsewidth requires, and compares with known synchronous head pulse P0, if identical, step below then continuing as difference, is then carried out this step again;
B: synchronous head P1 buffer memory is to the pulsewidth buffer unit;
C: synchronous head recurrent interval timing unit enabling counting device picks up counting, and timing is to synchronous head interpulse period;
D: pulsewidth buffer unit output synchronous head P1 also sends into synchronous head pulsewidth comparing unit;
E: synchronous head P1 and the pulse P2 of input in real time compare, if both can overlap, realize that then the success of synchronous head is caught.
7. the arteries and veins position code synchronism catching method based on FPGA design according to claim 6, it is characterized in that: in steps A, described synchronous head pulsewidth comparing unit can be introduced synchronous head error interpulse period and relax the pulsewidth scope of judging described synchronous head P1.
8. the arteries and veins position code synchronism catching method based on FPGA design according to claim 6, it is characterized in that: in steps A, in the hardware description language design based on FPGA, utilize splicing operational symbol in position the pulse input to be spliced to the lowest order of the shift register of described synchronous head pulsewidth screening unit.
9. the arteries and veins position code synchronism catching method based on FPGA design according to claim 6, it is characterized in that: in steps A, after the deration of signal of described synchronous head P1 all enters the shift register of synchronous head pulsewidth screening unit, utilize conditional operator to judge whether it is satisfactory synchronous head pulse.
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| CN105162440A (en) * | 2015-08-21 | 2015-12-16 | 四川九洲电器集团有限责任公司 | Synchronous detection device |
| CN105656617A (en) * | 2016-01-06 | 2016-06-08 | 中国洛阳电子装备试验中心 | Time control pulse interval laser encoding and decoding method |
| CN114745029A (en) * | 2022-04-13 | 2022-07-12 | 北京盈通恒信电力科技有限公司 | Method, device and system for synchronization acquisition of narrowband power line communication |
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| CN101141238A (en) * | 2007-09-13 | 2008-03-12 | 中兴通讯股份有限公司 | Superframe frame synchronization method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105162440A (en) * | 2015-08-21 | 2015-12-16 | 四川九洲电器集团有限责任公司 | Synchronous detection device |
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| CN105656617A (en) * | 2016-01-06 | 2016-06-08 | 中国洛阳电子装备试验中心 | Time control pulse interval laser encoding and decoding method |
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| CN114745029A (en) * | 2022-04-13 | 2022-07-12 | 北京盈通恒信电力科技有限公司 | Method, device and system for synchronization acquisition of narrowband power line communication |
| CN114745029B (en) * | 2022-04-13 | 2024-04-16 | 北京天润旺林科技有限公司 | Method, device and system for synchronous acquisition of narrowband power line communication |
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Application publication date: 20130828 |