CN105162440A - Synchronous detection device - Google Patents
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- CN105162440A CN105162440A CN201510519999.5A CN201510519999A CN105162440A CN 105162440 A CN105162440 A CN 105162440A CN 201510519999 A CN201510519999 A CN 201510519999A CN 105162440 A CN105162440 A CN 105162440A
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Abstract
The invention discloses a synchronous detection device. The synchronous detection device comprises a pulse shaping module and a synchronous judgement module, wherein the pulse shaping module is used for outputting a standard double-pulse synchronous header signal based on a received double-pulse synchronous signal; and the synchronous judgement module is connected with the pulse shaping module and used for judging whether the standard double-pulse synchronous header signal satisfies a pre-set synchronous judgement condition or not. The synchronous detection device provided by the invention is used for solving the technical problem that a double-pulse signal synchronous method is lacking in the prior art; and thus, the technical effect of accurately synchronizing double-pulse signals is realized.
Description
Technical field
The present invention relates to electronic technology field, particularly a kind of sync detection device.
Background technology
Along with the development of science and technology, the communication technology is constantly progress also, and pulse signal, as a kind of carrier of information, is widely used in the communications field.Pulse signal is a kind of discrete signal, and shape is varied, as pulse signal comprises single pulse signal, dipulse signal.Dipulse signal refers to generation two pulse signals in one-period, and the width of two pulses is identical, and the time interval between two pulses can be arbitrary interval.
When adopting dipulse signal to communicate, need synchronously to detect dipulse signal, but lack in the prior art synchronous method is carried out to dipulse signal.
Summary of the invention
The embodiment of the present application provides a kind of sync detection device, for solving the shortage that exists in prior art dipulse signal being carried out to the technical problem of synchronous method, achieving the technique effect of accurate synchronization dipulse signal.
The embodiment of the present application provides a kind of sync detection device, comprising:
Shaping pulse module, for based on the dipulse synchronizing signal received, outputting standard dipulse synchronous head signal;
Synchronization decisions module, is connected with described shaping pulse module, for judging whether described standard dipulse synchronous head signal meets pre-determined synchronization judgment condition.
Optionally, described device also comprises:
Postpone output module, be connected with described synchronization decisions module, for when described standard dipulse synchronous head signal meets described pre-determined synchronization judgment condition, receive by the sync id signal of described synchronization decisions CMOS macro cell, and delay disposal is carried out to described sync id signal, the sync id signal after output delay.
Optionally, described device also comprises:
Clock module, for providing identical operating clock signals to described shaping pulse module, described synchronization decisions module, described delay output module, to make described shaping pulse module, described synchronization decisions module, the concurrent working of described delay output module.
Optionally, described shaping pulse module is used for: when the synchronous head pulse signal of described dipulse synchronizing signal meets default shaping judgment condition, export described standard dipulse synchronous head signal.
Optionally, described shaping pulse module comprises:
M bit shift register, for the described synchronous head pulse signal corresponding with work at present clock signal being stored in the 1st trigger in M bit shift register, and by corresponding with a upper operating clock signals and be stored in described 1st trigger to the data mobile in the trigger of W position to the 2nd trigger in the trigger of W+1 position, wherein, M, W is positive integer, and M is greater than W.
Optionally, described shaping pulse module also comprises:
Reshaping signal output module, when the data for storing in described M bit shift register meet described default shaping judgment condition, exports described standard dipulse synchronous head signal.
Optionally, described reshaping signal output module is used for:
The data stored in described M bit shift register meet first and preset shaping judgment condition or the data that store in described M bit shift register and meet second when presetting shaping judgment condition, output pulse width is the high level of a described operating clock signals length, and when not meeting described first and presetting shaping judgment condition, output pulse width is the low level of a described operating clock signals length.
Optionally, described first default shaping judgment condition is when the rising edge of described synchronous head pulse arrives, the data stored in described 1st trigger in described M bit shift register are 0, and to get i be successively 2 to N+1, and the data stored in i-th trigger are 1; Described second default shaping judgment condition is when the trailing edge of described synchronous head pulse arrives, the data that described W+1 position trigger in described M bit shift register stores are 0, and to get i be successively 0 to N-1, in the trigger of W-i position, the data of poke are 1, wherein, N is the positive integer being less than or equal to W.
Optionally, described synchronization decisions module comprises:
S bit shift register, for the described standard dipulse synchronous head signal corresponding with work at present clock signal being stored in the 1st trigger in S bit shift register, and by corresponding with a upper operating clock signals and be stored in described 1st trigger to the data mobile in the trigger of I+J position to the 2nd trigger in the trigger of I+J+1 position;
Wherein, I is the pulse spacing of described synchronous head pulse and the ratio in described operating clock signals cycle, and J is the maximum time scope and the ratio in described operating clock signals cycle that described lock-out pulse allows shake.
Optionally, described synchronization decisions module also comprises:
Synchronizing signal output module, when the data for storing in described S bit shift register meet described synchronization decisions condition, exports described sync id signal.
Optionally, described synchronizing signal output module is used for:
When the data stored in described S bit shift register meet described synchronization decisions condition, output pulse width is the high level of a described operating clock signals length, and when not meeting described synchronization decisions condition, output pulse width is the low level of a described operating clock signals length.
Optionally, described synchronization decisions condition is: the data that described 1st trigger in described S bit shift register stores are 1, and have at least the data stored in a trigger to be 1 in I-J position trigger to described I+J position trigger.
Optionally, described delay output module comprises:
Counter, for when the rising edge of described sync id signal arrives, perform initialization operation and start counting, wherein, the count frequency of described counter is identical with the frequency of described operating clock signals.
Optionally, described delay output module comprises:
Inhibit signal output module, for exporting the sync id signal after described delay.
Optionally, described inhibit signal output module is used for: when the count value of described counter reaches default output delay parameter value, output pulse width is the high level of a described operating clock signals length, and when the count value of described counter does not reach described default output delay parameter, output pulse width is the low level of a described operating clock signals length.
Above-mentioned one or more technical scheme in the embodiment of the present application, at least has one or more technique effects following:
One, the scheme in the embodiment of the present application, by shaping pulse module, carry out Shape correction, outputting standard dipulse synchronous head signal, and whether criterion dipulse synchronous head signal meets pre-determined synchronization judgment condition to the dipulse synchronizing signal received.Then showing that when meeting described pre-determined synchronization judgment condition this dipulse signal is the signal that needs receive, then showing that when not meeting described pre-determined synchronization judgment condition this dipulse signal is not the signal that needs receive.And when meeting described pre-determined synchronization judgment condition, this signal is received and subsequent treatment.Visible, the scheme in the embodiment of the present application effectively can solve the shortage existed in prior art carries out synchronous method technical problem to dipulse signal, achieves the technique effect of accurate synchronization dipulse signal.
Two, the shaping pulse module in the embodiment of the present application comprises M bit shift register, synchronization decisions module comprises S bit shift register, postpone output module and comprise counter, the feature of the pulse signal that user can be synchronous according to actual needs specifically arranges the value of register and counter.Therefore, the scheme in the embodiment of the present application can realize the technique effect of the parameters of flexible configuration synchronizing indicator.
Three, the synchronizing indicator in the embodiment of the present application is due to can flexible configuration parameters, therefore be convenient at any a FPGA (FieldProgrammableGateArray, field programmable gate array) on transplant, without the need to redesigning testing circuit according to FPGA, achieve and shorten the construction cycle, reduce the technique effect of design cost.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only the embodiment of the present application, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
The structured flowchart of the first sync detection device that Fig. 1 provides for the embodiment of the present application one;
The structured flowchart of the second sync detection device that Fig. 2 provides for the embodiment of the present application one;
The structured flowchart of the third sync detection device that Fig. 3 provides for the embodiment of the present application one;
The specific implementation structured flowchart of the first sync detection device that Fig. 4 provides for the embodiment of the present application one;
What for the application, Fig. 5 implemented that an example provides carries out the synchronous particular flow sheet detected to dipulse synchronizing signal;
Fig. 6 is in the embodiment of the present application one when the rising edge of dipulse synchronizing signal triggers default shaping judgment condition, and dipulse synchronizing signal exports schematic diagram through the signal of sync detection device process;
Fig. 7 is in the embodiment of the present application one when the trailing edge of dipulse synchronizing signal triggers default shaping judgment condition, and dipulse synchronizing signal exports schematic diagram through the signal of sync detection device process.
Embodiment
The embodiment of the present application provides a kind of sync detection device, for solving the shortage that exists in prior art dipulse signal being carried out to the technical problem of synchronous method, achieving the technique effect of accurate synchronization dipulse signal.
Technical scheme in the embodiment of the present application is solve above-mentioned technical problem, and general thought is as follows:
A kind of sync detection device, comprising: shaping pulse module, for based on the dipulse synchronizing signal received, and outputting standard dipulse synchronous head signal; Synchronization decisions module, is connected with described shaping pulse module, for judging whether described standard dipulse synchronous head signal meets pre-determined synchronization judgment condition.
In such scheme, by shaping pulse module, Shape correction is carried out to the dipulse synchronizing signal received, outputting standard dipulse synchronous head signal, and whether criterion dipulse synchronous head signal meets pre-determined synchronization judgment condition.Then showing that when meeting described pre-determined synchronization judgment condition this dipulse signal is the signal that needs receive, then showing that when not meeting described pre-determined synchronization judgment condition this dipulse signal is not the signal that needs receive.And when meeting described pre-determined synchronization judgment condition, this signal is received and subsequent treatment.Visible, the scheme in the embodiment of the present application effectively can solve the shortage existed in prior art carries out synchronous method technical problem to dipulse signal, achieves the technique effect of accurate synchronization dipulse signal.
In order to better understand technique scheme, below by accompanying drawing and specific embodiment, technical solution of the present invention is described in detail, the specific features being to be understood that in the embodiment of the present application and embodiment is the detailed description to technical solution of the present invention, instead of the restriction to technical solution of the present invention, when not conflicting, the technical characteristic in the embodiment of the present application and embodiment can combine mutually.
Embodiment one
Please refer to Fig. 1, the embodiment of the present application provides a kind of sync detection device, comprising:
Shaping pulse module 10, for based on the dipulse synchronizing signal received, outputting standard dipulse synchronous head signal;
Synchronization decisions module 20, is connected with described shaping pulse module 10, for judging whether described standard dipulse synchronous head signal meets pre-determined synchronization judgment condition.
Please refer to Fig. 2, described device also comprises:
Postpone output module 30, be connected with described synchronization decisions module 20, for when described standard dipulse synchronous head signal meets described pre-determined synchronization judgment condition, receive by the sync id signal of described synchronization decisions CMOS macro cell, and delay disposal is carried out to described sync id signal, the sync id signal after output delay.
In specific implementation process, the synchronous detection that described sync detection device can realize dipulse signal based on FPGA.For dipulse synchronizing signal, comprise synchronous head pulse and information pulse, in communication process, must by after synchronous head pulse accurate synchronization, the correct transmission information of ability.Therefore, after sync detection device receives dipulse synchronizing signal, first analyzing and processing to be carried out to synchronous head pulse.
As shown in Figure 3, normally work to enable modules, sync detection device also comprises: clock module 40, for providing identical operating clock signals to described shaping pulse module 10, described synchronization decisions module 20, described delay output module 30, to make described shaping pulse module 10, described synchronization decisions module 20, the concurrent working of described delay output module 30.
Specifically, described clock module 40 can be clock oscillation circuit, and user can determine frequency of oscillation according to actual needs accurately.When rising edge or the trailing edge arrival of clock signal, modules write data.In the embodiment of the present application, with the frequency of clock signal for 100MHz, namely the cycle of clock signal is 10ns is example, is described the synchronous detection of dipulse signal.
When described sync detection device receives dipulse synchronizing signal, first dipulse synchronizing signal is sent into shaping pulse module 10 and do Shape correction.When the synchronous head pulse signal of described dipulse synchronizing signal meets default shaping judgment condition, export described standard dipulse synchronous head signal.
Further, described shaping pulse module 10 comprises: M bit shift register 11, for the described synchronous head pulse signal corresponding with work at present clock signal being stored in the 1st trigger in described M bit shift register 11, and by corresponding with a upper operating clock signals and be stored in described 1st trigger to the data mobile in the trigger of W position to the 2nd trigger in the trigger of W+1 position, wherein, M, W are positive integer, and M is greater than W.
Specifically, suppose that the pulse duration of the dipulse synchronizing signal received is the length of 160 clock signals, namely clock-pulse width is 160 × 10ns=1.6us; The length of 1000 clock signals that what synchronous head was interpulse be spaced apart, i.e. 1000 × 10ns=10us; Lock-out pulse jitter scope is the length of 10 clock signals, i.e. 10 × 10ns=0.1us.
In specific implementation process, S
0represent dipulse synchronizing signal, as shown in Figure 4, Figure 5, every trigger A in described M bit shift register 11
irepresent, i is more than or equal to the positive integer that 1 is less than or equal to M.For described M bit shift register for rising edge clock signal triggers, when the rising edge of first clock signal arrives, the current data (supposing that current data is 1) of synchronous head signal is stored into the 1st trigger A
1in, now, A
1in data be 1.When the rising edge of second clock signal arrives, the current data (supposing that current data is still 1) of synchronous head signal is stored into the 1st trigger A
1in, a upper clock signal is stored into A simultaneously
1in data mobile to the 2nd trigger A
2in, now, A
1data be 1, A
2data be 1.When the rising edge of the 3rd clock signal arrives, the current data (supposing that current data is 0) of synchronous head signal is stored into the 1st trigger A
1in, a upper clock signal is stored into A simultaneously
1and A
2in data move to A respectively
2and A
3in.Now, the 1st trigger, the 2nd trigger, the data in the 3rd trigger are respectively 0,1,1.By that analogy, when each operating clock signals arrives, the data corresponding with work at present clock signal are moved into A
1, and by corresponding with a upper operating clock signals and be stored in A
1to A
win data according to A
i+1=A
imode move on to A
2to A
w+1in.
The effect of shaping pulse module 10 is the interference in order to eliminate spurious signal.In the transmitting procedure of dipulse synchronizing signal, the impact of environment or other factors may be subject to, produce some burr pulses.In order to get rid of the interference of the spurious signals such as burr pulse, spurious signal can be eliminated by shaping judgment condition.
In the embodiment of the present application, described shaping pulse module 10 also comprises: reshaping signal output module 12, when the data for storing in described M bit shift register 11 meet described default shaping judgment condition, exports described standard dipulse synchronous head signal.
Concrete, described reshaping signal output module 12 for: in described M bit shift register 11 store data meet first preset shaping judgment condition or in described M bit shift register 11 store data meet second preset shaping judgment condition time, output pulse width is the high level of a described operating clock signals length, and when not meeting described first and presetting shaping judgment condition, output pulse width is the low level of a described operating clock signals length.
Wherein, described first default shaping judgment condition is when the rising edge of described synchronous head pulse arrives, the data stored in described 1st trigger in described M bit shift register 11 are 0, and to get i be successively 2 to N+1, and the data stored in i-th trigger are 1; Described second default shaping judgment condition is when the trailing edge of described synchronous head pulse arrives, the data that described W+1 position trigger in described M bit shift register stores are 0, and to get i be successively 0 to N-1, in the trigger of W-i position, the data of poke are 1, wherein, N is the positive integer being less than or equal to W.
In specific implementation process, user can arrange the value of N to limit the width of true pulse signal.As when N is set to 100, be only real synchronization pulse during with regard to meaning and only having the width of pulse signal to be more than or equal to 100, the signal that pulse duration is less than 100 is the spurious signals such as burr signal.And only when pulse signal is actual signal, described reshaping signal output module just meeting output pulse width is the high level of a described operating clock signals length (namely width is 10ns), equal output low level in other cases.Certainly, the value of N can be configured according to actual conditions, and if N is 75,135 etc., the application is not specifically limited.But the value of N should for being less than or equal to the positive integer of W, and the value of W also can be arranged according to actual needs, in the embodiment of the present application, the value of W is set to the pulse duration being no more than dipulse synchronizing signal, and namely W is less than or equal to 160.Further, the value of M is to be arranged to infinitely-great in theory, and for the ease of to the configuration of default shaping judgment condition and adjustment, namely configure the number of available shift register, the value of M can be set to the positive integer being greater than W, and namely M is greater than 160.
Specifically, shaping judgement can have been come by shaping judging module, as shown in Figure 4.Preset shaping judgment condition and can be divided into two kinds of situations, a kind of rising edge by described dipulse synchronizing signal triggers, and as shown in Figure 6, a kind of trailing edge by described dipulse synchronizing signal triggers, as shown in Figure 7.
Please refer to Fig. 5, Fig. 6, for the pulse duration of dipulse synchronizing signal for W, when the rising edge of dipulse synchronizing signal triggers, as shown in Figure 6, show that when pulse duration is greater than N this pulse signal is real pulse signal, namely the data having N continuous trigger to store in shift register are 1, and be that the rising edge of pulse signal triggers to represent, the data of the therefore last position trigger storage of an above-mentioned N continuous trigger should be 0.Namely the first default shaping judgment condition is the data stored in the 1st trigger is that the data stored in the 0,2nd trigger to the N number of trigger of N+1 position this continuous print of trigger are 1.Namely the first default shaping judgment condition is A
1be 0, A
2to A
n+1be 1.And when meeting first and presetting shaping judgment condition, export the high level of an operating clock signals length.When namely occurring N number of 1 in Fig. 6 continuously after rising edge arrives, exporting a width is the high level of 10ns.CLK in Fig. 6 represents clock signal.
When the trailing edge of dipulse synchronizing signal triggers shaping judgment condition, please refer to Fig. 5, Fig. 7, show that when pulse duration is greater than N this pulse signal is real pulse signal equally, namely the data having a N continuous trigger to store in shift register are 1, being that the trailing edge of pulse signal triggers to represent, should be 0 in the data of rear trigger storage of an above-mentioned N continuous trigger.Namely the second default shaping judgment condition is the data stored in the trigger of W+1 position is that the data stored in the 0, the W position trigger to the N number of trigger of W-N+1 position this continuous print of trigger are 1.Namely the second default shaping judgment condition is A
w+1be 0, A
wto A
w-N+1be 1.And when meeting second and presetting shaping judgment condition, export the high level of an operating clock signals length.When namely occurring N number of 1 in Fig. 7 continuously before trailing edge arrives, exporting a width is the high level of 10ns.CLK in Fig. 7 represents clock signal.
Further, in Fig. 5 to Fig. 7, use S
1expression standard dipulse synchronizing signal, described standard dipulse synchronous head signal is the above-mentioned high level exporting an operating clock signals length when synchronous head pulse signal meets default shaping judgment condition, the pulse signal of output low level when not meeting.
Next, to described standard dipulse synchronous head signal S
1carry out synchronization decisions process.Described synchronization decisions module 20 comprises: S bit shift register 21, for the described standard dipulse synchronous head signal corresponding with work at present clock signal being stored in the 1st trigger in S bit shift register, and by corresponding with a upper operating clock signals and be stored in described 1st trigger to the data mobile in the trigger of I+J position to the 2nd trigger in the trigger of I+J+1 position; Wherein, I is the pulse spacing of described synchronous head pulse and the ratio in described operating clock signals cycle, and J is the maximum time scope and the ratio in described operating clock signals cycle that described lock-out pulse allows shake.
In specific implementation process, as shown in Figure 4, every trigger B in described S bit shift register 21
irepresent, i is more than or equal to the positive integer that 1 is less than or equal to S.When each operating clock signals arrives, the current data of standard dipulse synchronous head signal is moved into described S bit shift register.If current data is 0, be then stored into the 1st trigger B by 0
1in, and by last operating clock signals stored at B
1in data (as 1), move to the 2nd trigger B
2in.By that analogy, when each operating clock signals arrives, the data corresponding with work at present clock signal are moved into B
1, and by corresponding with a upper operating clock signals and be stored in B
1to B
i+Jin data according to B
i+1=B
imode move on to B
2to B
i+J+1in.In concrete movement rule and shaping pulse module 10, the operation principle of shift register is similar, is not just repeating at this.
Further, stating synchronization decisions module 20 and also comprise: synchronizing signal output module 22, when the data for storing in described S bit shift register 21 meet described synchronization decisions condition, exporting described sync id signal.Described synchronization decisions condition is: the data that described 1st trigger in described S bit shift register 21 stores are 1, and have at least the data stored in a trigger to be 1 in I-J position trigger to described I+J position trigger.
Due to standard synchronizing signal can because of the reasons such as interference cause between lock-out pulse between be interposed between I left and right fluctuation, so the ability in order to strengthen this fluctuation of synchronization decisions resume module, when adjudicating synchronous, as long as the pulse spacing between lock-out pulse is being more than or equal to I-J, be less than or equal in the scope of I+J, be all judged to be the dipulse synchronous head receiving a standard.That is at B
i-Jto B
i+Jin have at least the value of a trigger to be 1.Synchronization decisions can be realized by synchronization decisions module, as shown in Figure 4.In the embodiment of the present application, with I, to be 1000, J be 10 for example, then the scope in pulse spacing is 9990 ~ 1010, and that is, as long as the 9990th trigger is in these 20 triggers of the 1010th trigger, the data having the trigger of more than to store are 1.Also here, the numerical value of J can flexible configuration, and the application is not specifically limited.
Further, described synchronizing signal output module 22 for: in described S bit shift register 21 store data meet described synchronization decisions condition time, output pulse width is the high level of a described operating clock signals length, and when not meeting described synchronization decisions condition, output pulse width is the low level of a described operating clock signals length.
Please refer to Fig. 6 and Fig. 7, at described 9990th trigger in these 20 triggers of the 1010th trigger, when the data having the trigger of more than to store are 1, synchronizing signal output module then exports the high level of an operating clock signals length (10ns), in other cases equal output low level.In Fig. 5 to Fig. 7, use S
2represent sync id signal, that is, described sync id signal is the above-mentioned high level exporting an operating clock signals length when standard dipulse synchronous head signal meets pre-determined synchronization judgment condition, the pulse signal of output low level when not meeting.
Next, sync id signal S is exported in synchronization decisions module 20
2after, described delay output module 30 receives described sync id signal, and carries out delay disposal to described sync id signal.
Due to dipulse synchronizing signal what follow below is information pulse, and sync id signal is for information reads the identifier providing an accurate original position.Suppose the position of information pulse 100 work clock pulse durations after dipulse synchronizing signal, but synchronization decisions module 20 export sync id information time after dipulse synchronizing signal the position of 1 work clock pulse duration.Therefore, need to postpone sync id signal, postpone 99 work clock pulse durations.
Described delay output module 30 comprises: counter 31, and for when the rising edge of described sync id signal arrives, perform initialization operation and start counting, wherein, the count frequency of described counter is identical with the frequency of described operating clock signals.
In specific implementation process, counter is made up of basic counting unit and some control gates, counting unit is then made up of a series of all kinds of triggers with storage informational function, and these triggers have rest-set flip-flop, T trigger, d type flip flop and JK flip-flop etc.Those skilled in the art can select dissimilar counter according to actual needs, and the application is not specifically limited.
In order to realize postponing sync id signal, when the rising edge of sync id signal arrives, counter 31 performs initialization operation, carries out reset operation by each trigger.And count according to the carrying out of described operating clock signals, that is often arrive an operating clock signals, counter performs and adds 1 operation.To include 3 triggers in counter, when the rising edge of sync id signal arrives, trigger resets, and the data of this hour counter are 000.When the trailing edge of first job clock signal arrives (trailing edge triggering), the data of counter are 001, when the trailing edge of second operating clock signals arrives, the data of counter are 010, by that analogy, not through the trailing edge of an operating clock signals, counter does and adds 1 process.As shown in Figure 4, include X trigger in counter 31, those skilled in the art can come as required to the number X in register in counter, and the application does not do specific requirement.
Described delay output module 30 also comprises: inhibit signal output module 32, for exporting the sync id signal after described delay.Described inhibit signal output module 32 for: when the count value of described counter 31 reaches default output delay parameter value, output pulse width is the high level of a described operating clock signals length, and when the count value of described counter does not reach described default output delay parameter, output pulse width is the low level of a described operating clock signals length.
Specifically, user can arrange default output delay parameter value according to actual conditions, as when needs by as described in as described in sync id signal delay 50 during operating clock signals length, when the count value of counter is 50, export the high level (10ns) of an operating clock signals length, when the count value of described counter does not reach described default output delay parameter, output low level.In the above described manner, export the sync id signal after described delay, in Fig. 5 to Fig. 7, use S
3represent the sync id signal after described delay, D represents default output delay parameter.
In the embodiment of the present application, the dipulse synchronizing signal that user can receive as required specifically arranges the quantity of trigger in M bit shift register, S bit shift register, also can arrange the quantity X of trigger in counter.Because the sync detection device in the embodiment of the present application can be applied in FPGA, after solidification, according to circumstances flexible configuration can be carried out in order to meet user, need the storage bit number of shift register sum counter large as much as possible, in the embodiment of the present application, as long as meet pulse duration K, the S that M is greater than dipulse synchronizing signal to be more than or equal to I+J, preset output delay parameter value D and be less than or equal to 2
x-1.By being the quantity N of the trigger of 1 continuously in adjustment K, I, J, D and shaping judgment condition, the dipulse synchronizing signal detected is adjusted.Certainly, except above-mentioned optimum configurations scope, those skilled in the art can carry out specifically to arrange the scope of each parameter as required, and the application is not specifically limited.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (15)
1. a sync detection device, comprising:
Shaping pulse module, for based on the dipulse synchronizing signal received, outputting standard dipulse synchronous head signal;
Synchronization decisions module, is connected with described shaping pulse module, for judging whether described standard dipulse synchronous head signal meets pre-determined synchronization judgment condition.
2. device as claimed in claim 1, it is characterized in that, described device also comprises:
Postpone output module, be connected with described synchronization decisions module, for when described standard dipulse synchronous head signal meets described pre-determined synchronization judgment condition, receive by the sync id signal of described synchronization decisions CMOS macro cell, and delay disposal is carried out to described sync id signal, the sync id signal after output delay.
3. device as claimed in claim 2, it is characterized in that, described device also comprises:
Clock module, for providing identical operating clock signals to described shaping pulse module, described synchronization decisions module, described delay output module, to make described shaping pulse module, described synchronization decisions module, the concurrent working of described delay output module.
4. device as claimed in claim 3, it is characterized in that, described shaping pulse module is used for: when the synchronous head pulse signal of described dipulse synchronizing signal meets default shaping judgment condition, export described standard dipulse synchronous head signal.
5. the device as described in claim arbitrary in claim 1-4, is characterized in that, described shaping pulse module comprises:
M bit shift register, for the described synchronous head pulse signal corresponding with work at present clock signal is stored into described M bit shift deposit in the 1st trigger in, and by corresponding with a upper operating clock signals and be stored in described 1st trigger to the data mobile in the trigger of W position to the 2nd trigger in the trigger of W+1 position, wherein, M, W is positive integer, and M is greater than W.
6. device as claimed in claim 5, it is characterized in that, described shaping pulse module also comprises:
Reshaping signal output module, when the data for storing in described M bit shift register meet described default shaping judgment condition, exports described standard dipulse synchronous head signal.
7. device as claimed in claim 6, it is characterized in that, described reshaping signal output module is used for:
The data stored in described M bit shift register meet first and preset shaping judgment condition or the data that store in described M bit shift register and meet second when presetting shaping judgment condition, output pulse width is the high level of a described operating clock signals length, and when not meeting described first and presetting shaping judgment condition, output pulse width is the low level of a described operating clock signals length.
8. device as claimed in claim 7, it is characterized in that, described first default shaping judgment condition is when the rising edge of described synchronous head pulse arrives, the data stored in described 1st trigger in described M bit shift register are 0, and to get i be successively 2 to N+1, the data stored in i-th trigger are 1; Described second default shaping judgment condition is when the trailing edge of described synchronous head pulse arrives, the data that described W+1 position trigger in described M bit shift register stores are 0, and to get i be successively 0 to N-1, in the trigger of W-i position, the data of poke are 1, wherein, N is the positive integer being less than or equal to W.
9. the device as described in claim arbitrary in claim 1-3, is characterized in that, described synchronization decisions module comprises:
S bit shift register, for the described standard dipulse synchronous head signal corresponding with work at present clock signal being stored in the 1st trigger in S bit shift register, and by corresponding with a upper operating clock signals and be stored in described 1st trigger to the data mobile in the trigger of I+J position to the 2nd trigger in the trigger of I+J+1 position;
Wherein, I is the pulse spacing of described synchronous head pulse and the ratio in described operating clock signals cycle, and J is the maximum time scope and the ratio in described operating clock signals cycle that described lock-out pulse allows shake.
10. device as claimed in claim 9, it is characterized in that, described synchronization decisions module also comprises:
Synchronizing signal output module, when the data for storing in described S bit shift register meet described synchronization decisions condition, exports described sync id signal.
11. devices as claimed in claim 10, it is characterized in that, described synchronizing signal output module is used for:
When the data stored in described S bit shift register meet described synchronization decisions condition, output pulse width is the high level of a described operating clock signals length, and when not meeting described synchronization decisions condition, output pulse width is the low level of a described operating clock signals length.
12. devices as claimed in claim 11, it is characterized in that, described synchronization decisions condition is: the data that described 1st trigger in described S bit shift register stores are 1, and have at least the data stored in a trigger to be 1 in I-J position trigger to described I+J position trigger.
13. devices as described in claim arbitrary in claim 1-3, it is characterized in that, described delay output module comprises:
Counter, for when the rising edge of described sync id signal arrives, perform initialization operation and start counting, wherein, the count frequency of described counter is identical with the frequency of described operating clock signals.
14. devices as claimed in claim 13, it is characterized in that, described delay output module comprises:
Inhibit signal output module, for exporting the sync id signal after described delay.
15. devices as claimed in claim 14, it is characterized in that, described inhibit signal output module is used for: when the count value of described counter reaches default output delay parameter value, output pulse width is the high level of a described operating clock signals length, and when the count value of described counter does not reach described default output delay parameter, output pulse width is the low level of a described operating clock signals length.
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| CN111273233A (en) * | 2020-03-04 | 2020-06-12 | 北京环境特性研究所 | Asynchronous pulse detection method and device for electronic corner reflector |
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