CN103258311A - Pixel misplacement adjustment method of infrared long-line detector - Google Patents

Abstract

The invention discloses a pixel misplacement adjustment method of a multi-piece-spliced infrared long-line detector. The method is mainly used for a scanning imaging system of the infrared long-line detector. According to the technical scheme, the method mainly includes the following steps: (1) misplacement parameters are adjusted in real time by means of a micro processor (Micro Blaze) in an FPGA; (2) DDR2SDRAM is read by means of a memory controller (Memory Control Block, MCB) so that large misplacement among modules of the long-line detector is adjusted; (3) adjustment of small misplacement inside the modules is achieved through a block memory (Block RAM) built in the FPGA; (4) data are sent to a main unit for display by means of a PCI Express protocol. The method has the advantages that by means of ping-pong buffer, the DDR2SDRAM and the PCI Express protocol, data transmission with a high data rate can be achieved, the misplacement parameters can be adjusted in real time through the embedded micro processor, the long-line detectors with different module quantities can be compatible, the modularization degree is high, and reusability is good.

Description

A kind of pixel dislocation method of adjustment of infrared long detector array

Technical field

The present invention relates to transmission and the demonstration of the infrared long alignment image of multi-disc splice type, is a kind of pixel dislocation method of adjustment specifically.It is mainly used in adjusting infrared long detector array because the pixel spatial offset that factors such as manufacturing and splicing process cause.

Background technology

Infrared long detector array mainly obtains infrared image by scanning.Infrared radiation converts electric signal to through infrared eye, read by sensing circuit then and carry out analog to digital conversion, the digital signal of exporting after the analog to digital conversion through adjustment and pre-service after be transferred to that the rear end is used for showing or further processing.Want correct demonstration and handle infrared image, at first must adjust the spatial offset of detector array pixel.

The scheme of in the past adjusting infrared long detector array pixel dislocation is: raw image data is directly deposited external memory storage in proper order, according to the positional information of detector pixel, read from the corresponding position of storer one by one then; Perhaps earlier according to the pixel positional information, the formula of filling a vacancy data are stored into the storer relevant position, just can read complete columns certificate in proper order after the multiple row continuously.These methods mainly are to adopt SRAM or FLASH as external memory storage, the big shearing of detector array intermodule and the little dislocation in the module are adjusted together, the detector that differs bigger for super long alignment and pixel position then needs very big storage space, address read-write also needs time of more growing, the infrared image transmission system of improper high-speed real-time one by one.And suppose that mostly each module big shearing all is the same with mistake position parameter, adjust underaction.

Therefore, design a kind of fast and flexible and to adjust the high pixel dislocation method of adjustment of precision very necessary.The scheme that adopts DDR2 SDRAM and Block RAM to adjust big shearing and little dislocation respectively can be given full play to the speed advantage of DDR2 SDRAM burst read-write, suitable high speed infrared transmission system.Also can make the dislocation adjustment convenient flexibly to the reasonable division of each module of detector and the application of embedded microprocessor (MicroBlaze) when programming simultaneously.

Summary of the invention

Purpose of the present invention is to propose the method for adjustment that a kind of infrared long detector array pixel misplaces, and realizes high-speed transfer, processing and the demonstration of infrared picture data.

For achieving the above object, hardware platform of the present invention mainly comprises, a slice FPGA, a slice DDR2SDRAM and a PC.。

Each hardware components need satisfy: described FPGA must have abundant logical resource, and Memory Controller module (MCB) is arranged, PCI Express endpoint module (Endpoint Block), and support embedded microprocessor (MicroBlaze).Described DDR2 sdram size should be enough big, can store the view data of certain columns.Described main frame must be supported PCI Express interface.Described peripheral interface mainly comprises serial ports, SPI interface, socket etc.

The annexation that each hardware is formed is: infrared eye output is connected with FPGA by socket after analog to digital conversion; FPGA realizes the read-write of DDR2 SDRAM is controlled by embedded Memory Controller module (MCB); FPGA is by PCI Express endpoint module transmission data; FPGA is mutual by embedded microprocessor (MicroBlaze) control serial ports realization and main frame.The concrete flow process of implementing of the present invention is as follows:

(1) make up data reception module, the serial data that analog to digital converter (ADC) is exported converts parallel data to, and to its ping-pong buffer;

(2) utilize the embedded Memory Controller of FPGA (MCB) that each frame data is stored in the corresponding address of DDR2SDRAM, adjust the big shearing of long each intermodule of detector array;

(3) data that will adjust big shearing read back into the corresponding address of the built-in block storage of FPGA (Block RAM) from external memory storage DDR2SDRAM, adjust the little dislocation of each inside modules pixel;

(4) utilize the PCI Express endpoint module of FPGA, data are sent to main frame show;

(5) by embedded microprocessor (MicroBlaze) control serial ports, realize communicating by letter with serial port of host computer, real time modifying dislocation parameter is up to not dislocation of the image that shows.

Distinguishing feature of the present invention is as follows:

(1) scheme of employing Module Division, the output of each module of long detector array is corresponded to each passage of Memory Controller module (MCB) respectively, by its inner self-built scheduling mechanism, realization is to the read-write of DDR2SDRAM, programming is simple, easy operating, and because the division of module, make software architecture be fit to the detector array of disparate modules number, reusability is good.

(2) adopt the scheme of big shearing and little dislocation being separated processing, can guarantee continuous batch read-write DDR2SDRAM to greatest extent, give full play to the advantage of DDR2SDRAM burst read-write, shortened the processing time greatly, be fit to the higher Infrared Transmission system of data transfer rate.

(3) adjust the precision height, can realize the dislocation adjustment of a minimum pixel; Adjust flexibly, the dislocation parameter of each module can be adjusted separately, by observing image, can proofread and correct the pixel dislocation of long detector array rapidly.

Description of drawings

Fig. 1 is the system chart that infrared long detector array pixel dislocation is adjusted.

Fig. 2 is the process flow diagram that infrared long detector array pixel dislocation is adjusted.

Embodiment

With reference to the accompanying drawings the specific embodiment of the present invention is further described below.

Fig. 1 is the system chart that infrared long detector array pixel dislocation is adjusted.The hardware platform that adopts of the present invention mainly comprises: a slice FPGA, a slice DDR2 SDRAM and a PC and other peripheral interfaces.

Described fpga chip has been selected the XCS6LX100T-FGG676 of Xilinx Spartan-6 series for use, this model FPGA has abundant logical resource, can be used for making up internal buffer and built-in block storage (Block RAM), with the adjustment of little dislocation in the buffer memory of realizing data and the module; 4 Memory Controller modules (MCB) are arranged, can control outside DDR2SDRAM storer very easily, realize the adjustment of intermodule big shearing; Also have a PCI Express endpoint module can realize PCI Express agreement, transfer data to main frame and show; This FPGA supports embedded microprocessor (MicroBlaze) simultaneously, can build the software platform of system very easily.

Described DDR2 SDRAM chip has been selected the MT47H32M16-37E of Micron company for use, and this model DDR2SDRAM total volume is 512Mbits, can realize the dislocation adjustment that the module locus differs greatly.

Described PC must be supported PCI Express interface, and USB or RS232 serial ports are arranged.

Described peripheral interface comprises: the socket that is connected with analog to digital converter, and with the mutual serial ports of main frame, JTAG mouth etc.

Fig. 2 is the process flow diagram that infrared long detector array pixel dislocation is adjusted.

The software platform of FPGA module is based on that embedded microprocessor (MicroBlaze) builds, on microprocessor carry various IP kernels, mainly comprise serial ports nuclear (UART), external memory controller (ExternalMemory Controller, EMC), interruptable controller, multiport memory controller (Multi-PortMemory Controller, MPMC) etc.UART receives the various command that main frame is sent, comprising detector integrates time and row cycle being set, dislocation parameter etc. being set; EMC is primarily implemented between software and the FPGA hardware logic and transmits parameter; Interruptable controller mainly is the interruption of control serial ports and timer interruption etc.; MPMC realizes Memory Controller module (MCB), the read-write of control DDR2SDRAM.

The hardware logic of FPGA module mainly comprises 4 functional modules: mistake position module and data transmission blocks in data reception module, the adjustment of intermodule big shearing, the module.

Because long detector array generally all is to be spliced by a lot of modules, and each module divides the pixel output of odd even road again, therefore adopts the analog to digital converter (ADC) of serial output can reduce interface quantity, thus the simplification board design.The function of data reception module is the serial data that receives the A/D conversion, and converts serial data to parallel data, according to putting in order of pixel it is carried out ping-pong buffer then.Ping-pong operation is by at FPGA internal build buffer memory, and the highest addresses line negate of buffer memory is realized, when when handling the former frame data, current frame data still can not conflict deposits buffer memory in, thereby realizes high-speed data transmission.

Because the locus of long each module of detector array is not on same straight line, the scenery that each module is seen at one time is not also on same straight line, so the image that scans misplaces.The function of big shearing adjusting module is exactly to revise the position deviation of long each intermodule of detector array, and the image that makes it to scan out is significantly dislocation not.Memory Controller module (MCB) is configured to 6 subscriber channels, and wherein 5 are used for writing data to DDR2 SDRAM, also has one to be used for data are read from DDR2 SDRAM.The big shearing adjusting module is read data from each buffer memory, write subscriber channel for 5 that correspond to Memory Controller module (MCB) respectively, and deposit in the corresponding address of DDR2SDRAM like according to the spatial positional information of pixel data being filled in a form, after the multiframe data deposit in, just have complete columns certificate in the storer, so just realized the adjustment of intermodule big shearing.

Because the pixel in each module of long detector array is that the branch odd even is read, so strange row pixel and even row pixel also must be on same straight lines, the adjustment of little dislocation is exactly the position deviation of revising pixel in each module of long detector array in the module.The data that call over from DDR2 SDRAM are exactly to have adjusted the picturewide certificate of big shearing, spatial positional information according to pixel in each module deposits these columns certificates in the corresponding address of the built-in block storage of FPGA (Block RAM) in, can realize the adjustment of little dislocation in the module.

The function of data transmission blocks is exactly that the logical embedded PCI Express endpoint module of the FPGA view data that will adjust the pixel dislocation sends to main frame and shows.

An example of the present invention is as follows:

Adopt 2560 yuan of long wavelength's detector array, this detector is spliced by 10 modules, 256 yuan of each modules, and the branch parity column is read.

System's analog to digital converter adopts the AD9259 of AD company, and this chip has 4 autonomous channels, every passage 14bits, LVDS output, and the highest sample frequency reaches 50MSPS.The method of the invention adjustment is adopted in the pixel dislocation, 10 modules are corresponded to 5 AD9259 respectively, the output of 5 AD9259 is gone here and there respectively and conversion and buffer memory, passage 1-5 by Memory Controller module (MCB) writes into DDR2SDRAM then, for each write access, write 512 data and only need switch 512/64=8 first address (the MCB read-write FIFO degree of depth is 64).Then data are read from passage 0, owing to be to read continuously, only need switch 2560/64=40 time first address when reading frame data.Adjust the data of too small dislocation and deliver to the main frame demonstration again, by observing image, determine that it is 82 pixels that the present invention adopts the big shearing between detector module at last, the little dislocation in the module is 8 pixels.

Claims (1)

1. the pixel of infrared long detector array dislocation method of adjustment is characterized in that may further comprise the steps:

(1) make up data reception module, the serial data that analog to digital converter is exported converts parallel data to, and to its ping-pong buffer;

(2) utilize the embedded Memory Controller of FPGA that each frame data is stored in the corresponding address of DDR2 SDRAM, adjust the big shearing of long each intermodule of detector array;

(3) data that will adjust big shearing read back into the corresponding address of the built-in block storage of FPGA from external memory storage DDR2 SDRAM, adjust the little dislocation of each inside modules pixel;

(4) utilize the PCI Express endpoint module of FPGA, data are sent to main frame show;

(5) by embedded microprocessor control serial ports, realize communicating by letter with serial port of host computer, real time modifying dislocation parameter is up to not dislocation of the image that shows.

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